Lachezar Lechev 7be63b3468

fix: spi transfer bug and additions to test ...

Signed-off-by: Lachezar Lechev <elpiel93@gmail.com>

2023-03-26 18:14:17 +03:00

..

dma_copy_async.rs

Add HIL tests of DMA & UART, and correctly set DREQ for uart DMA

2022-08-26 12:55:15 +02:00

flash.rs

Add delay to flash test to allow time to parse RTT header

2022-10-27 12:49:20 +02:00

gpio_async.rs

Replace futures::future::join -> embassy_futures::join::join.

2022-09-22 16:48:35 +02:00

gpio.rs

rp: add OutputOpenDrain input test.

2022-12-06 21:09:27 +01:00

multicore.rs

Refactor after review

2022-12-13 13:49:51 +01:00

spi_async.rs

fix: spi transfer bug and additions to test

2023-03-26 18:14:17 +03:00

spi.rs

Cleanup examples

2022-09-01 15:12:44 +02:00

uart_buffered.rs

rp/uart: use lockfree ringbuffer.

2022-11-25 22:30:47 +01:00

uart_dma.rs

Add HIL tests of DMA & UART, and correctly set DREQ for uart DMA

2022-08-26 12:55:15 +02:00

uart_upgrade.rs

Add HIL test for into_buffered uart on embassy-rp

2023-03-14 12:46:58 +01:00

uart.rs

Add HIL tests of DMA & UART, and correctly set DREQ for uart DMA

2022-08-26 12:55:15 +02:00