185 lines
4.2 KiB
Rust
185 lines
4.2 KiB
Rust
use stm32_metapac::rcc::vals::{Pllsrc, Sw};
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use crate::pac::{FLASH, RCC};
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use crate::rcc::{set_freqs, Clocks};
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use crate::time::Hertz;
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/// HSI speed
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pub const HSI_FREQ: Hertz = Hertz(16_000_000);
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/// LSI speed
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pub const LSI_FREQ: Hertz = Hertz(32_000);
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pub use crate::pac::pwr::vals::Vos as VoltageScale;
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pub use crate::pac::rcc::vals::{Hpre as AHBPrescaler, Ppre as APBPrescaler};
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#[derive(Copy, Clone)]
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pub enum ClockSrc {
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HSE(Hertz),
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HSI16,
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}
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#[derive(Clone, Copy, Debug)]
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pub enum PllSrc {
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HSE(Hertz),
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HSI16,
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}
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impl Into<Pllsrc> for PllSrc {
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fn into(self) -> Pllsrc {
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match self {
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PllSrc::HSE(..) => Pllsrc::HSE32,
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PllSrc::HSI16 => Pllsrc::HSI16,
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}
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}
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}
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impl Into<Sw> for ClockSrc {
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fn into(self) -> Sw {
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match self {
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ClockSrc::HSE(..) => Sw::HSE32,
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ClockSrc::HSI16 => Sw::HSI16,
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}
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}
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}
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trait Div {
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fn div(&self) -> u8;
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}
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impl Div for APBPrescaler {
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fn div(&self) -> u8 {
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match self {
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Self::DIV1 => 1,
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Self::DIV2 => 2,
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Self::DIV4 => 4,
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Self::DIV8 => 8,
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Self::DIV16 => 16,
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_ => unreachable!(),
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}
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}
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}
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impl Div for AHBPrescaler {
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fn div(&self) -> u8 {
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match self {
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Self::DIV1 => 1,
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Self::DIV2 => 2,
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Self::DIV4 => 4,
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Self::DIV8 => 8,
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Self::DIV16 => 16,
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_ => unreachable!(),
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}
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}
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}
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#[derive(Copy, Clone)]
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pub struct Config {
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pub mux: ClockSrc,
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pub ahb_pre: AHBPrescaler,
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pub apb1_pre: APBPrescaler,
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pub apb2_pre: APBPrescaler,
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pub apb7_pre: APBPrescaler,
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}
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impl Default for Config {
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fn default() -> Self {
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Self {
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mux: ClockSrc::HSI16,
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ahb_pre: AHBPrescaler::DIV1,
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apb1_pre: APBPrescaler::DIV1,
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apb2_pre: APBPrescaler::DIV1,
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apb7_pre: APBPrescaler::DIV1,
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}
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}
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}
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pub(crate) unsafe fn init(config: Config) {
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let sys_clk = match config.mux {
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ClockSrc::HSE(freq) => {
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RCC.cr().write(|w| w.set_hseon(true));
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while !RCC.cr().read().hserdy() {}
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freq.0
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}
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ClockSrc::HSI16 => {
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RCC.cr().write(|w| w.set_hsion(true));
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while !RCC.cr().read().hsirdy() {}
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HSI_FREQ.0
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}
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};
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// TODO make configurable
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let power_vos = VoltageScale::RANGE1;
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// states and programming delay
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let wait_states = match power_vos {
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VoltageScale::RANGE1 => match sys_clk {
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..=32_000_000 => 0,
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..=64_000_000 => 1,
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..=96_000_000 => 2,
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..=100_000_000 => 3,
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_ => 4,
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},
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VoltageScale::RANGE2 => match sys_clk {
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..=8_000_000 => 0,
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..=16_000_000 => 1,
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_ => 2,
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},
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};
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FLASH.acr().modify(|w| {
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w.set_latency(wait_states);
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});
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RCC.cfgr1().modify(|w| {
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w.set_sw(config.mux.into());
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});
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RCC.cfgr2().modify(|w| {
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w.set_hpre(config.ahb_pre.into());
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w.set_ppre1(config.apb1_pre.into());
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w.set_ppre2(config.apb2_pre.into());
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});
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RCC.cfgr3().modify(|w| {
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w.set_ppre7(config.apb7_pre.into());
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});
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let ahb_freq: u32 = sys_clk / config.ahb_pre.div() as u32;
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let (apb1_freq, apb1_tim_freq) = match config.apb1_pre.div() {
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1 => (ahb_freq, ahb_freq),
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div => {
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let freq = ahb_freq / div as u32;
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(freq, freq * 2)
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}
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};
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let (apb2_freq, apb2_tim_freq) = match config.apb2_pre.div() {
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1 => (ahb_freq, ahb_freq),
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div => {
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let freq = ahb_freq / div as u32;
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(freq, freq * 2)
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}
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};
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let (apb7_freq, _apb7_tim_freq) = match config.apb7_pre.div() {
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1 => (ahb_freq, ahb_freq),
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div => {
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let freq = ahb_freq / div as u32;
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(freq, freq * 2)
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}
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};
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set_freqs(Clocks {
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sys: Hertz(sys_clk),
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ahb1: Hertz(ahb_freq),
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ahb2: Hertz(ahb_freq),
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ahb4: Hertz(ahb_freq),
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apb1: Hertz(apb1_freq),
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apb2: Hertz(apb2_freq),
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apb7: Hertz(apb7_freq),
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apb1_tim: Hertz(apb1_tim_freq),
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apb2_tim: Hertz(apb2_tim_freq),
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});
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}
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