596 lines
21 KiB
Rust
596 lines
21 KiB
Rust
use core::slice;
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use embassy_futures::select::{select3, Either3};
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use embassy_net_driver_channel as ch;
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use embassy_sync::pubsub::PubSubBehavior;
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use embassy_time::{block_for, Duration, Timer};
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use embedded_hal_1::digital::OutputPin;
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use crate::bus::Bus;
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pub use crate::bus::SpiBusCyw43;
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use crate::consts::*;
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use crate::events::{EventQueue, EventStatus};
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use crate::fmt::Bytes;
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use crate::ioctl::{IoctlState, IoctlType, PendingIoctl};
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use crate::nvram::NVRAM;
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use crate::structs::*;
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use crate::{events, Core, CHIP, MTU};
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#[cfg(feature = "firmware-logs")]
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struct LogState {
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addr: u32,
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last_idx: usize,
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buf: [u8; 256],
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buf_count: usize,
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}
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#[cfg(feature = "firmware-logs")]
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impl Default for LogState {
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fn default() -> Self {
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Self {
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addr: Default::default(),
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last_idx: Default::default(),
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buf: [0; 256],
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buf_count: Default::default(),
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}
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}
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}
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pub struct Runner<'a, PWR, SPI> {
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ch: ch::Runner<'a, MTU>,
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bus: Bus<PWR, SPI>,
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ioctl_state: &'a IoctlState,
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ioctl_id: u16,
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sdpcm_seq: u8,
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sdpcm_seq_max: u8,
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events: &'a EventQueue,
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#[cfg(feature = "firmware-logs")]
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log: LogState,
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}
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impl<'a, PWR, SPI> Runner<'a, PWR, SPI>
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where
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PWR: OutputPin,
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SPI: SpiBusCyw43,
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{
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pub(crate) fn new(
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ch: ch::Runner<'a, MTU>,
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bus: Bus<PWR, SPI>,
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ioctl_state: &'a IoctlState,
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events: &'a EventQueue,
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) -> Self {
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Self {
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ch,
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bus,
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ioctl_state,
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ioctl_id: 0,
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sdpcm_seq: 0,
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sdpcm_seq_max: 1,
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events,
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#[cfg(feature = "firmware-logs")]
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log: LogState::default(),
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}
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}
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pub(crate) async fn init(&mut self, firmware: &[u8]) {
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self.bus.init().await;
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// Init ALP (Active Low Power) clock
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self.bus
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.write8(FUNC_BACKPLANE, REG_BACKPLANE_CHIP_CLOCK_CSR, BACKPLANE_ALP_AVAIL_REQ)
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.await;
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info!("waiting for clock...");
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while self.bus.read8(FUNC_BACKPLANE, REG_BACKPLANE_CHIP_CLOCK_CSR).await & BACKPLANE_ALP_AVAIL == 0 {}
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info!("clock ok");
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let chip_id = self.bus.bp_read16(0x1800_0000).await;
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info!("chip ID: {}", chip_id);
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// Upload firmware.
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self.core_disable(Core::WLAN).await;
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self.core_reset(Core::SOCSRAM).await;
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self.bus.bp_write32(CHIP.socsram_base_address + 0x10, 3).await;
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self.bus.bp_write32(CHIP.socsram_base_address + 0x44, 0).await;
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let ram_addr = CHIP.atcm_ram_base_address;
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info!("loading fw");
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self.bus.bp_write(ram_addr, firmware).await;
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info!("loading nvram");
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// Round up to 4 bytes.
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let nvram_len = (NVRAM.len() + 3) / 4 * 4;
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self.bus
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.bp_write(ram_addr + CHIP.chip_ram_size - 4 - nvram_len as u32, NVRAM)
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.await;
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let nvram_len_words = nvram_len as u32 / 4;
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let nvram_len_magic = (!nvram_len_words << 16) | nvram_len_words;
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self.bus
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.bp_write32(ram_addr + CHIP.chip_ram_size - 4, nvram_len_magic)
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.await;
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// Start core!
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info!("starting up core...");
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self.core_reset(Core::WLAN).await;
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assert!(self.core_is_up(Core::WLAN).await);
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while self.bus.read8(FUNC_BACKPLANE, REG_BACKPLANE_CHIP_CLOCK_CSR).await & 0x80 == 0 {}
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// "Set up the interrupt mask and enable interrupts"
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// self.bus.bp_write32(CHIP.sdiod_core_base_address + 0x24, 0xF0).await;
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self.bus
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.write16(FUNC_BUS, REG_BUS_INTERRUPT_ENABLE, IRQ_F2_PACKET_AVAILABLE)
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.await;
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// "Lower F2 Watermark to avoid DMA Hang in F2 when SD Clock is stopped."
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// Sounds scary...
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self.bus
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.write8(FUNC_BACKPLANE, REG_BACKPLANE_FUNCTION2_WATERMARK, 32)
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.await;
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// wait for wifi startup
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info!("waiting for wifi init...");
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while self.bus.read32(FUNC_BUS, REG_BUS_STATUS).await & STATUS_F2_RX_READY == 0 {}
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// Some random configs related to sleep.
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// These aren't needed if we don't want to sleep the bus.
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// TODO do we need to sleep the bus to read the irq line, due to
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// being on the same pin as MOSI/MISO?
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/*
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let mut val = self.bus.read8(FUNC_BACKPLANE, REG_BACKPLANE_WAKEUP_CTRL).await;
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val |= 0x02; // WAKE_TILL_HT_AVAIL
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self.bus.write8(FUNC_BACKPLANE, REG_BACKPLANE_WAKEUP_CTRL, val).await;
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self.bus.write8(FUNC_BUS, 0xF0, 0x08).await; // SDIOD_CCCR_BRCM_CARDCAP.CMD_NODEC = 1
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self.bus.write8(FUNC_BACKPLANE, REG_BACKPLANE_CHIP_CLOCK_CSR, 0x02).await; // SBSDIO_FORCE_HT
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let mut val = self.bus.read8(FUNC_BACKPLANE, REG_BACKPLANE_SLEEP_CSR).await;
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val |= 0x01; // SBSDIO_SLPCSR_KEEP_SDIO_ON
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self.bus.write8(FUNC_BACKPLANE, REG_BACKPLANE_SLEEP_CSR, val).await;
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*/
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// clear pulls
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self.bus.write8(FUNC_BACKPLANE, REG_BACKPLANE_PULL_UP, 0).await;
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let _ = self.bus.read8(FUNC_BACKPLANE, REG_BACKPLANE_PULL_UP).await;
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// start HT clock
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//self.bus.write8(FUNC_BACKPLANE, REG_BACKPLANE_CHIP_CLOCK_CSR, 0x10).await;
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//info!("waiting for HT clock...");
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//while self.bus.read8(FUNC_BACKPLANE, REG_BACKPLANE_CHIP_CLOCK_CSR).await & 0x80 == 0 {}
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//info!("clock ok");
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#[cfg(feature = "firmware-logs")]
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self.log_init().await;
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info!("init done ");
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}
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#[cfg(feature = "firmware-logs")]
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async fn log_init(&mut self) {
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// Initialize shared memory for logging.
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let addr = CHIP.atcm_ram_base_address + CHIP.chip_ram_size - 4 - CHIP.socram_srmem_size;
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let shared_addr = self.bus.bp_read32(addr).await;
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info!("shared_addr {:08x}", shared_addr);
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let mut shared = [0; SharedMemData::SIZE];
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self.bus.bp_read(shared_addr, &mut shared).await;
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let shared = SharedMemData::from_bytes(&shared);
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self.log.addr = shared.console_addr + 8;
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}
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#[cfg(feature = "firmware-logs")]
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async fn log_read(&mut self) {
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// Read log struct
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let mut log = [0; SharedMemLog::SIZE];
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self.bus.bp_read(self.log.addr, &mut log).await;
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let log = SharedMemLog::from_bytes(&log);
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let idx = log.idx as usize;
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// If pointer hasn't moved, no need to do anything.
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if idx == self.log.last_idx {
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return;
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}
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// Read entire buf for now. We could read only what we need, but then we
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// run into annoying alignment issues in `bp_read`.
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let mut buf = [0; 0x400];
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self.bus.bp_read(log.buf, &mut buf).await;
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while self.log.last_idx != idx as usize {
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let b = buf[self.log.last_idx];
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if b == b'\r' || b == b'\n' {
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if self.log.buf_count != 0 {
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let s = unsafe { core::str::from_utf8_unchecked(&self.log.buf[..self.log.buf_count]) };
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debug!("LOGS: {}", s);
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self.log.buf_count = 0;
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}
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} else if self.log.buf_count < self.log.buf.len() {
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self.log.buf[self.log.buf_count] = b;
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self.log.buf_count += 1;
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}
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self.log.last_idx += 1;
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if self.log.last_idx == 0x400 {
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self.log.last_idx = 0;
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}
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}
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}
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pub async fn run(mut self) -> ! {
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let mut buf = [0; 512];
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loop {
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#[cfg(feature = "firmware-logs")]
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self.log_read().await;
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if self.has_credit() {
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let ioctl = self.ioctl_state.wait_pending();
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let tx = self.ch.tx_buf();
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let ev = self.bus.wait_for_event();
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match select3(ioctl, tx, ev).await {
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Either3::First(PendingIoctl {
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buf: iobuf,
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kind,
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cmd,
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iface,
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}) => {
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self.send_ioctl(kind, cmd, iface, unsafe { &*iobuf }).await;
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self.check_status(&mut buf).await;
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}
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Either3::Second(packet) => {
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trace!("tx pkt {:02x}", Bytes(&packet[..packet.len().min(48)]));
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let mut buf = [0; 512];
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let buf8 = slice8_mut(&mut buf);
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let total_len = SdpcmHeader::SIZE + BcdHeader::SIZE + packet.len();
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let seq = self.sdpcm_seq;
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self.sdpcm_seq = self.sdpcm_seq.wrapping_add(1);
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let sdpcm_header = SdpcmHeader {
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len: total_len as u16, // TODO does this len need to be rounded up to u32?
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len_inv: !total_len as u16,
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sequence: seq,
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channel_and_flags: CHANNEL_TYPE_DATA,
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next_length: 0,
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header_length: SdpcmHeader::SIZE as _,
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wireless_flow_control: 0,
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bus_data_credit: 0,
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reserved: [0, 0],
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};
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let bcd_header = BcdHeader {
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flags: BDC_VERSION << BDC_VERSION_SHIFT,
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priority: 0,
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flags2: 0,
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data_offset: 0,
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};
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trace!("tx {:?}", sdpcm_header);
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trace!(" {:?}", bcd_header);
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buf8[0..SdpcmHeader::SIZE].copy_from_slice(&sdpcm_header.to_bytes());
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buf8[SdpcmHeader::SIZE..][..BcdHeader::SIZE].copy_from_slice(&bcd_header.to_bytes());
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buf8[SdpcmHeader::SIZE + BcdHeader::SIZE..][..packet.len()].copy_from_slice(packet);
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let total_len = (total_len + 3) & !3; // round up to 4byte
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trace!(" {:02x}", Bytes(&buf8[..total_len.min(48)]));
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self.bus.wlan_write(&buf[..(total_len / 4)]).await;
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self.ch.tx_done();
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self.check_status(&mut buf).await;
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}
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Either3::Third(()) => {
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self.handle_irq(&mut buf).await;
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}
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}
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} else {
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warn!("TX stalled");
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self.bus.wait_for_event().await;
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self.handle_irq(&mut buf).await;
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}
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}
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}
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/// Wait for IRQ on F2 packet available
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async fn handle_irq(&mut self, buf: &mut [u32; 512]) {
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// Receive stuff
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let irq = self.bus.read16(FUNC_BUS, REG_BUS_INTERRUPT).await;
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trace!("irq{}", FormatInterrupt(irq));
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if irq & IRQ_F2_PACKET_AVAILABLE != 0 {
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self.check_status(buf).await;
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}
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}
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/// Handle F2 events while status register is set
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async fn check_status(&mut self, buf: &mut [u32; 512]) {
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loop {
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let mut status = 0xFFFF_FFFF;
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while status == 0xFFFF_FFFF {
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status = self.bus.read32(FUNC_BUS, REG_BUS_STATUS).await;
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}
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trace!("check status{}", FormatStatus(status));
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if status & STATUS_F2_PKT_AVAILABLE != 0 {
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let len = (status & STATUS_F2_PKT_LEN_MASK) >> STATUS_F2_PKT_LEN_SHIFT;
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self.bus.wlan_read(buf, len).await;
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trace!("rx {:02x}", Bytes(&slice8_mut(buf)[..(len as usize).min(48)]));
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self.rx(&slice8_mut(buf)[..len as usize]);
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} else {
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break;
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}
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}
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}
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fn rx(&mut self, packet: &[u8]) {
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if packet.len() < SdpcmHeader::SIZE {
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warn!("packet too short, len={}", packet.len());
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return;
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}
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let sdpcm_header = SdpcmHeader::from_bytes(packet[..SdpcmHeader::SIZE].try_into().unwrap());
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trace!("rx {:?}", sdpcm_header);
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if sdpcm_header.len != !sdpcm_header.len_inv {
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warn!("len inv mismatch");
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return;
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}
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if sdpcm_header.len as usize != packet.len() {
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// TODO: is this guaranteed??
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warn!("len from header doesn't match len from spi");
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return;
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}
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self.update_credit(&sdpcm_header);
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let channel = sdpcm_header.channel_and_flags & 0x0f;
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let payload = &packet[sdpcm_header.header_length as _..];
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match channel {
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CHANNEL_TYPE_CONTROL => {
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if payload.len() < CdcHeader::SIZE {
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warn!("payload too short, len={}", payload.len());
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return;
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}
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let cdc_header = CdcHeader::from_bytes(payload[..CdcHeader::SIZE].try_into().unwrap());
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trace!(" {:?}", cdc_header);
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if cdc_header.id == self.ioctl_id {
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if cdc_header.status != 0 {
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// TODO: propagate error instead
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panic!("IOCTL error {}", cdc_header.status as i32);
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}
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let resp_len = cdc_header.len as usize;
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let response = &payload[CdcHeader::SIZE..][..resp_len];
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info!("IOCTL Response: {:02x}", Bytes(response));
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self.ioctl_state.ioctl_done(response);
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}
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}
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CHANNEL_TYPE_EVENT => {
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let bcd_header = BcdHeader::from_bytes(&payload[..BcdHeader::SIZE].try_into().unwrap());
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trace!(" {:?}", bcd_header);
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let packet_start = BcdHeader::SIZE + 4 * bcd_header.data_offset as usize;
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if packet_start + EventPacket::SIZE > payload.len() {
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warn!("BCD event, incomplete header");
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return;
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}
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let bcd_packet = &payload[packet_start..];
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trace!(" {:02x}", Bytes(&bcd_packet[..(bcd_packet.len() as usize).min(36)]));
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let mut event_packet = EventPacket::from_bytes(&bcd_packet[..EventPacket::SIZE].try_into().unwrap());
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event_packet.byteswap();
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const ETH_P_LINK_CTL: u16 = 0x886c; // HPNA, wlan link local tunnel, according to linux if_ether.h
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if event_packet.eth.ether_type != ETH_P_LINK_CTL {
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warn!(
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"unexpected ethernet type 0x{:04x}, expected Broadcom ether type 0x{:04x}",
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event_packet.eth.ether_type, ETH_P_LINK_CTL
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);
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return;
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}
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const BROADCOM_OUI: &[u8] = &[0x00, 0x10, 0x18];
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if event_packet.hdr.oui != BROADCOM_OUI {
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warn!(
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"unexpected ethernet OUI {:02x}, expected Broadcom OUI {:02x}",
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Bytes(&event_packet.hdr.oui),
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Bytes(BROADCOM_OUI)
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);
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return;
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}
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const BCMILCP_SUBTYPE_VENDOR_LONG: u16 = 32769;
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if event_packet.hdr.subtype != BCMILCP_SUBTYPE_VENDOR_LONG {
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warn!("unexpected subtype {}", event_packet.hdr.subtype);
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return;
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}
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const BCMILCP_BCM_SUBTYPE_EVENT: u16 = 1;
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if event_packet.hdr.user_subtype != BCMILCP_BCM_SUBTYPE_EVENT {
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warn!("unexpected user_subtype {}", event_packet.hdr.subtype);
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return;
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}
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if event_packet.msg.datalen as usize >= (bcd_packet.len() - EventMessage::SIZE) {
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warn!("BCD event, incomplete data");
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return;
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}
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let evt_type = events::Event::from(event_packet.msg.event_type as u8);
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let evt_data = &bcd_packet[EventMessage::SIZE..][..event_packet.msg.datalen as usize];
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debug!(
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"=== EVENT {:?}: {:?} {:02x}",
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evt_type,
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event_packet.msg,
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Bytes(evt_data)
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);
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if evt_type == events::Event::AUTH || evt_type == events::Event::JOIN {
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self.events.publish_immediate(EventStatus {
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status: event_packet.msg.status,
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event_type: evt_type,
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});
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}
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}
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CHANNEL_TYPE_DATA => {
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let bcd_header = BcdHeader::from_bytes(&payload[..BcdHeader::SIZE].try_into().unwrap());
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trace!(" {:?}", bcd_header);
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let packet_start = BcdHeader::SIZE + 4 * bcd_header.data_offset as usize;
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if packet_start > payload.len() {
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warn!("packet start out of range.");
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return;
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}
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let packet = &payload[packet_start..];
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trace!("rx pkt {:02x}", Bytes(&packet[..(packet.len() as usize).min(48)]));
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match self.ch.try_rx_buf() {
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Some(buf) => {
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buf[..packet.len()].copy_from_slice(packet);
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self.ch.rx_done(packet.len())
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}
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None => warn!("failed to push rxd packet to the channel."),
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}
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}
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_ => {}
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}
|
|
}
|
|
|
|
fn update_credit(&mut self, sdpcm_header: &SdpcmHeader) {
|
|
if sdpcm_header.channel_and_flags & 0xf < 3 {
|
|
let mut sdpcm_seq_max = sdpcm_header.bus_data_credit;
|
|
if sdpcm_seq_max.wrapping_sub(self.sdpcm_seq) > 0x40 {
|
|
sdpcm_seq_max = self.sdpcm_seq + 2;
|
|
}
|
|
self.sdpcm_seq_max = sdpcm_seq_max;
|
|
}
|
|
}
|
|
|
|
fn has_credit(&self) -> bool {
|
|
self.sdpcm_seq != self.sdpcm_seq_max && self.sdpcm_seq_max.wrapping_sub(self.sdpcm_seq) & 0x80 == 0
|
|
}
|
|
|
|
async fn send_ioctl(&mut self, kind: IoctlType, cmd: u32, iface: u32, data: &[u8]) {
|
|
let mut buf = [0; 512];
|
|
let buf8 = slice8_mut(&mut buf);
|
|
|
|
let total_len = SdpcmHeader::SIZE + CdcHeader::SIZE + data.len();
|
|
|
|
let sdpcm_seq = self.sdpcm_seq;
|
|
self.sdpcm_seq = self.sdpcm_seq.wrapping_add(1);
|
|
self.ioctl_id = self.ioctl_id.wrapping_add(1);
|
|
|
|
let sdpcm_header = SdpcmHeader {
|
|
len: total_len as u16, // TODO does this len need to be rounded up to u32?
|
|
len_inv: !total_len as u16,
|
|
sequence: sdpcm_seq,
|
|
channel_and_flags: CHANNEL_TYPE_CONTROL,
|
|
next_length: 0,
|
|
header_length: SdpcmHeader::SIZE as _,
|
|
wireless_flow_control: 0,
|
|
bus_data_credit: 0,
|
|
reserved: [0, 0],
|
|
};
|
|
|
|
let cdc_header = CdcHeader {
|
|
cmd: cmd,
|
|
len: data.len() as _,
|
|
flags: kind as u16 | (iface as u16) << 12,
|
|
id: self.ioctl_id,
|
|
status: 0,
|
|
};
|
|
trace!("tx {:?}", sdpcm_header);
|
|
trace!(" {:?}", cdc_header);
|
|
|
|
buf8[0..SdpcmHeader::SIZE].copy_from_slice(&sdpcm_header.to_bytes());
|
|
buf8[SdpcmHeader::SIZE..][..CdcHeader::SIZE].copy_from_slice(&cdc_header.to_bytes());
|
|
buf8[SdpcmHeader::SIZE + CdcHeader::SIZE..][..data.len()].copy_from_slice(data);
|
|
|
|
let total_len = (total_len + 3) & !3; // round up to 4byte
|
|
|
|
trace!(" {:02x}", Bytes(&buf8[..total_len.min(48)]));
|
|
|
|
self.bus.wlan_write(&buf[..total_len / 4]).await;
|
|
}
|
|
|
|
async fn core_disable(&mut self, core: Core) {
|
|
let base = core.base_addr();
|
|
|
|
// Dummy read?
|
|
let _ = self.bus.bp_read8(base + AI_RESETCTRL_OFFSET).await;
|
|
|
|
// Check it isn't already reset
|
|
let r = self.bus.bp_read8(base + AI_RESETCTRL_OFFSET).await;
|
|
if r & AI_RESETCTRL_BIT_RESET != 0 {
|
|
return;
|
|
}
|
|
|
|
self.bus.bp_write8(base + AI_IOCTRL_OFFSET, 0).await;
|
|
let _ = self.bus.bp_read8(base + AI_IOCTRL_OFFSET).await;
|
|
|
|
block_for(Duration::from_millis(1));
|
|
|
|
self.bus
|
|
.bp_write8(base + AI_RESETCTRL_OFFSET, AI_RESETCTRL_BIT_RESET)
|
|
.await;
|
|
let _ = self.bus.bp_read8(base + AI_RESETCTRL_OFFSET).await;
|
|
}
|
|
|
|
async fn core_reset(&mut self, core: Core) {
|
|
self.core_disable(core).await;
|
|
|
|
let base = core.base_addr();
|
|
self.bus
|
|
.bp_write8(base + AI_IOCTRL_OFFSET, AI_IOCTRL_BIT_FGC | AI_IOCTRL_BIT_CLOCK_EN)
|
|
.await;
|
|
let _ = self.bus.bp_read8(base + AI_IOCTRL_OFFSET).await;
|
|
|
|
self.bus.bp_write8(base + AI_RESETCTRL_OFFSET, 0).await;
|
|
|
|
Timer::after(Duration::from_millis(1)).await;
|
|
|
|
self.bus
|
|
.bp_write8(base + AI_IOCTRL_OFFSET, AI_IOCTRL_BIT_CLOCK_EN)
|
|
.await;
|
|
let _ = self.bus.bp_read8(base + AI_IOCTRL_OFFSET).await;
|
|
|
|
Timer::after(Duration::from_millis(1)).await;
|
|
}
|
|
|
|
async fn core_is_up(&mut self, core: Core) -> bool {
|
|
let base = core.base_addr();
|
|
|
|
let io = self.bus.bp_read8(base + AI_IOCTRL_OFFSET).await;
|
|
if io & (AI_IOCTRL_BIT_FGC | AI_IOCTRL_BIT_CLOCK_EN) != AI_IOCTRL_BIT_CLOCK_EN {
|
|
debug!("core_is_up: returning false due to bad ioctrl {:02x}", io);
|
|
return false;
|
|
}
|
|
|
|
let r = self.bus.bp_read8(base + AI_RESETCTRL_OFFSET).await;
|
|
if r & (AI_RESETCTRL_BIT_RESET) != 0 {
|
|
debug!("core_is_up: returning false due to bad resetctrl {:02x}", r);
|
|
return false;
|
|
}
|
|
|
|
true
|
|
}
|
|
}
|
|
|
|
fn slice8_mut(x: &mut [u32]) -> &mut [u8] {
|
|
let len = x.len() * 4;
|
|
unsafe { slice::from_raw_parts_mut(x.as_mut_ptr() as _, len) }
|
|
}
|