283 lines
6.6 KiB
Rust
283 lines
6.6 KiB
Rust
/// Trigger selection for STM32F0.
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#[cfg(stm32f0)]
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#[derive(Debug, Copy, Clone, Eq, PartialEq)]
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#[cfg_attr(feature = "defmt", derive(defmt::Format))]
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pub enum TriggerSel {
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Tim6 = 0,
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Tim3 = 1,
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Tim7 = 2,
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Tim15 = 3,
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Tim2 = 4,
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Exti9 = 6,
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Software = 7,
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}
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/// Trigger selection for STM32F1.
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#[cfg(stm32f1)]
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#[derive(Debug, Copy, Clone, Eq, PartialEq)]
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#[cfg_attr(feature = "defmt", derive(defmt::Format))]
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pub enum TriggerSel {
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Tim6 = 0,
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#[cfg(any(stm32f100, stm32f105, stm32f107))]
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Tim3 = 1,
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#[cfg(any(stm32f101, stm32f103))]
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Tim8 = 1,
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Tim7 = 2,
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#[cfg(any(stm32f101, stm32f103, stm32f105, stm32f107))]
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Tim5 = 3,
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#[cfg(all(stm32f100, any(flashsize_4, flashsize_6, flashsize_8, flashsize_b)))]
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Tim15 = 3,
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#[cfg(all(stm32f100, any(flashsize_c, flashsize_d, flashsize_e)))]
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/// Can be remapped to TIM15 with MISC_REMAP in AFIO_MAPR2.
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Tim5Or15 = 3,
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Tim2 = 4,
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Tim4 = 5,
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Exti9 = 6,
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Software = 7,
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}
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/// Trigger selection for STM32F2/F4/F7/L4, except F410 or L4+.
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#[cfg(all(any(stm32f2, stm32f4, stm32f7, stm32l4_nonplus), not(stm32f410)))]
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#[derive(Debug, Copy, Clone, Eq, PartialEq)]
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#[cfg_attr(feature = "defmt", derive(defmt::Format))]
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pub enum TriggerSel {
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Tim6 = 0,
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Tim8 = 1,
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#[cfg(not(any(stm32l45x, stm32l46x)))]
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Tim7 = 2,
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Tim5 = 3,
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Tim2 = 4,
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Tim4 = 5,
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Exti9 = 6,
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Software = 7,
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}
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/// Trigger selection for STM32F410.
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#[cfg(stm32f410)]
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#[derive(Debug, Copy, Clone, Eq, PartialEq)]
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#[cfg_attr(feature = "defmt", derive(defmt::Format))]
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pub enum TriggerSel {
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Tim5 = 3,
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Exti9 = 6,
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Software = 7,
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}
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/// Trigger selection for STM32F301/2 and 318.
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#[cfg(any(stm32f301, stm32f302, stm32f318))]
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#[derive(Debug, Copy, Clone, Eq, PartialEq)]
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#[cfg_attr(feature = "defmt", derive(defmt::Format))]
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pub enum TriggerSel {
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Tim6 = 0,
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#[cfg(stm32f302)]
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/// Requires DAC_TRIG_RMP set in SYSCFG_CFGR1.
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Tim3 = 1,
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Tim15 = 3,
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Tim2 = 4,
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#[cfg(all(stm32f302, any(flashsize_6, flashsize_8)))]
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Tim4 = 5,
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Exti9 = 6,
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Software = 7,
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}
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/// Trigger selection for STM32F303/3x8 (excluding 318 which is like 301, and 378 which is 37x).
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#[cfg(any(stm32f303, stm32f328, stm32f358, stm32f398))]
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#[derive(Debug, Copy, Clone, Eq, PartialEq)]
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#[cfg_attr(feature = "defmt", derive(defmt::Format))]
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pub enum TriggerSel {
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Tim6 = 0,
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/// * DAC1: defaults to TIM8 but can be remapped to TIM3 with DAC_TRIG_RMP in SYSCFG_CFGR1
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/// * DAC2: always TIM3
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Tim8Or3 = 1,
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Tim7 = 2,
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Tim15 = 3,
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Tim2 = 4,
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Tim4 = 5,
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Exti9 = 6,
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Software = 7,
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}
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/// Trigger selection for STM32F37x.
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#[cfg(any(stm32f373, stm32f378))]
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#[derive(Debug, Copy, Clone, Eq, PartialEq)]
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#[cfg_attr(feature = "defmt", derive(defmt::Format))]
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pub enum TriggerSel {
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Tim6 = 0,
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Tim3 = 1,
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Tim7 = 2,
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/// TIM5 on DAC1, TIM18 on DAC2
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Dac1Tim5Dac2Tim18 = 3,
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Tim2 = 4,
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Tim4 = 5,
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Exti9 = 6,
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Software = 7,
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}
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/// Trigger selection for STM32F334.
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#[cfg(stm32f334)]
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#[derive(Debug, Copy, Clone, Eq, PartialEq)]
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#[cfg_attr(feature = "defmt", derive(defmt::Format))]
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pub enum TriggerSel {
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Tim6 = 0,
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/// Requires DAC_TRIG_RMP set in SYSCFG_CFGR1.
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Tim3 = 1,
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Tim7 = 2,
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/// Can be remapped to HRTIM_DACTRG1 using DAC1_TRIG3_RMP in SYSCFG_CFGR3.
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Tim15OrHrtimDacTrg1 = 3,
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Tim2 = 4,
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/// Requires DAC_TRIG5_RMP set in SYSCFG_CFGR3.
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HrtimDacTrg2 = 5,
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}
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/// Trigger selection for STM32L0.
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#[cfg(stm32l0)]
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#[derive(Debug, Copy, Clone, Eq, PartialEq)]
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#[cfg_attr(feature = "defmt", derive(defmt::Format))]
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pub enum TriggerSel {
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Tim6 = 0,
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Tim3 = 1,
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Tim3Ch3 = 2,
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Tim21 = 3,
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Tim2 = 4,
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Tim7 = 5,
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Exti9 = 6,
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Software = 7,
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}
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/// Trigger selection for STM32L1.
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#[cfg(stm32l1)]
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#[derive(Debug, Copy, Clone, Eq, PartialEq)]
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#[cfg_attr(feature = "defmt", derive(defmt::Format))]
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pub enum TriggerSel {
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Tim6 = 0,
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Tim7 = 2,
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Tim9 = 3,
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Tim2 = 4,
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Tim4 = 5,
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Exti9 = 6,
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Software = 7,
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}
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/// Trigger selection for L4+, L5, U5, H7.
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#[cfg(any(stm32l4_plus, stm32l5, stm32u5, stm32h7))]
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#[derive(Debug, Copy, Clone, Eq, PartialEq)]
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#[cfg_attr(feature = "defmt", derive(defmt::Format))]
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pub enum TriggerSel {
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Software = 0,
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Tim1 = 1,
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Tim2 = 2,
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Tim4 = 3,
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Tim5 = 4,
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Tim6 = 5,
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Tim7 = 6,
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Tim8 = 7,
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Tim15 = 8,
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#[cfg(all(stm32h7, hrtim))]
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Hrtim1DacTrg1 = 9,
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#[cfg(all(stm32h7, hrtim))]
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Hrtim1DacTrg2 = 10,
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Lptim1 = 11,
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#[cfg(not(stm32u5))]
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Lptim2 = 12,
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#[cfg(stm32u5)]
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Lptim3 = 12,
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Exti9 = 13,
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#[cfg(any(stm32h7ax, stm32h7bx))]
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/// RM0455 suggests this might be LPTIM2 on DAC1 and LPTIM3 on DAC2,
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/// but it's probably wrong. Please let us know if you find out.
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Lptim3 = 14,
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#[cfg(any(stm32h72x, stm32h73x))]
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Tim23 = 14,
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#[cfg(any(stm32h72x, stm32h73x))]
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Tim24 = 15,
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}
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/// Trigger selection for H5.
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#[cfg(stm32h5)]
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#[derive(Debug, Copy, Clone, Eq, PartialEq)]
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#[cfg_attr(feature = "defmt", derive(defmt::Format))]
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pub enum TriggerSel {
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Software = 0,
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Tim1 = 1,
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Tim2 = 2,
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#[cfg(any(stm32h56x, stm32h57x))]
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Tim4 = 3,
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#[cfg(stm32h503)]
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Tim3 = 3,
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#[cfg(any(stm32h56x, stm32h57x))]
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Tim5 = 4,
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Tim6 = 5,
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Tim7 = 6,
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#[cfg(any(stm32h56x, stm32h57x))]
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Tim8 = 7,
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#[cfg(any(stm32h56x, stm32h57x))]
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Tim15 = 8,
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Lptim1 = 11,
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Lptim2 = 12,
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Exti9 = 13,
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}
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/// Trigger selection for G0.
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#[cfg(stm32g0)]
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#[derive(Debug, Copy, Clone, Eq, PartialEq)]
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#[cfg_attr(feature = "defmt", derive(defmt::Format))]
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pub enum TriggerSel {
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Software = 0,
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Tim1 = 1,
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Tim2 = 2,
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Tim3 = 3,
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Tim6 = 5,
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Tim7 = 6,
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Tim15 = 8,
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Lptim1 = 11,
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Lptim2 = 12,
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Exti9 = 13,
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}
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/// Trigger selection for G4.
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#[cfg(stm32g4)]
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#[derive(Debug, Copy, Clone, Eq, PartialEq)]
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#[cfg_attr(feature = "defmt", derive(defmt::Format))]
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pub enum TriggerSel {
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Software = 0,
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/// * DAC1, DAC2, DAC4: TIM8
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/// * DAC3: TIM1
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Dac124Tim8Dac3Tim1 = 1,
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Tim7 = 2,
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Tim15 = 3,
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Tim2 = 4,
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Tim4 = 5,
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Exti9 = 6,
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Tim6 = 7,
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Tim3 = 8,
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HrtimDacRstTrg1 = 9,
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HrtimDacRstTrg2 = 10,
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HrtimDacRstTrg3 = 11,
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HrtimDacRstTrg4 = 12,
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HrtimDacRstTrg5 = 13,
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HrtimDacRstTrg6 = 14,
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/// * DAC1, DAC4: HRTIM_DAC_TRG1
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/// * DAC2: HRTIM_DAC_TRG2
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/// * DAC3: HRTIM_DAC_TRG3
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HrtimDacTrg123 = 15,
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}
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/// Trigger selection for WL.
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#[cfg(stm32wl)]
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#[derive(Debug, Copy, Clone, Eq, PartialEq)]
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#[cfg_attr(feature = "defmt", derive(defmt::Format))]
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pub enum TriggerSel {
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Software = 0,
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Tim1 = 1,
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Tim2 = 2,
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Lptim1 = 11,
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Lptim2 = 12,
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Lptim3 = 13,
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Exti9 = 14,
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}
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impl TriggerSel {
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pub fn tsel(&self) -> u8 {
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*self as u8
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}
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}
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