334 lines
8.2 KiB
Rust
334 lines
8.2 KiB
Rust
use crate::pac::{FLASH, RCC};
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use crate::rcc::{set_freqs, Clocks};
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use crate::time::{Hertz, U32Ext};
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/// Most of clock setup is copied from stm32l0xx-hal, and adopted to the generated PAC,
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/// and with the addition of the init function to configure a system clock.
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/// Only the basic setup using the HSE and HSI clocks are supported as of now.
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/// HSI speed
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pub const HSI_FREQ: Hertz = Hertz(16_000_000);
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/// LSI speed
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pub const LSI_FREQ: Hertz = Hertz(32_000);
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/// HSE32 speed
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pub const HSE32_FREQ: Hertz = Hertz(32_000_000);
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/// System clock mux source
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#[derive(Clone, Copy)]
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pub enum ClockSrc {
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MSI(MSIRange),
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HSE32,
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HSI16,
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}
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#[derive(Clone, Copy, PartialOrd, PartialEq)]
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pub enum MSIRange {
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/// Around 100 kHz
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Range0,
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/// Around 200 kHz
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Range1,
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/// Around 400 kHz
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Range2,
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/// Around 800 kHz
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Range3,
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/// Around 1 MHz
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Range4,
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/// Around 2 MHz
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Range5,
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/// Around 4 MHz (reset value)
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Range6,
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/// Around 8 MHz
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Range7,
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/// Around 16 MHz
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Range8,
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/// Around 24 MHz
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Range9,
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/// Around 32 MHz
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Range10,
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/// Around 48 MHz
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Range11,
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}
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impl MSIRange {
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fn freq(&self) -> u32 {
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match self {
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MSIRange::Range0 => 100_000,
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MSIRange::Range1 => 200_000,
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MSIRange::Range2 => 400_000,
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MSIRange::Range3 => 800_000,
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MSIRange::Range4 => 1_000_000,
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MSIRange::Range5 => 2_000_000,
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MSIRange::Range6 => 4_000_000,
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MSIRange::Range7 => 8_000_000,
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MSIRange::Range8 => 16_000_000,
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MSIRange::Range9 => 24_000_000,
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MSIRange::Range10 => 32_000_000,
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MSIRange::Range11 => 48_000_000,
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}
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}
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fn vos(&self) -> VoltageScale {
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if self > &MSIRange::Range8 {
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VoltageScale::Range1
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} else {
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VoltageScale::Range2
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}
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}
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}
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impl Default for MSIRange {
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fn default() -> MSIRange {
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MSIRange::Range6
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}
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}
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impl Into<u8> for MSIRange {
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fn into(self) -> u8 {
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match self {
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MSIRange::Range0 => 0b0000,
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MSIRange::Range1 => 0b0001,
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MSIRange::Range2 => 0b0010,
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MSIRange::Range3 => 0b0011,
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MSIRange::Range4 => 0b0100,
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MSIRange::Range5 => 0b0101,
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MSIRange::Range6 => 0b0110,
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MSIRange::Range7 => 0b0111,
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MSIRange::Range8 => 0b1000,
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MSIRange::Range9 => 0b1001,
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MSIRange::Range10 => 0b1010,
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MSIRange::Range11 => 0b1011,
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}
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}
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}
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/// Voltage Scale
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///
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/// Represents the voltage range feeding the CPU core. The maximum core
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/// clock frequency depends on this value.
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#[derive(Copy, Clone, PartialEq)]
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pub enum VoltageScale {
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Range1,
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Range2,
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}
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/// AHB prescaler
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#[derive(Clone, Copy, PartialEq)]
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pub enum AHBPrescaler {
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NotDivided,
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Div2,
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Div3,
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Div4,
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Div5,
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Div6,
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Div8,
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Div10,
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Div16,
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Div32,
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Div64,
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Div128,
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Div256,
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Div512,
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}
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/// APB prescaler
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#[derive(Clone, Copy)]
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pub enum APBPrescaler {
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NotDivided,
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Div2,
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Div4,
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Div8,
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Div16,
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}
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impl Into<u8> for APBPrescaler {
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fn into(self) -> u8 {
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match self {
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APBPrescaler::NotDivided => 1,
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APBPrescaler::Div2 => 0x04,
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APBPrescaler::Div4 => 0x05,
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APBPrescaler::Div8 => 0x06,
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APBPrescaler::Div16 => 0x07,
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}
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}
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}
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impl Into<u8> for AHBPrescaler {
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fn into(self) -> u8 {
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match self {
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AHBPrescaler::NotDivided => 1,
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AHBPrescaler::Div2 => 0x08,
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AHBPrescaler::Div3 => 0x01,
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AHBPrescaler::Div4 => 0x09,
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AHBPrescaler::Div5 => 0x02,
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AHBPrescaler::Div6 => 0x05,
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AHBPrescaler::Div8 => 0x0a,
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AHBPrescaler::Div10 => 0x06,
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AHBPrescaler::Div16 => 0x0b,
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AHBPrescaler::Div32 => 0x07,
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AHBPrescaler::Div64 => 0x0c,
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AHBPrescaler::Div128 => 0x0d,
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AHBPrescaler::Div256 => 0x0e,
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AHBPrescaler::Div512 => 0x0f,
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}
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}
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}
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/// Clocks configutation
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pub struct Config {
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pub mux: ClockSrc,
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pub ahb_pre: AHBPrescaler,
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pub shd_ahb_pre: AHBPrescaler,
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pub apb1_pre: APBPrescaler,
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pub apb2_pre: APBPrescaler,
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pub enable_lsi: bool,
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}
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impl Default for Config {
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#[inline]
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fn default() -> Config {
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Config {
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mux: ClockSrc::MSI(MSIRange::default()),
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ahb_pre: AHBPrescaler::NotDivided,
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shd_ahb_pre: AHBPrescaler::NotDivided,
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apb1_pre: APBPrescaler::NotDivided,
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apb2_pre: APBPrescaler::NotDivided,
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enable_lsi: false,
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}
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}
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}
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pub(crate) unsafe fn init(config: Config) {
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let (sys_clk, sw, vos) = match config.mux {
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ClockSrc::HSI16 => {
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// Enable HSI16
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RCC.cr().write(|w| w.set_hsion(true));
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while !RCC.cr().read().hsirdy() {}
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(HSI_FREQ.0, 0x01, VoltageScale::Range2)
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}
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ClockSrc::HSE32 => {
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// Enable HSE32
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RCC.cr().write(|w| {
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w.set_hsebyppwr(true);
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w.set_hseon(true);
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});
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while !RCC.cr().read().hserdy() {}
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(HSE32_FREQ.0, 0x02, VoltageScale::Range1)
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}
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ClockSrc::MSI(range) => {
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RCC.cr().write(|w| {
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w.set_msirange(range.into());
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w.set_msion(true);
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});
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while !RCC.cr().read().msirdy() {}
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(range.freq(), 0x00, range.vos())
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}
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};
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RCC.cfgr().modify(|w| {
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w.set_sw(sw.into());
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if config.ahb_pre == AHBPrescaler::NotDivided {
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w.set_hpre(0);
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} else {
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w.set_hpre(config.ahb_pre.into());
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}
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w.set_ppre1(config.apb1_pre.into());
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w.set_ppre2(config.apb2_pre.into());
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});
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RCC.extcfgr().modify(|w| {
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if config.shd_ahb_pre == AHBPrescaler::NotDivided {
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w.set_shdhpre(0);
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} else {
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w.set_shdhpre(config.shd_ahb_pre.into());
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}
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});
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let ahb_freq: u32 = match config.ahb_pre {
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AHBPrescaler::NotDivided => sys_clk,
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pre => {
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let pre: u8 = pre.into();
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let pre = 1 << (pre as u32 - 7);
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sys_clk / pre
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}
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};
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let shd_ahb_freq: u32 = match config.shd_ahb_pre {
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AHBPrescaler::NotDivided => sys_clk,
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pre => {
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let pre: u8 = pre.into();
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let pre = 1 << (pre as u32 - 7);
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sys_clk / pre
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}
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};
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let (apb1_freq, apb1_tim_freq) = match config.apb1_pre {
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APBPrescaler::NotDivided => (ahb_freq, ahb_freq),
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pre => {
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let pre: u8 = pre.into();
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let pre: u8 = 1 << (pre - 3);
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let freq = ahb_freq / pre as u32;
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(freq, freq * 2)
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}
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};
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let (apb2_freq, apb2_tim_freq) = match config.apb2_pre {
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APBPrescaler::NotDivided => (ahb_freq, ahb_freq),
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pre => {
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let pre: u8 = pre.into();
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let pre: u8 = 1 << (pre - 3);
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let freq = ahb_freq / (1 << (pre as u8 - 3));
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(freq, freq * 2)
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}
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};
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let apb3_freq = shd_ahb_freq;
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if config.enable_lsi {
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let csr = RCC.csr().read();
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if !csr.lsion() {
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RCC.csr().modify(|w| w.set_lsion(true));
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while !RCC.csr().read().lsirdy() {}
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}
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}
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// Adjust flash latency
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let flash_clk_src_freq: u32 = shd_ahb_freq;
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let ws = match vos {
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VoltageScale::Range1 => match flash_clk_src_freq {
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0..=18_000_000 => 0b000,
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18_000_001..=36_000_000 => 0b001,
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_ => 0b010,
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},
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VoltageScale::Range2 => match flash_clk_src_freq {
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0..=6_000_000 => 0b000,
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6_000_001..=12_000_000 => 0b001,
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_ => 0b010,
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},
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};
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FLASH.acr().modify(|w| {
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w.set_latency(ws);
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});
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while FLASH.acr().read().latency() != ws {}
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set_freqs(Clocks {
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sys: sys_clk.hz(),
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ahb1: ahb_freq.hz(),
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ahb2: ahb_freq.hz(),
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ahb3: shd_ahb_freq.hz(),
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apb1: apb1_freq.hz(),
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apb2: apb2_freq.hz(),
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apb3: apb3_freq.hz(),
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apb1_tim: apb1_tim_freq.hz(),
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apb2_tim: apb2_tim_freq.hz(),
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});
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}
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