396 lines
15 KiB
Rust
396 lines
15 KiB
Rust
use core::cmp::min;
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use core::mem;
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use core::pin::Pin;
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use core::sync::atomic::{compiler_fence, Ordering};
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use core::task::{Context, Poll};
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use embassy::interrupt::InterruptExt;
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use embassy::io::{AsyncBufRead, AsyncWrite, Result};
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use embassy::util::{Unborrow, WakerRegistration};
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use embassy_extras::peripheral::{PeripheralMutex, PeripheralState};
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use embassy_extras::ring_buffer::RingBuffer;
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use embassy_extras::{low_power_wait_until, unborrow};
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use crate::fmt::{panic, *};
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use crate::gpio::sealed::Pin as _;
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use crate::gpio::{OptionalPin as GpioOptionalPin, Pin as GpioPin};
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use crate::pac;
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use crate::ppi::{AnyConfigurableChannel, ConfigurableChannel, Event, Ppi, Task};
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use crate::timer::Instance as TimerInstance;
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use crate::uarte::{Config, Instance as UarteInstance};
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// Re-export SVD variants to allow user to directly set values
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pub use pac::uarte0::{baudrate::BAUDRATE_A as Baudrate, config::PARITY_A as Parity};
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#[derive(Copy, Clone, Debug, PartialEq)]
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enum RxState {
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Idle,
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Receiving,
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}
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#[derive(Copy, Clone, Debug, PartialEq)]
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enum TxState {
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Idle,
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Transmitting(usize),
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}
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struct State<'d, U: UarteInstance, T: TimerInstance> {
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uarte: U,
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timer: T,
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_ppi_ch1: Ppi<'d, AnyConfigurableChannel>,
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_ppi_ch2: Ppi<'d, AnyConfigurableChannel>,
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rx: RingBuffer<'d>,
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rx_state: RxState,
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rx_waker: WakerRegistration,
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tx: RingBuffer<'d>,
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tx_state: TxState,
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tx_waker: WakerRegistration,
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}
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/// Interface to a UARTE instance
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///
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/// This is a very basic interface that comes with the following limitations:
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/// - The UARTE instances share the same address space with instances of UART.
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/// You need to make sure that conflicting instances
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/// are disabled before using `Uarte`. See product specification:
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/// - nrf52832: Section 15.2
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/// - nrf52840: Section 6.1.2
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pub struct BufferedUarte<'d, U: UarteInstance, T: TimerInstance> {
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inner: PeripheralMutex<State<'d, U, T>>,
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}
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impl<'d, U: UarteInstance, T: TimerInstance> BufferedUarte<'d, U, T> {
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/// unsafe: may not leak self or futures
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pub unsafe fn new(
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uarte: impl Unborrow<Target = U> + 'd,
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timer: impl Unborrow<Target = T> + 'd,
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ppi_ch1: impl Unborrow<Target = impl ConfigurableChannel> + 'd,
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ppi_ch2: impl Unborrow<Target = impl ConfigurableChannel> + 'd,
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irq: impl Unborrow<Target = U::Interrupt> + 'd,
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rxd: impl Unborrow<Target = impl GpioPin> + 'd,
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txd: impl Unborrow<Target = impl GpioPin> + 'd,
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cts: impl Unborrow<Target = impl GpioOptionalPin> + 'd,
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rts: impl Unborrow<Target = impl GpioOptionalPin> + 'd,
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config: Config,
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rx_buffer: &'d mut [u8],
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tx_buffer: &'d mut [u8],
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) -> Self {
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unborrow!(uarte, timer, ppi_ch1, ppi_ch2, irq, rxd, txd, cts, rts);
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let r = U::regs();
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let rt = timer.regs();
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rxd.conf().write(|w| w.input().connect().drive().h0h1());
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r.psel.rxd.write(|w| unsafe { w.bits(rxd.psel_bits()) });
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txd.set_high();
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txd.conf().write(|w| w.dir().output().drive().h0h1());
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r.psel.txd.write(|w| unsafe { w.bits(txd.psel_bits()) });
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if let Some(pin) = rts.pin_mut() {
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pin.set_high();
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pin.conf().write(|w| w.dir().output().drive().h0h1());
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}
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r.psel.cts.write(|w| unsafe { w.bits(cts.psel_bits()) });
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if let Some(pin) = cts.pin_mut() {
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pin.conf().write(|w| w.input().connect().drive().h0h1());
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}
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r.psel.rts.write(|w| unsafe { w.bits(rts.psel_bits()) });
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r.baudrate.write(|w| w.baudrate().variant(config.baudrate));
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r.config.write(|w| w.parity().variant(config.parity));
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// Configure
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let hardware_flow_control = match (rts.pin().is_some(), cts.pin().is_some()) {
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(false, false) => false,
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(true, true) => true,
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_ => panic!("RTS and CTS pins must be either both set or none set."),
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};
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r.config.write(|w| {
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w.hwfc().bit(hardware_flow_control);
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w.parity().variant(config.parity);
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w
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});
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r.baudrate.write(|w| w.baudrate().variant(config.baudrate));
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// Enable interrupts
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r.intenset.write(|w| w.endrx().set().endtx().set());
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// Disable the irq, let the Registration enable it when everything is set up.
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irq.disable();
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irq.pend();
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// Enable UARTE instance
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r.enable.write(|w| w.enable().enabled());
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// BAUDRATE register values are `baudrate * 2^32 / 16000000`
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// source: https://devzone.nordicsemi.com/f/nordic-q-a/391/uart-baudrate-register-values
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//
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// We want to stop RX if line is idle for 2 bytes worth of time
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// That is 20 bits (each byte is 1 start bit + 8 data bits + 1 stop bit)
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// This gives us the amount of 16M ticks for 20 bits.
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let timeout = 0x8000_0000 / (config.baudrate as u32 / 40);
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rt.tasks_stop.write(|w| unsafe { w.bits(1) });
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rt.bitmode.write(|w| w.bitmode()._32bit());
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rt.prescaler.write(|w| unsafe { w.prescaler().bits(0) });
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rt.cc[0].write(|w| unsafe { w.bits(timeout) });
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rt.mode.write(|w| w.mode().timer());
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rt.shorts.write(|w| {
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w.compare0_clear().set_bit();
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w.compare0_stop().set_bit();
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w
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});
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let mut ppi_ch1 = Ppi::new(ppi_ch1.degrade_configurable());
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ppi_ch1.set_event(Event::from_reg(&r.events_rxdrdy));
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ppi_ch1.set_task(Task::from_reg(&rt.tasks_clear));
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ppi_ch1.set_fork_task(Task::from_reg(&rt.tasks_start));
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ppi_ch1.enable();
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let mut ppi_ch2 = Ppi::new(ppi_ch2.degrade_configurable());
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ppi_ch2.set_event(Event::from_reg(&rt.events_compare[0]));
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ppi_ch2.set_task(Task::from_reg(&r.tasks_stoprx));
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ppi_ch2.enable();
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BufferedUarte {
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inner: PeripheralMutex::new(
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State {
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uarte,
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timer,
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_ppi_ch1: ppi_ch1,
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_ppi_ch2: ppi_ch2,
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rx: RingBuffer::new(rx_buffer),
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rx_state: RxState::Idle,
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rx_waker: WakerRegistration::new(),
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tx: RingBuffer::new(tx_buffer),
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tx_state: TxState::Idle,
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tx_waker: WakerRegistration::new(),
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},
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irq,
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),
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}
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}
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pub fn set_baudrate(self: Pin<&mut Self>, baudrate: Baudrate) {
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self.inner().with(|state, _irq| {
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let r = U::regs();
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let rt = state.timer.regs();
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let timeout = 0x8000_0000 / (baudrate as u32 / 40);
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rt.cc[0].write(|w| unsafe { w.bits(timeout) });
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rt.tasks_clear.write(|w| unsafe { w.bits(1) });
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r.baudrate.write(|w| w.baudrate().variant(baudrate));
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});
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}
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fn inner(self: Pin<&mut Self>) -> Pin<&mut PeripheralMutex<State<'d, U, T>>> {
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unsafe { Pin::new_unchecked(&mut self.get_unchecked_mut().inner) }
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}
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}
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impl<'d, U: UarteInstance, T: TimerInstance> AsyncBufRead for BufferedUarte<'d, U, T> {
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fn poll_fill_buf(self: Pin<&mut Self>, cx: &mut Context<'_>) -> Poll<Result<&[u8]>> {
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let mut inner = self.inner();
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inner.as_mut().register_interrupt();
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inner.with(|state, _irq| {
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// Conservative compiler fence to prevent optimizations that do not
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// take in to account actions by DMA. The fence has been placed here,
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// before any DMA action has started
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compiler_fence(Ordering::SeqCst);
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trace!("poll_read");
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// We have data ready in buffer? Return it.
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let buf = state.rx.pop_buf();
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if !buf.is_empty() {
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trace!(" got {:?} {:?}", buf.as_ptr() as u32, buf.len());
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let buf: &[u8] = buf;
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let buf: &[u8] = unsafe { mem::transmute(buf) };
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return Poll::Ready(Ok(buf));
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}
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trace!(" empty");
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state.rx_waker.register(cx.waker());
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Poll::<Result<&[u8]>>::Pending
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})
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}
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fn consume(self: Pin<&mut Self>, amt: usize) {
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let mut inner = self.inner();
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inner.as_mut().register_interrupt();
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inner.with(|state, irq| {
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trace!("consume {:?}", amt);
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state.rx.pop(amt);
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irq.pend();
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})
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}
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}
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impl<'d, U: UarteInstance, T: TimerInstance> AsyncWrite for BufferedUarte<'d, U, T> {
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fn poll_write(self: Pin<&mut Self>, cx: &mut Context<'_>, buf: &[u8]) -> Poll<Result<usize>> {
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let mut inner = self.inner();
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inner.as_mut().register_interrupt();
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inner.with(|state, irq| {
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trace!("poll_write: {:?}", buf.len());
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let tx_buf = state.tx.push_buf();
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if tx_buf.is_empty() {
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trace!("poll_write: pending");
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state.tx_waker.register(cx.waker());
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return Poll::Pending;
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}
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let n = min(tx_buf.len(), buf.len());
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tx_buf[..n].copy_from_slice(&buf[..n]);
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state.tx.push(n);
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trace!("poll_write: queued {:?}", n);
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// Conservative compiler fence to prevent optimizations that do not
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// take in to account actions by DMA. The fence has been placed here,
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// before any DMA action has started
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compiler_fence(Ordering::SeqCst);
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irq.pend();
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Poll::Ready(Ok(n))
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})
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}
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}
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impl<'a, U: UarteInstance, T: TimerInstance> Drop for State<'a, U, T> {
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fn drop(&mut self) {
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let r = U::regs();
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let rt = self.timer.regs();
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// TODO this probably deadlocks. do like Uarte instead.
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rt.tasks_stop.write(|w| unsafe { w.bits(1) });
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if let RxState::Receiving = self.rx_state {
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r.tasks_stoprx.write(|w| unsafe { w.bits(1) });
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}
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if let TxState::Transmitting(_) = self.tx_state {
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r.tasks_stoptx.write(|w| unsafe { w.bits(1) });
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}
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if let RxState::Receiving = self.rx_state {
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low_power_wait_until(|| r.events_endrx.read().bits() == 1);
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}
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if let TxState::Transmitting(_) = self.tx_state {
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low_power_wait_until(|| r.events_endtx.read().bits() == 1);
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}
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}
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}
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impl<'a, U: UarteInstance, T: TimerInstance> PeripheralState for State<'a, U, T> {
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type Interrupt = U::Interrupt;
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fn on_interrupt(&mut self) {
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trace!("irq: start");
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let r = U::regs();
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let rt = self.timer.regs();
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loop {
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match self.rx_state {
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RxState::Idle => {
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trace!(" irq_rx: in state idle");
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let buf = self.rx.push_buf();
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if !buf.is_empty() {
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trace!(" irq_rx: starting {:?}", buf.len());
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self.rx_state = RxState::Receiving;
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// Set up the DMA read
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r.rxd.ptr.write(|w|
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// The PTR field is a full 32 bits wide and accepts the full range
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// of values.
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unsafe { w.ptr().bits(buf.as_ptr() as u32) });
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r.rxd.maxcnt.write(|w|
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// We're giving it the length of the buffer, so no danger of
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// accessing invalid memory. We have verified that the length of the
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// buffer fits in an `u8`, so the cast to `u8` is also fine.
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//
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// The MAXCNT field is at least 8 bits wide and accepts the full
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// range of values.
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unsafe { w.maxcnt().bits(buf.len() as _) });
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trace!(" irq_rx: buf {:?} {:?}", buf.as_ptr() as u32, buf.len());
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// Start UARTE Receive transaction
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r.tasks_startrx.write(|w|
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// `1` is a valid value to write to task registers.
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unsafe { w.bits(1) });
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}
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break;
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}
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RxState::Receiving => {
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trace!(" irq_rx: in state receiving");
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if r.events_endrx.read().bits() != 0 {
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rt.tasks_stop.write(|w| unsafe { w.bits(1) });
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let n: usize = r.rxd.amount.read().amount().bits() as usize;
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trace!(" irq_rx: endrx {:?}", n);
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self.rx.push(n);
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r.events_endrx.reset();
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self.rx_waker.wake();
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self.rx_state = RxState::Idle;
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} else {
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break;
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}
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}
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}
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}
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loop {
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match self.tx_state {
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TxState::Idle => {
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trace!(" irq_tx: in state Idle");
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let buf = self.tx.pop_buf();
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if !buf.is_empty() {
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trace!(" irq_tx: starting {:?}", buf.len());
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self.tx_state = TxState::Transmitting(buf.len());
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// Set up the DMA write
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r.txd.ptr.write(|w|
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// The PTR field is a full 32 bits wide and accepts the full range
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// of values.
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unsafe { w.ptr().bits(buf.as_ptr() as u32) });
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r.txd.maxcnt.write(|w|
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// We're giving it the length of the buffer, so no danger of
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// accessing invalid memory. We have verified that the length of the
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// buffer fits in an `u8`, so the cast to `u8` is also fine.
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//
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// The MAXCNT field is 8 bits wide and accepts the full range of
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// values.
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unsafe { w.maxcnt().bits(buf.len() as _) });
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// Start UARTE Transmit transaction
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r.tasks_starttx.write(|w|
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// `1` is a valid value to write to task registers.
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unsafe { w.bits(1) });
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}
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break;
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}
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TxState::Transmitting(n) => {
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trace!(" irq_tx: in state Transmitting");
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if r.events_endtx.read().bits() != 0 {
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r.events_endtx.reset();
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trace!(" irq_tx: endtx {:?}", n);
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self.tx.pop(n);
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self.tx_waker.wake();
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self.tx_state = TxState::Idle;
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} else {
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break;
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}
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}
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}
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}
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trace!("irq: end");
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}
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}
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