553 lines
16 KiB
Rust
553 lines
16 KiB
Rust
use core::convert::Infallible;
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use core::future::Future;
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use core::marker::PhantomData;
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use core::task::{Context, Poll};
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use embassy::interrupt::{Interrupt, InterruptExt};
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use embassy::waitqueue::AtomicWaker;
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use embassy_hal_common::unsafe_impl_unborrow;
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use futures::future::poll_fn;
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use crate::gpio::sealed::Pin as _;
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use crate::gpio::{AnyPin, Flex, Input, Output, Pin as GpioPin};
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use crate::pac;
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use crate::ppi::{Event, Task};
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use crate::{interrupt, peripherals};
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pub const CHANNEL_COUNT: usize = 8;
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#[cfg(any(feature = "nrf52833", feature = "nrf52840"))]
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pub const PIN_COUNT: usize = 48;
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#[cfg(not(any(feature = "nrf52833", feature = "nrf52840")))]
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pub const PIN_COUNT: usize = 32;
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#[allow(clippy::declare_interior_mutable_const)]
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const NEW_AW: AtomicWaker = AtomicWaker::new();
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static CHANNEL_WAKERS: [AtomicWaker; CHANNEL_COUNT] = [NEW_AW; CHANNEL_COUNT];
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static PORT_WAKERS: [AtomicWaker; PIN_COUNT] = [NEW_AW; PIN_COUNT];
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pub enum InputChannelPolarity {
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None,
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HiToLo,
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LoToHi,
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Toggle,
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}
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/// Polarity of the `task out` operation.
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pub enum OutputChannelPolarity {
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Set,
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Clear,
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Toggle,
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}
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fn regs() -> &'static pac::gpiote::RegisterBlock {
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cfg_if::cfg_if! {
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if #[cfg(any(feature="nrf5340-app-s", feature="nrf9160-s"))] {
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unsafe { &*pac::GPIOTE0::ptr() }
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} else if #[cfg(any(feature="nrf5340-app-ns", feature="nrf9160-ns"))] {
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unsafe { &*pac::GPIOTE1::ptr() }
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} else {
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unsafe { &*pac::GPIOTE::ptr() }
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}
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}
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}
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pub(crate) fn init(irq_prio: crate::interrupt::Priority) {
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#[cfg(any(feature = "nrf52833", feature = "nrf52840"))]
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let ports = unsafe { &[&*pac::P0::ptr(), &*pac::P1::ptr()] };
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#[cfg(not(any(feature = "nrf52833", feature = "nrf52840")))]
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let ports = unsafe { &[&*pac::P0::ptr()] };
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for &p in ports {
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// Enable latched detection
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p.detectmode.write(|w| w.detectmode().ldetect());
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// Clear latch
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p.latch.write(|w| unsafe { w.bits(0xFFFFFFFF) })
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}
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// Enable interrupts
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cfg_if::cfg_if! {
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if #[cfg(any(feature="nrf5340-app-s", feature="nrf9160-s"))] {
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let irq = unsafe { interrupt::GPIOTE0::steal() };
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} else if #[cfg(any(feature="nrf5340-app-ns", feature="nrf9160-ns"))] {
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let irq = unsafe { interrupt::GPIOTE1::steal() };
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} else {
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let irq = unsafe { interrupt::GPIOTE::steal() };
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}
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}
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irq.unpend();
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irq.set_priority(irq_prio);
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irq.enable();
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let g = regs();
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g.events_port.write(|w| w);
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g.intenset.write(|w| w.port().set());
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}
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cfg_if::cfg_if! {
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if #[cfg(any(feature="nrf5340-app-s", feature="nrf9160-s"))] {
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#[interrupt]
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fn GPIOTE0() {
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unsafe { handle_gpiote_interrupt() };
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}
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} else if #[cfg(any(feature="nrf5340-app-ns", feature="nrf9160-ns"))] {
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#[interrupt]
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fn GPIOTE1() {
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unsafe { handle_gpiote_interrupt() };
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}
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} else {
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#[interrupt]
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fn GPIOTE() {
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unsafe { handle_gpiote_interrupt() };
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}
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}
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}
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unsafe fn handle_gpiote_interrupt() {
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let g = regs();
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for i in 0..CHANNEL_COUNT {
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if g.events_in[i].read().bits() != 0 {
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g.intenclr.write(|w| w.bits(1 << i));
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CHANNEL_WAKERS[i].wake();
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}
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}
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if g.events_port.read().bits() != 0 {
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g.events_port.write(|w| w);
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#[cfg(any(feature = "nrf52833", feature = "nrf52840"))]
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let ports = &[&*pac::P0::ptr(), &*pac::P1::ptr()];
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#[cfg(not(any(feature = "nrf52833", feature = "nrf52840")))]
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let ports = &[&*pac::P0::ptr()];
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for (port, &p) in ports.iter().enumerate() {
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let bits = p.latch.read().bits();
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for pin in BitIter(bits) {
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p.pin_cnf[pin as usize].modify(|_, w| w.sense().disabled());
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PORT_WAKERS[port * 32 + pin as usize].wake();
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}
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p.latch.write(|w| w.bits(bits));
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}
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}
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}
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struct BitIter(u32);
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impl Iterator for BitIter {
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type Item = u32;
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fn next(&mut self) -> Option<Self::Item> {
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match self.0.trailing_zeros() {
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32 => None,
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b => {
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self.0 &= !(1 << b);
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Some(b)
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}
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}
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}
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}
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/// GPIOTE channel driver in input mode
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pub struct InputChannel<'d, C: Channel, T: GpioPin> {
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ch: C,
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pin: Input<'d, T>,
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}
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impl<'d, C: Channel, T: GpioPin> Drop for InputChannel<'d, C, T> {
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fn drop(&mut self) {
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let g = regs();
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let num = self.ch.number();
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g.config[num].write(|w| w.mode().disabled());
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g.intenclr.write(|w| unsafe { w.bits(1 << num) });
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}
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}
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impl<'d, C: Channel, T: GpioPin> InputChannel<'d, C, T> {
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pub fn new(ch: C, pin: Input<'d, T>, polarity: InputChannelPolarity) -> Self {
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let g = regs();
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let num = ch.number();
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g.config[num].write(|w| {
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match polarity {
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InputChannelPolarity::HiToLo => w.mode().event().polarity().hi_to_lo(),
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InputChannelPolarity::LoToHi => w.mode().event().polarity().lo_to_hi(),
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InputChannelPolarity::None => w.mode().event().polarity().none(),
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InputChannelPolarity::Toggle => w.mode().event().polarity().toggle(),
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};
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#[cfg(any(feature = "nrf52833", feature = "nrf52840"))]
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w.port().bit(match pin.pin.pin.port() {
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crate::gpio::Port::Port0 => false,
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crate::gpio::Port::Port1 => true,
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});
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unsafe { w.psel().bits(pin.pin.pin.pin()) }
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});
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g.events_in[num].reset();
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InputChannel { ch, pin }
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}
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pub async fn wait(&self) {
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let g = regs();
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let num = self.ch.number();
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// Enable interrupt
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g.events_in[num].reset();
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g.intenset.write(|w| unsafe { w.bits(1 << num) });
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poll_fn(|cx| {
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CHANNEL_WAKERS[num].register(cx.waker());
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if g.events_in[num].read().bits() != 0 {
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Poll::Ready(())
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} else {
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Poll::Pending
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}
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})
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.await;
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}
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/// Returns the IN event, for use with PPI.
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pub fn event_in(&self) -> Event {
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let g = regs();
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Event::from_reg(&g.events_in[self.ch.number()])
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}
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}
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/// GPIOTE channel driver in output mode
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pub struct OutputChannel<'d, C: Channel, T: GpioPin> {
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ch: C,
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_pin: Output<'d, T>,
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}
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impl<'d, C: Channel, T: GpioPin> Drop for OutputChannel<'d, C, T> {
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fn drop(&mut self) {
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let g = regs();
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let num = self.ch.number();
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g.config[num].write(|w| w.mode().disabled());
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g.intenclr.write(|w| unsafe { w.bits(1 << num) });
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}
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}
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impl<'d, C: Channel, T: GpioPin> OutputChannel<'d, C, T> {
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pub fn new(ch: C, pin: Output<'d, T>, polarity: OutputChannelPolarity) -> Self {
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let g = regs();
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let num = ch.number();
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g.config[num].write(|w| {
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w.mode().task();
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match pin.is_set_high() {
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true => w.outinit().high(),
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false => w.outinit().low(),
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};
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match polarity {
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OutputChannelPolarity::Set => w.polarity().lo_to_hi(),
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OutputChannelPolarity::Clear => w.polarity().hi_to_lo(),
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OutputChannelPolarity::Toggle => w.polarity().toggle(),
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};
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#[cfg(any(feature = "nrf52833", feature = "nrf52840"))]
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w.port().bit(match pin.pin.pin.port() {
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crate::gpio::Port::Port0 => false,
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crate::gpio::Port::Port1 => true,
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});
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unsafe { w.psel().bits(pin.pin.pin.pin()) }
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});
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OutputChannel { ch, _pin: pin }
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}
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/// Triggers `task out` (as configured with task_out_polarity, defaults to Toggle).
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pub fn out(&self) {
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let g = regs();
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g.tasks_out[self.ch.number()].write(|w| unsafe { w.bits(1) });
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}
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/// Triggers `task set` (set associated pin high).
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#[cfg(not(feature = "nrf51"))]
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pub fn set(&self) {
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let g = regs();
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g.tasks_set[self.ch.number()].write(|w| unsafe { w.bits(1) });
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}
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/// Triggers `task clear` (set associated pin low).
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#[cfg(not(feature = "nrf51"))]
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pub fn clear(&self) {
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let g = regs();
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g.tasks_clr[self.ch.number()].write(|w| unsafe { w.bits(1) });
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}
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/// Returns the OUT task, for use with PPI.
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pub fn task_out(&self) -> Task {
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let g = regs();
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Task::from_reg(&g.tasks_out[self.ch.number()])
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}
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/// Returns the CLR task, for use with PPI.
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#[cfg(not(feature = "nrf51"))]
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pub fn task_clr(&self) -> Task {
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let g = regs();
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Task::from_reg(&g.tasks_clr[self.ch.number()])
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}
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/// Returns the SET task, for use with PPI.
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#[cfg(not(feature = "nrf51"))]
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pub fn task_set(&self) -> Task {
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let g = regs();
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Task::from_reg(&g.tasks_set[self.ch.number()])
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}
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}
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// =======================
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pub(crate) struct PortInputFuture<'a> {
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pin_port: u8,
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phantom: PhantomData<&'a mut AnyPin>,
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}
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impl<'a> Unpin for PortInputFuture<'a> {}
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impl<'a> Drop for PortInputFuture<'a> {
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fn drop(&mut self) {
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let pin = unsafe { AnyPin::steal(self.pin_port) };
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pin.conf().modify(|_, w| w.sense().disabled());
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}
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}
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impl<'a> Future for PortInputFuture<'a> {
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type Output = ();
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fn poll(self: core::pin::Pin<&mut Self>, cx: &mut Context<'_>) -> Poll<Self::Output> {
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PORT_WAKERS[self.pin_port as usize].register(cx.waker());
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let pin = unsafe { AnyPin::steal(self.pin_port) };
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if pin.conf().read().sense().is_disabled() {
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Poll::Ready(())
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} else {
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Poll::Pending
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}
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}
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}
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impl<'d, T: GpioPin> Input<'d, T> {
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pub async fn wait_for_high(&mut self) {
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self.pin.wait_for_high().await
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}
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pub async fn wait_for_low(&mut self) {
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self.pin.wait_for_low().await
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}
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pub async fn wait_for_rising_edge(&mut self) {
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self.pin.wait_for_rising_edge().await
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}
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pub async fn wait_for_falling_edge(&mut self) {
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self.pin.wait_for_falling_edge().await
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}
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pub async fn wait_for_any_edge(&mut self) {
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self.pin.wait_for_any_edge().await
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}
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}
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impl<'d, T: GpioPin> Flex<'d, T> {
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pub async fn wait_for_high(&mut self) {
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self.pin.conf().modify(|_, w| w.sense().high());
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PortInputFuture {
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pin_port: self.pin.pin_port(),
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phantom: PhantomData,
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}
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.await
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}
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pub async fn wait_for_low(&mut self) {
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self.pin.conf().modify(|_, w| w.sense().low());
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PortInputFuture {
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pin_port: self.pin.pin_port(),
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phantom: PhantomData,
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}
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.await
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}
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pub async fn wait_for_rising_edge(&mut self) {
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self.wait_for_low().await;
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self.wait_for_high().await;
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}
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pub async fn wait_for_falling_edge(&mut self) {
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self.wait_for_high().await;
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self.wait_for_low().await;
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}
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pub async fn wait_for_any_edge(&mut self) {
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if self.is_high() {
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self.pin.conf().modify(|_, w| w.sense().low());
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} else {
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self.pin.conf().modify(|_, w| w.sense().high());
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}
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PortInputFuture {
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pin_port: self.pin.pin_port(),
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phantom: PhantomData,
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}
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.await
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}
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}
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// =======================
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mod sealed {
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pub trait Channel {}
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}
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pub trait Channel: sealed::Channel + Sized {
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fn number(&self) -> usize;
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fn degrade(self) -> AnyChannel {
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AnyChannel {
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number: self.number() as u8,
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}
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}
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}
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pub struct AnyChannel {
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number: u8,
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}
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unsafe_impl_unborrow!(AnyChannel);
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impl sealed::Channel for AnyChannel {}
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impl Channel for AnyChannel {
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fn number(&self) -> usize {
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self.number as usize
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}
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}
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macro_rules! impl_channel {
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($type:ident, $number:expr) => {
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impl sealed::Channel for peripherals::$type {}
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impl Channel for peripherals::$type {
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fn number(&self) -> usize {
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$number as usize
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}
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}
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};
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}
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impl_channel!(GPIOTE_CH0, 0);
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impl_channel!(GPIOTE_CH1, 1);
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impl_channel!(GPIOTE_CH2, 2);
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impl_channel!(GPIOTE_CH3, 3);
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impl_channel!(GPIOTE_CH4, 4);
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impl_channel!(GPIOTE_CH5, 5);
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impl_channel!(GPIOTE_CH6, 6);
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impl_channel!(GPIOTE_CH7, 7);
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// ====================
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mod eh02 {
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use super::*;
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impl<'d, C: Channel, T: GpioPin> embedded_hal_02::digital::v2::InputPin for InputChannel<'d, C, T> {
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type Error = Infallible;
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fn is_high(&self) -> Result<bool, Self::Error> {
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Ok(self.pin.is_high())
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}
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fn is_low(&self) -> Result<bool, Self::Error> {
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Ok(self.pin.is_low())
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}
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}
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}
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#[cfg(feature = "unstable-traits")]
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mod eh1 {
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use super::*;
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impl<'d, C: Channel, T: GpioPin> embedded_hal_1::digital::ErrorType for InputChannel<'d, C, T> {
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type Error = Infallible;
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}
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impl<'d, C: Channel, T: GpioPin> embedded_hal_1::digital::blocking::InputPin
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for InputChannel<'d, C, T>
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{
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fn is_high(&self) -> Result<bool, Self::Error> {
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Ok(self.pin.is_high())
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}
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fn is_low(&self) -> Result<bool, Self::Error> {
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Ok(self.pin.is_low())
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}
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}
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}
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cfg_if::cfg_if! {
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if #[cfg(all(feature = "unstable-traits", feature = "nightly"))] {
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use futures::FutureExt;
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impl<'d, T: GpioPin> embedded_hal_async::digital::Wait for Input<'d, T> {
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type WaitForHighFuture<'a> = impl Future<Output = Result<(), Self::Error>> + 'a where Self: 'a;
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fn wait_for_high<'a>(&'a mut self) -> Self::WaitForHighFuture<'a> {
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self.wait_for_high().map(Ok)
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}
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type WaitForLowFuture<'a> = impl Future<Output = Result<(), Self::Error>> + 'a where Self: 'a;
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fn wait_for_low<'a>(&'a mut self) -> Self::WaitForLowFuture<'a> {
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self.wait_for_low().map(Ok)
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}
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type WaitForRisingEdgeFuture<'a> = impl Future<Output = Result<(), Self::Error>> + 'a where Self: 'a;
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fn wait_for_rising_edge<'a>(&'a mut self) -> Self::WaitForRisingEdgeFuture<'a> {
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self.wait_for_rising_edge().map(Ok)
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}
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type WaitForFallingEdgeFuture<'a> = impl Future<Output = Result<(), Self::Error>> + 'a where Self: 'a;
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fn wait_for_falling_edge<'a>(&'a mut self) -> Self::WaitForFallingEdgeFuture<'a> {
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self.wait_for_falling_edge().map(Ok)
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|
}
|
|
|
|
type WaitForAnyEdgeFuture<'a> = impl Future<Output = Result<(), Self::Error>> + 'a where Self: 'a;
|
|
|
|
fn wait_for_any_edge<'a>(&'a mut self) -> Self::WaitForAnyEdgeFuture<'a> {
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|
self.wait_for_any_edge().map(Ok)
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|
}
|
|
}
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|
|
|
impl<'d, T: GpioPin> embedded_hal_async::digital::Wait for Flex<'d, T> {
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|
type WaitForHighFuture<'a> = impl Future<Output = Result<(), Self::Error>> + 'a where Self: 'a;
|
|
|
|
fn wait_for_high<'a>(&'a mut self) -> Self::WaitForHighFuture<'a> {
|
|
self.wait_for_high().map(Ok)
|
|
}
|
|
|
|
type WaitForLowFuture<'a> = impl Future<Output = Result<(), Self::Error>> + 'a where Self: 'a;
|
|
|
|
fn wait_for_low<'a>(&'a mut self) -> Self::WaitForLowFuture<'a> {
|
|
self.wait_for_low().map(Ok)
|
|
}
|
|
|
|
type WaitForRisingEdgeFuture<'a> = impl Future<Output = Result<(), Self::Error>> + 'a where Self: 'a;
|
|
|
|
fn wait_for_rising_edge<'a>(&'a mut self) -> Self::WaitForRisingEdgeFuture<'a> {
|
|
self.wait_for_rising_edge().map(Ok)
|
|
}
|
|
|
|
type WaitForFallingEdgeFuture<'a> = impl Future<Output = Result<(), Self::Error>> + 'a where Self: 'a;
|
|
|
|
fn wait_for_falling_edge<'a>(&'a mut self) -> Self::WaitForFallingEdgeFuture<'a> {
|
|
self.wait_for_falling_edge().map(Ok)
|
|
}
|
|
|
|
type WaitForAnyEdgeFuture<'a> = impl Future<Output = Result<(), Self::Error>> + 'a where Self: 'a;
|
|
|
|
fn wait_for_any_edge<'a>(&'a mut self) -> Self::WaitForAnyEdgeFuture<'a> {
|
|
self.wait_for_any_edge().map(Ok)
|
|
}
|
|
}
|
|
}
|
|
}
|