872 lines
28 KiB
Rust
872 lines
28 KiB
Rust
use core::future;
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use core::marker::PhantomData;
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use core::task::Poll;
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use embassy_hal_internal::{into_ref, PeripheralRef};
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use embassy_sync::waitqueue::AtomicWaker;
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use pac::i2c;
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use crate::gpio::AnyPin;
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use crate::interrupt::typelevel::{Binding, Interrupt};
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use crate::{interrupt, pac, peripherals, Peripheral};
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/// I2C error abort reason
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#[derive(Debug, PartialEq, Eq)]
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#[cfg_attr(feature = "defmt", derive(defmt::Format))]
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pub enum AbortReason {
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/// A bus operation was not acknowledged, e.g. due to the addressed device
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/// not being available on the bus or the device not being ready to process
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/// requests at the moment
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NoAcknowledge,
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/// The arbitration was lost, e.g. electrical problems with the clock signal
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ArbitrationLoss,
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/// Transmit ended with data still in fifo
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TxNotEmpty(u16),
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Other(u32),
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}
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/// I2C error
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#[derive(Debug, PartialEq, Eq)]
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#[cfg_attr(feature = "defmt", derive(defmt::Format))]
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pub enum Error {
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/// I2C abort with error
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Abort(AbortReason),
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/// User passed in a read buffer that was 0 length
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InvalidReadBufferLength,
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/// User passed in a write buffer that was 0 length
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InvalidWriteBufferLength,
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/// Target i2c address is out of range
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AddressOutOfRange(u16),
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/// Target i2c address is reserved
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AddressReserved(u16),
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}
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#[non_exhaustive]
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#[derive(Copy, Clone)]
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pub struct Config {
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pub frequency: u32,
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}
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impl Default for Config {
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fn default() -> Self {
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Self { frequency: 100_000 }
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}
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}
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pub const FIFO_SIZE: u8 = 16;
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pub struct I2c<'d, T: Instance, M: Mode> {
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phantom: PhantomData<(&'d mut T, M)>,
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}
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impl<'d, T: Instance> I2c<'d, T, Blocking> {
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pub fn new_blocking(
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peri: impl Peripheral<P = T> + 'd,
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scl: impl Peripheral<P = impl SclPin<T>> + 'd,
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sda: impl Peripheral<P = impl SdaPin<T>> + 'd,
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config: Config,
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) -> Self {
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into_ref!(scl, sda);
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Self::new_inner(peri, scl.map_into(), sda.map_into(), config)
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}
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}
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impl<'d, T: Instance> I2c<'d, T, Async> {
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pub fn new_async(
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peri: impl Peripheral<P = T> + 'd,
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scl: impl Peripheral<P = impl SclPin<T>> + 'd,
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sda: impl Peripheral<P = impl SdaPin<T>> + 'd,
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_irq: impl Binding<T::Interrupt, InterruptHandler<T>>,
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config: Config,
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) -> Self {
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into_ref!(scl, sda);
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let i2c = Self::new_inner(peri, scl.map_into(), sda.map_into(), config);
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let r = T::regs();
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// mask everything initially
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r.ic_intr_mask().write_value(i2c::regs::IcIntrMask(0));
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T::Interrupt::unpend();
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unsafe { T::Interrupt::enable() };
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i2c
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}
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/// Calls `f` to check if we are ready or not.
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/// If not, `g` is called once the waker is set (to eg enable the required interrupts).
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async fn wait_on<F, U, G>(&mut self, mut f: F, mut g: G) -> U
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where
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F: FnMut(&mut Self) -> Poll<U>,
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G: FnMut(&mut Self),
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{
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future::poll_fn(|cx| {
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let r = f(self);
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if r.is_pending() {
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T::waker().register(cx.waker());
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g(self);
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}
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r
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})
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.await
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}
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async fn read_async_internal(&mut self, buffer: &mut [u8], restart: bool, send_stop: bool) -> Result<(), Error> {
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if buffer.is_empty() {
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return Err(Error::InvalidReadBufferLength);
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}
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let p = T::regs();
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let mut remaining = buffer.len();
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let mut remaining_queue = buffer.len();
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let mut abort_reason = Ok(());
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while remaining > 0 {
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// Waggle SCK - basically the same as write
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let tx_fifo_space = Self::tx_fifo_capacity();
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let mut batch = 0;
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debug_assert!(remaining_queue > 0);
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for _ in 0..remaining_queue.min(tx_fifo_space as usize) {
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remaining_queue -= 1;
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let last = remaining_queue == 0;
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batch += 1;
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p.ic_data_cmd().write(|w| {
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w.set_restart(restart && remaining_queue == buffer.len() - 1);
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w.set_stop(last && send_stop);
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w.set_cmd(true);
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});
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}
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// We've either run out of txfifo or just plain finished setting up
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// the clocks for the message - either way we need to wait for rx
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// data.
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debug_assert!(batch > 0);
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let res = self
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.wait_on(
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|me| {
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let rxfifo = Self::rx_fifo_len();
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if let Err(abort_reason) = me.read_and_clear_abort_reason() {
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Poll::Ready(Err(abort_reason))
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} else if rxfifo >= batch {
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Poll::Ready(Ok(rxfifo))
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} else {
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Poll::Pending
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}
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},
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|_me| {
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// Set the read threshold to the number of bytes we're
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// expecting so we don't get spurious interrupts.
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p.ic_rx_tl().write(|w| w.set_rx_tl(batch - 1));
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p.ic_intr_mask().modify(|w| {
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w.set_m_rx_full(true);
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w.set_m_tx_abrt(true);
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});
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},
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)
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.await;
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match res {
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Err(reason) => {
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abort_reason = Err(reason);
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break;
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}
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Ok(rxfifo) => {
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// Fetch things from rx fifo. We're assuming we're the only
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// rxfifo reader, so nothing else can take things from it.
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let rxbytes = (rxfifo as usize).min(remaining);
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let received = buffer.len() - remaining;
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for b in &mut buffer[received..received + rxbytes] {
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*b = p.ic_data_cmd().read().dat();
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}
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remaining -= rxbytes;
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}
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};
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}
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self.wait_stop_det(abort_reason, send_stop).await
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}
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async fn write_async_internal(
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&mut self,
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bytes: impl IntoIterator<Item = u8>,
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send_stop: bool,
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) -> Result<(), Error> {
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let p = T::regs();
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let mut bytes = bytes.into_iter().peekable();
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let res = 'xmit: loop {
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let tx_fifo_space = Self::tx_fifo_capacity();
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for _ in 0..tx_fifo_space {
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if let Some(byte) = bytes.next() {
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let last = bytes.peek().is_none();
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p.ic_data_cmd().write(|w| {
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w.set_stop(last && send_stop);
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w.set_cmd(false);
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w.set_dat(byte);
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});
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} else {
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break 'xmit Ok(());
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}
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}
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let res = self
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.wait_on(
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|me| {
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if let abort_reason @ Err(_) = me.read_and_clear_abort_reason() {
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Poll::Ready(abort_reason)
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} else if !Self::tx_fifo_full() {
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// resume if there's any space free in the tx fifo
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Poll::Ready(Ok(()))
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} else {
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Poll::Pending
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}
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},
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|_me| {
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// Set tx "free" threshold a little high so that we get
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// woken before the fifo completely drains to minimize
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// transfer stalls.
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p.ic_tx_tl().write(|w| w.set_tx_tl(1));
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p.ic_intr_mask().modify(|w| {
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w.set_m_tx_empty(true);
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w.set_m_tx_abrt(true);
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})
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},
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)
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.await;
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if res.is_err() {
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break res;
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}
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};
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self.wait_stop_det(res, send_stop).await
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}
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/// Helper to wait for a stop bit, for both tx and rx. If we had an abort,
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/// then we'll get a hardware-generated stop, otherwise wait for a stop if
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/// we're expecting it.
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///
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/// Also handles an abort which arises while processing the tx fifo.
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async fn wait_stop_det(&mut self, had_abort: Result<(), Error>, do_stop: bool) -> Result<(), Error> {
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if had_abort.is_err() || do_stop {
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let p = T::regs();
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let had_abort2 = self
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.wait_on(
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|me| {
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// We could see an abort while processing fifo backlog,
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// so handle it here.
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let abort = me.read_and_clear_abort_reason();
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if had_abort.is_ok() && abort.is_err() {
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Poll::Ready(abort)
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} else if p.ic_raw_intr_stat().read().stop_det() {
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Poll::Ready(Ok(()))
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} else {
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Poll::Pending
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}
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},
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|_me| {
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p.ic_intr_mask().modify(|w| {
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w.set_m_stop_det(true);
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w.set_m_tx_abrt(true);
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});
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},
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)
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.await;
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p.ic_clr_stop_det().read();
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had_abort.and(had_abort2)
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} else {
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had_abort
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}
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}
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pub async fn read_async(&mut self, addr: u16, buffer: &mut [u8]) -> Result<(), Error> {
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Self::setup(addr)?;
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self.read_async_internal(buffer, true, true).await
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}
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pub async fn write_async(&mut self, addr: u16, bytes: impl IntoIterator<Item = u8>) -> Result<(), Error> {
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Self::setup(addr)?;
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self.write_async_internal(bytes, true).await
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}
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pub async fn write_read_async(
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&mut self,
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addr: u16,
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bytes: impl IntoIterator<Item = u8>,
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buffer: &mut [u8],
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) -> Result<(), Error> {
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Self::setup(addr)?;
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self.write_async_internal(bytes, false).await?;
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self.read_async_internal(buffer, true, true).await
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}
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}
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pub struct InterruptHandler<T: Instance> {
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_uart: PhantomData<T>,
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}
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impl<T: Instance> interrupt::typelevel::Handler<T::Interrupt> for InterruptHandler<T> {
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// Mask interrupts and wake any task waiting for this interrupt
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unsafe fn on_interrupt() {
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let i2c = T::regs();
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i2c.ic_intr_mask().write_value(pac::i2c::regs::IcIntrMask::default());
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T::waker().wake();
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}
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}
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pub(crate) fn set_up_i2c_pin<'d, P, T>(pin: &P)
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where
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P: core::ops::Deref<Target = T>,
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T: crate::gpio::Pin,
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{
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pin.gpio().ctrl().write(|w| w.set_funcsel(3));
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pin.pad_ctrl().write(|w| {
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w.set_schmitt(true);
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w.set_slewfast(false);
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w.set_ie(true);
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w.set_od(false);
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w.set_pue(true);
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w.set_pde(false);
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});
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}
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impl<'d, T: Instance + 'd, M: Mode> I2c<'d, T, M> {
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fn new_inner(
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_peri: impl Peripheral<P = T> + 'd,
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scl: PeripheralRef<'d, AnyPin>,
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sda: PeripheralRef<'d, AnyPin>,
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config: Config,
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) -> Self {
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into_ref!(_peri);
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assert!(config.frequency <= 1_000_000);
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assert!(config.frequency > 0);
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let p = T::regs();
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let reset = T::reset();
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crate::reset::reset(reset);
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crate::reset::unreset_wait(reset);
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p.ic_enable().write(|w| w.set_enable(false));
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// Select controller mode & speed
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p.ic_con().modify(|w| {
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// Always use "fast" mode (<= 400 kHz, works fine for standard
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// mode too)
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w.set_speed(i2c::vals::Speed::FAST);
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w.set_master_mode(true);
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w.set_ic_slave_disable(true);
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w.set_ic_restart_en(true);
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w.set_tx_empty_ctrl(true);
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});
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// Set FIFO watermarks to 1 to make things simpler. This is encoded
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// by a register value of 0.
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p.ic_tx_tl().write(|w| w.set_tx_tl(0));
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p.ic_rx_tl().write(|w| w.set_rx_tl(0));
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// Configure SCL & SDA pins
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set_up_i2c_pin(&scl);
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set_up_i2c_pin(&sda);
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// Configure baudrate
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// There are some subtleties to I2C timing which we are completely
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// ignoring here See:
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// https://github.com/raspberrypi/pico-sdk/blob/bfcbefafc5d2a210551a4d9d80b4303d4ae0adf7/src/rp2_common/hardware_i2c/i2c.c#L69
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let clk_base = crate::clocks::clk_peri_freq();
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let period = (clk_base + config.frequency / 2) / config.frequency;
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let lcnt = period * 3 / 5; // spend 3/5 (60%) of the period low
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let hcnt = period - lcnt; // and 2/5 (40%) of the period high
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// Check for out-of-range divisors:
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assert!(hcnt <= 0xffff);
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assert!(lcnt <= 0xffff);
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assert!(hcnt >= 8);
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assert!(lcnt >= 8);
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// Per I2C-bus specification a device in standard or fast mode must
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// internally provide a hold time of at least 300ns for the SDA
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// signal to bridge the undefined region of the falling edge of SCL.
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// A smaller hold time of 120ns is used for fast mode plus.
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let sda_tx_hold_count = if config.frequency < 1_000_000 {
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// sda_tx_hold_count = clk_base [cycles/s] * 300ns * (1s /
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// 1e9ns) Reduce 300/1e9 to 3/1e7 to avoid numbers that don't
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// fit in uint. Add 1 to avoid division truncation.
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((clk_base * 3) / 10_000_000) + 1
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} else {
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// fast mode plus requires a clk_base > 32MHz
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assert!(clk_base >= 32_000_000);
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// sda_tx_hold_count = clk_base [cycles/s] * 120ns * (1s /
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// 1e9ns) Reduce 120/1e9 to 3/25e6 to avoid numbers that don't
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// fit in uint. Add 1 to avoid division truncation.
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((clk_base * 3) / 25_000_000) + 1
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};
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assert!(sda_tx_hold_count <= lcnt - 2);
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p.ic_fs_scl_hcnt().write(|w| w.set_ic_fs_scl_hcnt(hcnt as u16));
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p.ic_fs_scl_lcnt().write(|w| w.set_ic_fs_scl_lcnt(lcnt as u16));
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p.ic_fs_spklen()
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.write(|w| w.set_ic_fs_spklen(if lcnt < 16 { 1 } else { (lcnt / 16) as u8 }));
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p.ic_sda_hold()
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.modify(|w| w.set_ic_sda_tx_hold(sda_tx_hold_count as u16));
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// Enable I2C block
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p.ic_enable().write(|w| w.set_enable(true));
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Self { phantom: PhantomData }
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}
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fn setup(addr: u16) -> Result<(), Error> {
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if addr >= 0x80 {
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return Err(Error::AddressOutOfRange(addr));
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}
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if i2c_reserved_addr(addr) {
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return Err(Error::AddressReserved(addr));
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}
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let p = T::regs();
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p.ic_enable().write(|w| w.set_enable(false));
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p.ic_tar().write(|w| w.set_ic_tar(addr));
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p.ic_enable().write(|w| w.set_enable(true));
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Ok(())
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}
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#[inline]
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fn tx_fifo_full() -> bool {
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Self::tx_fifo_capacity() == 0
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}
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#[inline]
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fn tx_fifo_capacity() -> u8 {
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let p = T::regs();
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FIFO_SIZE - p.ic_txflr().read().txflr()
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}
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#[inline]
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fn rx_fifo_len() -> u8 {
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let p = T::regs();
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p.ic_rxflr().read().rxflr()
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}
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fn read_and_clear_abort_reason(&mut self) -> Result<(), Error> {
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let p = T::regs();
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let abort_reason = p.ic_tx_abrt_source().read();
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if abort_reason.0 != 0 {
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// Note clearing the abort flag also clears the reason, and this
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// instance of flag is clear-on-read! Note also the
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// IC_CLR_TX_ABRT register always reads as 0.
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p.ic_clr_tx_abrt().read();
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let reason = if abort_reason.abrt_7b_addr_noack()
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| abort_reason.abrt_10addr1_noack()
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| abort_reason.abrt_10addr2_noack()
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{
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AbortReason::NoAcknowledge
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} else if abort_reason.arb_lost() {
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AbortReason::ArbitrationLoss
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} else {
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AbortReason::Other(abort_reason.0)
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};
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Err(Error::Abort(reason))
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} else {
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Ok(())
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}
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}
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fn read_blocking_internal(&mut self, read: &mut [u8], restart: bool, send_stop: bool) -> Result<(), Error> {
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if read.is_empty() {
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return Err(Error::InvalidReadBufferLength);
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}
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let p = T::regs();
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let lastindex = read.len() - 1;
|
|
for (i, byte) in read.iter_mut().enumerate() {
|
|
let first = i == 0;
|
|
let last = i == lastindex;
|
|
|
|
// wait until there is space in the FIFO to write the next byte
|
|
while Self::tx_fifo_full() {}
|
|
|
|
p.ic_data_cmd().write(|w| {
|
|
w.set_restart(restart && first);
|
|
w.set_stop(send_stop && last);
|
|
|
|
w.set_cmd(true);
|
|
});
|
|
|
|
while Self::rx_fifo_len() == 0 {
|
|
self.read_and_clear_abort_reason()?;
|
|
}
|
|
|
|
*byte = p.ic_data_cmd().read().dat();
|
|
}
|
|
|
|
Ok(())
|
|
}
|
|
|
|
fn write_blocking_internal(&mut self, write: &[u8], send_stop: bool) -> Result<(), Error> {
|
|
if write.is_empty() {
|
|
return Err(Error::InvalidWriteBufferLength);
|
|
}
|
|
|
|
let p = T::regs();
|
|
|
|
for (i, byte) in write.iter().enumerate() {
|
|
let last = i == write.len() - 1;
|
|
|
|
p.ic_data_cmd().write(|w| {
|
|
w.set_stop(send_stop && last);
|
|
w.set_dat(*byte);
|
|
});
|
|
|
|
// Wait until the transmission of the address/data from the
|
|
// internal shift register has completed. For this to function
|
|
// correctly, the TX_EMPTY_CTRL flag in IC_CON must be set. The
|
|
// TX_EMPTY_CTRL flag was set in i2c_init.
|
|
while !p.ic_raw_intr_stat().read().tx_empty() {}
|
|
|
|
let abort_reason = self.read_and_clear_abort_reason();
|
|
|
|
if abort_reason.is_err() || (send_stop && last) {
|
|
// If the transaction was aborted or if it completed
|
|
// successfully wait until the STOP condition has occurred.
|
|
|
|
while !p.ic_raw_intr_stat().read().stop_det() {}
|
|
|
|
p.ic_clr_stop_det().read().clr_stop_det();
|
|
}
|
|
|
|
// Note the hardware issues a STOP automatically on an abort
|
|
// condition. Note also the hardware clears RX FIFO as well as
|
|
// TX on abort, ecause we set hwparam
|
|
// IC_AVOID_RX_FIFO_FLUSH_ON_TX_ABRT to 0.
|
|
abort_reason?;
|
|
}
|
|
Ok(())
|
|
}
|
|
|
|
// =========================
|
|
// Blocking public API
|
|
// =========================
|
|
|
|
pub fn blocking_read(&mut self, address: u8, read: &mut [u8]) -> Result<(), Error> {
|
|
Self::setup(address.into())?;
|
|
self.read_blocking_internal(read, true, true)
|
|
// Automatic Stop
|
|
}
|
|
|
|
pub fn blocking_write(&mut self, address: u8, write: &[u8]) -> Result<(), Error> {
|
|
Self::setup(address.into())?;
|
|
self.write_blocking_internal(write, true)
|
|
}
|
|
|
|
pub fn blocking_write_read(&mut self, address: u8, write: &[u8], read: &mut [u8]) -> Result<(), Error> {
|
|
Self::setup(address.into())?;
|
|
self.write_blocking_internal(write, false)?;
|
|
self.read_blocking_internal(read, true, true)
|
|
// Automatic Stop
|
|
}
|
|
}
|
|
|
|
mod eh02 {
|
|
use super::*;
|
|
|
|
impl<'d, T: Instance, M: Mode> embedded_hal_02::blocking::i2c::Read for I2c<'d, T, M> {
|
|
type Error = Error;
|
|
|
|
fn read(&mut self, address: u8, buffer: &mut [u8]) -> Result<(), Self::Error> {
|
|
self.blocking_read(address, buffer)
|
|
}
|
|
}
|
|
|
|
impl<'d, T: Instance, M: Mode> embedded_hal_02::blocking::i2c::Write for I2c<'d, T, M> {
|
|
type Error = Error;
|
|
|
|
fn write(&mut self, address: u8, bytes: &[u8]) -> Result<(), Self::Error> {
|
|
self.blocking_write(address, bytes)
|
|
}
|
|
}
|
|
|
|
impl<'d, T: Instance, M: Mode> embedded_hal_02::blocking::i2c::WriteRead for I2c<'d, T, M> {
|
|
type Error = Error;
|
|
|
|
fn write_read(&mut self, address: u8, bytes: &[u8], buffer: &mut [u8]) -> Result<(), Self::Error> {
|
|
self.blocking_write_read(address, bytes, buffer)
|
|
}
|
|
}
|
|
|
|
impl<'d, T: Instance, M: Mode> embedded_hal_02::blocking::i2c::Transactional for I2c<'d, T, M> {
|
|
type Error = Error;
|
|
|
|
fn exec(
|
|
&mut self,
|
|
address: u8,
|
|
operations: &mut [embedded_hal_02::blocking::i2c::Operation<'_>],
|
|
) -> Result<(), Self::Error> {
|
|
Self::setup(address.into())?;
|
|
for i in 0..operations.len() {
|
|
let last = i == operations.len() - 1;
|
|
match &mut operations[i] {
|
|
embedded_hal_02::blocking::i2c::Operation::Read(buf) => {
|
|
self.read_blocking_internal(buf, false, last)?
|
|
}
|
|
embedded_hal_02::blocking::i2c::Operation::Write(buf) => self.write_blocking_internal(buf, last)?,
|
|
}
|
|
}
|
|
Ok(())
|
|
}
|
|
}
|
|
}
|
|
|
|
#[cfg(feature = "unstable-traits")]
|
|
mod eh1 {
|
|
use super::*;
|
|
|
|
impl embedded_hal_1::i2c::Error for Error {
|
|
fn kind(&self) -> embedded_hal_1::i2c::ErrorKind {
|
|
match *self {
|
|
Self::Abort(AbortReason::ArbitrationLoss) => embedded_hal_1::i2c::ErrorKind::ArbitrationLoss,
|
|
Self::Abort(AbortReason::NoAcknowledge) => {
|
|
embedded_hal_1::i2c::ErrorKind::NoAcknowledge(embedded_hal_1::i2c::NoAcknowledgeSource::Address)
|
|
}
|
|
Self::Abort(AbortReason::TxNotEmpty(_)) => embedded_hal_1::i2c::ErrorKind::Other,
|
|
Self::Abort(AbortReason::Other(_)) => embedded_hal_1::i2c::ErrorKind::Other,
|
|
Self::InvalidReadBufferLength => embedded_hal_1::i2c::ErrorKind::Other,
|
|
Self::InvalidWriteBufferLength => embedded_hal_1::i2c::ErrorKind::Other,
|
|
Self::AddressOutOfRange(_) => embedded_hal_1::i2c::ErrorKind::Other,
|
|
Self::AddressReserved(_) => embedded_hal_1::i2c::ErrorKind::Other,
|
|
}
|
|
}
|
|
}
|
|
|
|
impl<'d, T: Instance, M: Mode> embedded_hal_1::i2c::ErrorType for I2c<'d, T, M> {
|
|
type Error = Error;
|
|
}
|
|
|
|
impl<'d, T: Instance, M: Mode> embedded_hal_1::i2c::I2c for I2c<'d, T, M> {
|
|
fn read(&mut self, address: u8, read: &mut [u8]) -> Result<(), Self::Error> {
|
|
self.blocking_read(address, read)
|
|
}
|
|
|
|
fn write(&mut self, address: u8, write: &[u8]) -> Result<(), Self::Error> {
|
|
self.blocking_write(address, write)
|
|
}
|
|
|
|
fn write_read(&mut self, address: u8, write: &[u8], read: &mut [u8]) -> Result<(), Self::Error> {
|
|
self.blocking_write_read(address, write, read)
|
|
}
|
|
|
|
fn transaction(
|
|
&mut self,
|
|
address: u8,
|
|
operations: &mut [embedded_hal_1::i2c::Operation<'_>],
|
|
) -> Result<(), Self::Error> {
|
|
Self::setup(address.into())?;
|
|
for i in 0..operations.len() {
|
|
let last = i == operations.len() - 1;
|
|
match &mut operations[i] {
|
|
embedded_hal_1::i2c::Operation::Read(buf) => self.read_blocking_internal(buf, false, last)?,
|
|
embedded_hal_1::i2c::Operation::Write(buf) => self.write_blocking_internal(buf, last)?,
|
|
}
|
|
}
|
|
Ok(())
|
|
}
|
|
}
|
|
}
|
|
#[cfg(all(feature = "unstable-traits", feature = "nightly"))]
|
|
mod nightly {
|
|
use embedded_hal_1::i2c::Operation;
|
|
use embedded_hal_async::i2c::AddressMode;
|
|
|
|
use super::*;
|
|
|
|
impl<'d, A, T> embedded_hal_async::i2c::I2c<A> for I2c<'d, T, Async>
|
|
where
|
|
A: AddressMode + Into<u16> + 'static,
|
|
T: Instance + 'd,
|
|
{
|
|
async fn read(&mut self, address: A, read: &mut [u8]) -> Result<(), Self::Error> {
|
|
let addr: u16 = address.into();
|
|
|
|
Self::setup(addr)?;
|
|
self.read_async_internal(read, false, true).await
|
|
}
|
|
|
|
async fn write(&mut self, address: A, write: &[u8]) -> Result<(), Self::Error> {
|
|
let addr: u16 = address.into();
|
|
|
|
Self::setup(addr)?;
|
|
self.write_async_internal(write.iter().copied(), true).await
|
|
}
|
|
|
|
async fn write_read(&mut self, address: A, write: &[u8], read: &mut [u8]) -> Result<(), Self::Error> {
|
|
let addr: u16 = address.into();
|
|
|
|
Self::setup(addr)?;
|
|
self.write_async_internal(write.iter().cloned(), false).await?;
|
|
self.read_async_internal(read, true, true).await
|
|
}
|
|
|
|
async fn transaction(&mut self, address: A, operations: &mut [Operation<'_>]) -> Result<(), Self::Error> {
|
|
let addr: u16 = address.into();
|
|
|
|
if operations.len() > 0 {
|
|
Self::setup(addr)?;
|
|
}
|
|
let mut iterator = operations.iter_mut();
|
|
|
|
while let Some(op) = iterator.next() {
|
|
let last = iterator.len() == 0;
|
|
|
|
match op {
|
|
Operation::Read(buffer) => {
|
|
self.read_async_internal(buffer, false, last).await?;
|
|
}
|
|
Operation::Write(buffer) => {
|
|
self.write_async_internal(buffer.into_iter().cloned(), last).await?;
|
|
}
|
|
}
|
|
}
|
|
Ok(())
|
|
}
|
|
}
|
|
}
|
|
|
|
pub fn i2c_reserved_addr(addr: u16) -> bool {
|
|
((addr & 0x78) == 0 || (addr & 0x78) == 0x78) && addr != 0
|
|
}
|
|
|
|
mod sealed {
|
|
use embassy_sync::waitqueue::AtomicWaker;
|
|
|
|
use crate::interrupt;
|
|
|
|
pub trait Instance {
|
|
const TX_DREQ: u8;
|
|
const RX_DREQ: u8;
|
|
|
|
type Interrupt: interrupt::typelevel::Interrupt;
|
|
|
|
fn regs() -> crate::pac::i2c::I2c;
|
|
fn reset() -> crate::pac::resets::regs::Peripherals;
|
|
fn waker() -> &'static AtomicWaker;
|
|
}
|
|
|
|
pub trait Mode {}
|
|
|
|
pub trait SdaPin<T: Instance> {}
|
|
pub trait SclPin<T: Instance> {}
|
|
}
|
|
|
|
pub trait Mode: sealed::Mode {}
|
|
|
|
macro_rules! impl_mode {
|
|
($name:ident) => {
|
|
impl sealed::Mode for $name {}
|
|
impl Mode for $name {}
|
|
};
|
|
}
|
|
|
|
pub struct Blocking;
|
|
pub struct Async;
|
|
|
|
impl_mode!(Blocking);
|
|
impl_mode!(Async);
|
|
|
|
pub trait Instance: sealed::Instance {}
|
|
|
|
macro_rules! impl_instance {
|
|
($type:ident, $irq:ident, $reset:ident, $tx_dreq:expr, $rx_dreq:expr) => {
|
|
impl sealed::Instance for peripherals::$type {
|
|
const TX_DREQ: u8 = $tx_dreq;
|
|
const RX_DREQ: u8 = $rx_dreq;
|
|
|
|
type Interrupt = crate::interrupt::typelevel::$irq;
|
|
|
|
#[inline]
|
|
fn regs() -> pac::i2c::I2c {
|
|
pac::$type
|
|
}
|
|
|
|
#[inline]
|
|
fn reset() -> pac::resets::regs::Peripherals {
|
|
let mut ret = pac::resets::regs::Peripherals::default();
|
|
ret.$reset(true);
|
|
ret
|
|
}
|
|
|
|
#[inline]
|
|
fn waker() -> &'static AtomicWaker {
|
|
static WAKER: AtomicWaker = AtomicWaker::new();
|
|
|
|
&WAKER
|
|
}
|
|
}
|
|
impl Instance for peripherals::$type {}
|
|
};
|
|
}
|
|
|
|
impl_instance!(I2C0, I2C0_IRQ, set_i2c0, 32, 33);
|
|
impl_instance!(I2C1, I2C1_IRQ, set_i2c1, 34, 35);
|
|
|
|
pub trait SdaPin<T: Instance>: sealed::SdaPin<T> + crate::gpio::Pin {}
|
|
pub trait SclPin<T: Instance>: sealed::SclPin<T> + crate::gpio::Pin {}
|
|
|
|
macro_rules! impl_pin {
|
|
($pin:ident, $instance:ident, $function:ident) => {
|
|
impl sealed::$function<peripherals::$instance> for peripherals::$pin {}
|
|
impl $function<peripherals::$instance> for peripherals::$pin {}
|
|
};
|
|
}
|
|
|
|
impl_pin!(PIN_0, I2C0, SdaPin);
|
|
impl_pin!(PIN_1, I2C0, SclPin);
|
|
impl_pin!(PIN_2, I2C1, SdaPin);
|
|
impl_pin!(PIN_3, I2C1, SclPin);
|
|
impl_pin!(PIN_4, I2C0, SdaPin);
|
|
impl_pin!(PIN_5, I2C0, SclPin);
|
|
impl_pin!(PIN_6, I2C1, SdaPin);
|
|
impl_pin!(PIN_7, I2C1, SclPin);
|
|
impl_pin!(PIN_8, I2C0, SdaPin);
|
|
impl_pin!(PIN_9, I2C0, SclPin);
|
|
impl_pin!(PIN_10, I2C1, SdaPin);
|
|
impl_pin!(PIN_11, I2C1, SclPin);
|
|
impl_pin!(PIN_12, I2C0, SdaPin);
|
|
impl_pin!(PIN_13, I2C0, SclPin);
|
|
impl_pin!(PIN_14, I2C1, SdaPin);
|
|
impl_pin!(PIN_15, I2C1, SclPin);
|
|
impl_pin!(PIN_16, I2C0, SdaPin);
|
|
impl_pin!(PIN_17, I2C0, SclPin);
|
|
impl_pin!(PIN_18, I2C1, SdaPin);
|
|
impl_pin!(PIN_19, I2C1, SclPin);
|
|
impl_pin!(PIN_20, I2C0, SdaPin);
|
|
impl_pin!(PIN_21, I2C0, SclPin);
|
|
impl_pin!(PIN_22, I2C1, SdaPin);
|
|
impl_pin!(PIN_23, I2C1, SclPin);
|
|
impl_pin!(PIN_24, I2C0, SdaPin);
|
|
impl_pin!(PIN_25, I2C0, SclPin);
|
|
impl_pin!(PIN_26, I2C1, SdaPin);
|
|
impl_pin!(PIN_27, I2C1, SclPin);
|
|
impl_pin!(PIN_28, I2C0, SdaPin);
|
|
impl_pin!(PIN_29, I2C0, SclPin);
|