785 lines
24 KiB
Rust
785 lines
24 KiB
Rust
use core::future::{poll_fn, Future};
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use core::slice;
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use core::task::Poll;
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use atomic_polyfill::{AtomicU8, Ordering};
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use embassy_hal_internal::atomic_ring_buffer::RingBuffer;
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use embassy_sync::waitqueue::AtomicWaker;
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use embassy_time::Timer;
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use super::*;
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use crate::clocks::clk_peri_freq;
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use crate::interrupt::typelevel::{Binding, Interrupt};
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use crate::{interrupt, RegExt};
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pub struct State {
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tx_waker: AtomicWaker,
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tx_buf: RingBuffer,
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rx_waker: AtomicWaker,
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rx_buf: RingBuffer,
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rx_error: AtomicU8,
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}
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// these must match bits 8..11 in UARTDR
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const RXE_OVERRUN: u8 = 8;
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const RXE_BREAK: u8 = 4;
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const RXE_PARITY: u8 = 2;
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const RXE_FRAMING: u8 = 1;
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impl State {
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pub const fn new() -> Self {
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Self {
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rx_buf: RingBuffer::new(),
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tx_buf: RingBuffer::new(),
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rx_waker: AtomicWaker::new(),
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tx_waker: AtomicWaker::new(),
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rx_error: AtomicU8::new(0),
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}
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}
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}
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pub struct BufferedUart<'d, T: Instance> {
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pub(crate) rx: BufferedUartRx<'d, T>,
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pub(crate) tx: BufferedUartTx<'d, T>,
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}
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pub struct BufferedUartRx<'d, T: Instance> {
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pub(crate) phantom: PhantomData<&'d mut T>,
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}
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pub struct BufferedUartTx<'d, T: Instance> {
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pub(crate) phantom: PhantomData<&'d mut T>,
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}
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pub(crate) fn init_buffers<'d, T: Instance + 'd>(
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_irq: impl Binding<T::Interrupt, BufferedInterruptHandler<T>>,
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tx_buffer: &'d mut [u8],
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rx_buffer: &'d mut [u8],
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) {
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let state = T::buffered_state();
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let len = tx_buffer.len();
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unsafe { state.tx_buf.init(tx_buffer.as_mut_ptr(), len) };
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let len = rx_buffer.len();
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unsafe { state.rx_buf.init(rx_buffer.as_mut_ptr(), len) };
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// From the datasheet:
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// "The transmit interrupt is based on a transition through a level, rather
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// than on the level itself. When the interrupt and the UART is enabled
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// before any data is written to the transmit FIFO the interrupt is not set.
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// The interrupt is only set, after written data leaves the single location
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// of the transmit FIFO and it becomes empty."
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//
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// This means we can leave the interrupt enabled the whole time as long as
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// we clear it after it happens. The downside is that the we manually have
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// to pend the ISR when we want data transmission to start.
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let regs = T::regs();
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regs.uartimsc().write(|w| {
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w.set_rxim(true);
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w.set_rtim(true);
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w.set_txim(true);
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});
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T::Interrupt::unpend();
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unsafe { T::Interrupt::enable() };
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}
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impl<'d, T: Instance> BufferedUart<'d, T> {
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pub fn new(
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_uart: impl Peripheral<P = T> + 'd,
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irq: impl Binding<T::Interrupt, BufferedInterruptHandler<T>>,
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tx: impl Peripheral<P = impl TxPin<T>> + 'd,
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rx: impl Peripheral<P = impl RxPin<T>> + 'd,
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tx_buffer: &'d mut [u8],
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rx_buffer: &'d mut [u8],
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config: Config,
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) -> Self {
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into_ref!(tx, rx);
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super::Uart::<'d, T, Async>::init(Some(tx.map_into()), Some(rx.map_into()), None, None, config);
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init_buffers::<T>(irq, tx_buffer, rx_buffer);
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Self {
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rx: BufferedUartRx { phantom: PhantomData },
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tx: BufferedUartTx { phantom: PhantomData },
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}
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}
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pub fn new_with_rtscts(
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_uart: impl Peripheral<P = T> + 'd,
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irq: impl Binding<T::Interrupt, BufferedInterruptHandler<T>>,
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tx: impl Peripheral<P = impl TxPin<T>> + 'd,
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rx: impl Peripheral<P = impl RxPin<T>> + 'd,
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rts: impl Peripheral<P = impl RtsPin<T>> + 'd,
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cts: impl Peripheral<P = impl CtsPin<T>> + 'd,
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tx_buffer: &'d mut [u8],
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rx_buffer: &'d mut [u8],
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config: Config,
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) -> Self {
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into_ref!(tx, rx, cts, rts);
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super::Uart::<'d, T, Async>::init(
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Some(tx.map_into()),
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Some(rx.map_into()),
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Some(rts.map_into()),
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Some(cts.map_into()),
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config,
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);
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init_buffers::<T>(irq, tx_buffer, rx_buffer);
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Self {
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rx: BufferedUartRx { phantom: PhantomData },
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tx: BufferedUartTx { phantom: PhantomData },
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}
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}
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pub fn blocking_write(&mut self, buffer: &[u8]) -> Result<usize, Error> {
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self.tx.blocking_write(buffer)
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}
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pub fn blocking_flush(&mut self) -> Result<(), Error> {
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self.tx.blocking_flush()
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}
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pub fn blocking_read(&mut self, buffer: &mut [u8]) -> Result<usize, Error> {
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self.rx.blocking_read(buffer)
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}
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pub fn busy(&self) -> bool {
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self.tx.busy()
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}
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pub async fn send_break(&mut self, bits: u32) {
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self.tx.send_break(bits).await
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}
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pub fn split(self) -> (BufferedUartRx<'d, T>, BufferedUartTx<'d, T>) {
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(self.rx, self.tx)
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}
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}
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impl<'d, T: Instance> BufferedUartRx<'d, T> {
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pub fn new(
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_uart: impl Peripheral<P = T> + 'd,
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irq: impl Binding<T::Interrupt, BufferedInterruptHandler<T>>,
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rx: impl Peripheral<P = impl RxPin<T>> + 'd,
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rx_buffer: &'d mut [u8],
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config: Config,
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) -> Self {
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into_ref!(rx);
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super::Uart::<'d, T, Async>::init(None, Some(rx.map_into()), None, None, config);
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init_buffers::<T>(irq, &mut [], rx_buffer);
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Self { phantom: PhantomData }
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}
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pub fn new_with_rts(
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_uart: impl Peripheral<P = T> + 'd,
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irq: impl Binding<T::Interrupt, BufferedInterruptHandler<T>>,
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rx: impl Peripheral<P = impl RxPin<T>> + 'd,
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rts: impl Peripheral<P = impl RtsPin<T>> + 'd,
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rx_buffer: &'d mut [u8],
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config: Config,
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) -> Self {
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into_ref!(rx, rts);
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super::Uart::<'d, T, Async>::init(None, Some(rx.map_into()), Some(rts.map_into()), None, config);
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init_buffers::<T>(irq, &mut [], rx_buffer);
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Self { phantom: PhantomData }
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}
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fn read<'a>(buf: &'a mut [u8]) -> impl Future<Output = Result<usize, Error>> + 'a
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where
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T: 'd,
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{
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poll_fn(move |cx| {
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if let Poll::Ready(r) = Self::try_read(buf) {
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return Poll::Ready(r);
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}
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T::buffered_state().rx_waker.register(cx.waker());
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Poll::Pending
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})
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}
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fn get_rx_error() -> Option<Error> {
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let errs = T::buffered_state().rx_error.swap(0, Ordering::Relaxed);
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if errs & RXE_OVERRUN != 0 {
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Some(Error::Overrun)
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} else if errs & RXE_BREAK != 0 {
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Some(Error::Break)
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} else if errs & RXE_PARITY != 0 {
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Some(Error::Parity)
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} else if errs & RXE_FRAMING != 0 {
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Some(Error::Framing)
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} else {
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None
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}
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}
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fn try_read(buf: &mut [u8]) -> Poll<Result<usize, Error>>
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where
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T: 'd,
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{
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if buf.is_empty() {
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return Poll::Ready(Ok(0));
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}
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let state = T::buffered_state();
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let mut rx_reader = unsafe { state.rx_buf.reader() };
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let n = rx_reader.pop(|data| {
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let n = data.len().min(buf.len());
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buf[..n].copy_from_slice(&data[..n]);
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n
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});
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let result = if n == 0 {
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match Self::get_rx_error() {
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None => return Poll::Pending,
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Some(e) => Err(e),
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}
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} else {
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Ok(n)
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};
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// (Re-)Enable the interrupt to receive more data in case it was
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// disabled because the buffer was full or errors were detected.
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let regs = T::regs();
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regs.uartimsc().write_set(|w| {
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w.set_rxim(true);
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w.set_rtim(true);
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});
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Poll::Ready(result)
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}
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pub fn blocking_read(&mut self, buf: &mut [u8]) -> Result<usize, Error> {
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loop {
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match Self::try_read(buf) {
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Poll::Ready(res) => return res,
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Poll::Pending => continue,
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}
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}
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}
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fn fill_buf<'a>() -> impl Future<Output = Result<&'a [u8], Error>>
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where
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T: 'd,
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{
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poll_fn(move |cx| {
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let state = T::buffered_state();
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let mut rx_reader = unsafe { state.rx_buf.reader() };
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let (p, n) = rx_reader.pop_buf();
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let result = if n == 0 {
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match Self::get_rx_error() {
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None => {
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state.rx_waker.register(cx.waker());
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return Poll::Pending;
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}
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Some(e) => Err(e),
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}
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} else {
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let buf = unsafe { slice::from_raw_parts(p, n) };
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Ok(buf)
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};
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Poll::Ready(result)
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})
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}
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fn consume(amt: usize) {
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let state = T::buffered_state();
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let mut rx_reader = unsafe { state.rx_buf.reader() };
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rx_reader.pop_done(amt);
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// (Re-)Enable the interrupt to receive more data in case it was
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// disabled because the buffer was full or errors were detected.
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let regs = T::regs();
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regs.uartimsc().write_set(|w| {
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w.set_rxim(true);
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w.set_rtim(true);
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});
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}
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}
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impl<'d, T: Instance> BufferedUartTx<'d, T> {
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pub fn new(
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_uart: impl Peripheral<P = T> + 'd,
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irq: impl Binding<T::Interrupt, BufferedInterruptHandler<T>>,
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tx: impl Peripheral<P = impl TxPin<T>> + 'd,
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tx_buffer: &'d mut [u8],
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config: Config,
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) -> Self {
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into_ref!(tx);
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super::Uart::<'d, T, Async>::init(Some(tx.map_into()), None, None, None, config);
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init_buffers::<T>(irq, tx_buffer, &mut []);
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Self { phantom: PhantomData }
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}
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pub fn new_with_cts(
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_uart: impl Peripheral<P = T> + 'd,
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irq: impl Binding<T::Interrupt, BufferedInterruptHandler<T>>,
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tx: impl Peripheral<P = impl TxPin<T>> + 'd,
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cts: impl Peripheral<P = impl CtsPin<T>> + 'd,
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tx_buffer: &'d mut [u8],
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config: Config,
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) -> Self {
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into_ref!(tx, cts);
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super::Uart::<'d, T, Async>::init(Some(tx.map_into()), None, None, Some(cts.map_into()), config);
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init_buffers::<T>(irq, tx_buffer, &mut []);
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Self { phantom: PhantomData }
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}
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fn write<'a>(buf: &'a [u8]) -> impl Future<Output = Result<usize, Error>> + 'a {
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poll_fn(move |cx| {
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if buf.is_empty() {
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return Poll::Ready(Ok(0));
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}
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let state = T::buffered_state();
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let mut tx_writer = unsafe { state.tx_buf.writer() };
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let n = tx_writer.push(|data| {
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let n = data.len().min(buf.len());
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data[..n].copy_from_slice(&buf[..n]);
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n
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});
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if n == 0 {
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state.tx_waker.register(cx.waker());
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return Poll::Pending;
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}
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// The TX interrupt only triggers when the there was data in the
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// FIFO and the number of bytes drops below a threshold. When the
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// FIFO was empty we have to manually pend the interrupt to shovel
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// TX data from the buffer into the FIFO.
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T::Interrupt::pend();
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Poll::Ready(Ok(n))
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})
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}
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fn flush() -> impl Future<Output = Result<(), Error>> {
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poll_fn(move |cx| {
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let state = T::buffered_state();
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if !state.tx_buf.is_empty() {
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state.tx_waker.register(cx.waker());
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return Poll::Pending;
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}
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Poll::Ready(Ok(()))
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})
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}
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pub fn blocking_write(&mut self, buf: &[u8]) -> Result<usize, Error> {
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if buf.is_empty() {
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return Ok(0);
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}
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loop {
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let state = T::buffered_state();
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let mut tx_writer = unsafe { state.tx_buf.writer() };
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let n = tx_writer.push(|data| {
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let n = data.len().min(buf.len());
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data[..n].copy_from_slice(&buf[..n]);
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n
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});
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if n != 0 {
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// The TX interrupt only triggers when the there was data in the
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// FIFO and the number of bytes drops below a threshold. When the
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// FIFO was empty we have to manually pend the interrupt to shovel
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// TX data from the buffer into the FIFO.
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T::Interrupt::pend();
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return Ok(n);
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}
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}
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}
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pub fn blocking_flush(&mut self) -> Result<(), Error> {
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loop {
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let state = T::buffered_state();
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if state.tx_buf.is_empty() {
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return Ok(());
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}
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}
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}
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pub fn busy(&self) -> bool {
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T::regs().uartfr().read().busy()
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}
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/// Assert a break condition after waiting for the transmit buffers to empty,
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/// for the specified number of bit times. This condition must be asserted
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/// for at least two frame times to be effective, `bits` will adjusted
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/// according to frame size, parity, and stop bit settings to ensure this.
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///
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/// This method may block for a long amount of time since it has to wait
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/// for the transmit fifo to empty, which may take a while on slow links.
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pub async fn send_break(&mut self, bits: u32) {
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let regs = T::regs();
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let bits = bits.max({
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let lcr = regs.uartlcr_h().read();
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let width = lcr.wlen() as u32 + 5;
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let parity = lcr.pen() as u32;
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let stops = 1 + lcr.stp2() as u32;
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2 * (1 + width + parity + stops)
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});
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let divx64 = (((regs.uartibrd().read().baud_divint() as u32) << 6)
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+ regs.uartfbrd().read().baud_divfrac() as u32) as u64;
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let div_clk = clk_peri_freq() as u64 * 64;
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let wait_usecs = (1_000_000 * bits as u64 * divx64 * 16 + div_clk - 1) / div_clk;
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Self::flush().await.unwrap();
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while self.busy() {}
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regs.uartlcr_h().write_set(|w| w.set_brk(true));
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Timer::after_micros(wait_usecs).await;
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regs.uartlcr_h().write_clear(|w| w.set_brk(true));
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}
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}
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impl<'d, T: Instance> Drop for BufferedUartRx<'d, T> {
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fn drop(&mut self) {
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let state = T::buffered_state();
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unsafe { state.rx_buf.deinit() }
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// TX is inactive if the the buffer is not available.
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// We can now unregister the interrupt handler
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if state.tx_buf.len() == 0 {
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T::Interrupt::disable();
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}
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}
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}
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impl<'d, T: Instance> Drop for BufferedUartTx<'d, T> {
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fn drop(&mut self) {
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let state = T::buffered_state();
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unsafe { state.tx_buf.deinit() }
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// RX is inactive if the the buffer is not available.
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// We can now unregister the interrupt handler
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if state.rx_buf.len() == 0 {
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T::Interrupt::disable();
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}
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}
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}
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pub struct BufferedInterruptHandler<T: Instance> {
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_uart: PhantomData<T>,
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}
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impl<T: Instance> interrupt::typelevel::Handler<T::Interrupt> for BufferedInterruptHandler<T> {
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unsafe fn on_interrupt() {
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let r = T::regs();
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if r.uartdmacr().read().rxdmae() {
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return;
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}
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let s = T::buffered_state();
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// Clear TX and error interrupt flags
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// RX interrupt flags are cleared by reading from the FIFO.
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let ris = r.uartris().read();
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r.uarticr().write(|w| {
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w.set_txic(ris.txris());
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w.set_feic(ris.feris());
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w.set_peic(ris.peris());
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w.set_beic(ris.beris());
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w.set_oeic(ris.oeris());
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});
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// Errors
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if ris.feris() {
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warn!("Framing error");
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}
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if ris.peris() {
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warn!("Parity error");
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}
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if ris.beris() {
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warn!("Break error");
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}
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if ris.oeris() {
|
|
warn!("Overrun error");
|
|
}
|
|
|
|
// RX
|
|
let mut rx_writer = unsafe { s.rx_buf.writer() };
|
|
let rx_buf = rx_writer.push_slice();
|
|
let mut n_read = 0;
|
|
let mut error = false;
|
|
for rx_byte in rx_buf {
|
|
if r.uartfr().read().rxfe() {
|
|
break;
|
|
}
|
|
let dr = r.uartdr().read();
|
|
if (dr.0 >> 8) != 0 {
|
|
s.rx_error.fetch_or((dr.0 >> 8) as u8, Ordering::Relaxed);
|
|
error = true;
|
|
// only fill the buffer with valid characters. the current character is fine
|
|
// if the error is an overrun, but if we add it to the buffer we'll report
|
|
// the overrun one character too late. drop it instead and pretend we were
|
|
// a bit slower at draining the rx fifo than we actually were.
|
|
// this is consistent with blocking uart error reporting.
|
|
break;
|
|
}
|
|
*rx_byte = dr.data();
|
|
n_read += 1;
|
|
}
|
|
if n_read > 0 {
|
|
rx_writer.push_done(n_read);
|
|
s.rx_waker.wake();
|
|
} else if error {
|
|
s.rx_waker.wake();
|
|
}
|
|
// Disable any further RX interrupts when the buffer becomes full or
|
|
// errors have occurred. This lets us buffer additional errors in the
|
|
// fifo without needing more error storage locations, and most applications
|
|
// will want to do a full reset of their uart state anyway once an error
|
|
// has happened.
|
|
if s.rx_buf.is_full() || error {
|
|
r.uartimsc().write_clear(|w| {
|
|
w.set_rxim(true);
|
|
w.set_rtim(true);
|
|
});
|
|
}
|
|
|
|
// TX
|
|
let mut tx_reader = unsafe { s.tx_buf.reader() };
|
|
let tx_buf = tx_reader.pop_slice();
|
|
let mut n_written = 0;
|
|
for tx_byte in tx_buf.iter_mut() {
|
|
if r.uartfr().read().txff() {
|
|
break;
|
|
}
|
|
r.uartdr().write(|w| w.set_data(*tx_byte));
|
|
n_written += 1;
|
|
}
|
|
if n_written > 0 {
|
|
tx_reader.pop_done(n_written);
|
|
s.tx_waker.wake();
|
|
}
|
|
// The TX interrupt only triggers once when the FIFO threshold is
|
|
// crossed. No need to disable it when the buffer becomes empty
|
|
// as it does re-trigger anymore once we have cleared it.
|
|
}
|
|
}
|
|
|
|
impl embedded_io::Error for Error {
|
|
fn kind(&self) -> embedded_io::ErrorKind {
|
|
embedded_io::ErrorKind::Other
|
|
}
|
|
}
|
|
|
|
impl<'d, T: Instance> embedded_io_async::ErrorType for BufferedUart<'d, T> {
|
|
type Error = Error;
|
|
}
|
|
|
|
impl<'d, T: Instance> embedded_io_async::ErrorType for BufferedUartRx<'d, T> {
|
|
type Error = Error;
|
|
}
|
|
|
|
impl<'d, T: Instance> embedded_io_async::ErrorType for BufferedUartTx<'d, T> {
|
|
type Error = Error;
|
|
}
|
|
|
|
impl<'d, T: Instance + 'd> embedded_io_async::Read for BufferedUart<'d, T> {
|
|
async fn read(&mut self, buf: &mut [u8]) -> Result<usize, Self::Error> {
|
|
BufferedUartRx::<'d, T>::read(buf).await
|
|
}
|
|
}
|
|
|
|
impl<'d, T: Instance + 'd> embedded_io_async::Read for BufferedUartRx<'d, T> {
|
|
async fn read(&mut self, buf: &mut [u8]) -> Result<usize, Self::Error> {
|
|
Self::read(buf).await
|
|
}
|
|
}
|
|
|
|
impl<'d, T: Instance + 'd> embedded_io_async::BufRead for BufferedUart<'d, T> {
|
|
async fn fill_buf(&mut self) -> Result<&[u8], Self::Error> {
|
|
BufferedUartRx::<'d, T>::fill_buf().await
|
|
}
|
|
|
|
fn consume(&mut self, amt: usize) {
|
|
BufferedUartRx::<'d, T>::consume(amt)
|
|
}
|
|
}
|
|
|
|
impl<'d, T: Instance + 'd> embedded_io_async::BufRead for BufferedUartRx<'d, T> {
|
|
async fn fill_buf(&mut self) -> Result<&[u8], Self::Error> {
|
|
Self::fill_buf().await
|
|
}
|
|
|
|
fn consume(&mut self, amt: usize) {
|
|
Self::consume(amt)
|
|
}
|
|
}
|
|
|
|
impl<'d, T: Instance + 'd> embedded_io_async::Write for BufferedUart<'d, T> {
|
|
async fn write(&mut self, buf: &[u8]) -> Result<usize, Self::Error> {
|
|
BufferedUartTx::<'d, T>::write(buf).await
|
|
}
|
|
|
|
async fn flush(&mut self) -> Result<(), Self::Error> {
|
|
BufferedUartTx::<'d, T>::flush().await
|
|
}
|
|
}
|
|
|
|
impl<'d, T: Instance + 'd> embedded_io_async::Write for BufferedUartTx<'d, T> {
|
|
async fn write(&mut self, buf: &[u8]) -> Result<usize, Self::Error> {
|
|
Self::write(buf).await
|
|
}
|
|
|
|
async fn flush(&mut self) -> Result<(), Self::Error> {
|
|
Self::flush().await
|
|
}
|
|
}
|
|
|
|
impl<'d, T: Instance + 'd> embedded_io::Read for BufferedUart<'d, T> {
|
|
fn read(&mut self, buf: &mut [u8]) -> Result<usize, Self::Error> {
|
|
self.rx.blocking_read(buf)
|
|
}
|
|
}
|
|
|
|
impl<'d, T: Instance + 'd> embedded_io::Read for BufferedUartRx<'d, T> {
|
|
fn read(&mut self, buf: &mut [u8]) -> Result<usize, Self::Error> {
|
|
self.blocking_read(buf)
|
|
}
|
|
}
|
|
|
|
impl<'d, T: Instance + 'd> embedded_io::Write for BufferedUart<'d, T> {
|
|
fn write(&mut self, buf: &[u8]) -> Result<usize, Self::Error> {
|
|
self.tx.blocking_write(buf)
|
|
}
|
|
|
|
fn flush(&mut self) -> Result<(), Self::Error> {
|
|
self.tx.blocking_flush()
|
|
}
|
|
}
|
|
|
|
impl<'d, T: Instance + 'd> embedded_io::Write for BufferedUartTx<'d, T> {
|
|
fn write(&mut self, buf: &[u8]) -> Result<usize, Self::Error> {
|
|
self.blocking_write(buf)
|
|
}
|
|
|
|
fn flush(&mut self) -> Result<(), Self::Error> {
|
|
self.blocking_flush()
|
|
}
|
|
}
|
|
|
|
impl<'d, T: Instance> embedded_hal_02::serial::Read<u8> for BufferedUartRx<'d, T> {
|
|
type Error = Error;
|
|
|
|
fn read(&mut self) -> Result<u8, nb::Error<Self::Error>> {
|
|
let r = T::regs();
|
|
if r.uartfr().read().rxfe() {
|
|
return Err(nb::Error::WouldBlock);
|
|
}
|
|
|
|
let dr = r.uartdr().read();
|
|
|
|
if dr.oe() {
|
|
Err(nb::Error::Other(Error::Overrun))
|
|
} else if dr.be() {
|
|
Err(nb::Error::Other(Error::Break))
|
|
} else if dr.pe() {
|
|
Err(nb::Error::Other(Error::Parity))
|
|
} else if dr.fe() {
|
|
Err(nb::Error::Other(Error::Framing))
|
|
} else {
|
|
Ok(dr.data())
|
|
}
|
|
}
|
|
}
|
|
|
|
impl<'d, T: Instance> embedded_hal_02::blocking::serial::Write<u8> for BufferedUartTx<'d, T> {
|
|
type Error = Error;
|
|
|
|
fn bwrite_all(&mut self, mut buffer: &[u8]) -> Result<(), Self::Error> {
|
|
while !buffer.is_empty() {
|
|
match self.blocking_write(buffer) {
|
|
Ok(0) => panic!("zero-length write."),
|
|
Ok(n) => buffer = &buffer[n..],
|
|
Err(e) => return Err(e),
|
|
}
|
|
}
|
|
Ok(())
|
|
}
|
|
|
|
fn bflush(&mut self) -> Result<(), Self::Error> {
|
|
self.blocking_flush()
|
|
}
|
|
}
|
|
|
|
impl<'d, T: Instance> embedded_hal_02::serial::Read<u8> for BufferedUart<'d, T> {
|
|
type Error = Error;
|
|
|
|
fn read(&mut self) -> Result<u8, nb::Error<Self::Error>> {
|
|
embedded_hal_02::serial::Read::read(&mut self.rx)
|
|
}
|
|
}
|
|
|
|
impl<'d, T: Instance> embedded_hal_02::blocking::serial::Write<u8> for BufferedUart<'d, T> {
|
|
type Error = Error;
|
|
|
|
fn bwrite_all(&mut self, mut buffer: &[u8]) -> Result<(), Self::Error> {
|
|
while !buffer.is_empty() {
|
|
match self.blocking_write(buffer) {
|
|
Ok(0) => panic!("zero-length write."),
|
|
Ok(n) => buffer = &buffer[n..],
|
|
Err(e) => return Err(e),
|
|
}
|
|
}
|
|
Ok(())
|
|
}
|
|
|
|
fn bflush(&mut self) -> Result<(), Self::Error> {
|
|
self.blocking_flush()
|
|
}
|
|
}
|
|
|
|
impl<'d, T: Instance> embedded_hal_nb::serial::ErrorType for BufferedUartRx<'d, T> {
|
|
type Error = Error;
|
|
}
|
|
|
|
impl<'d, T: Instance> embedded_hal_nb::serial::ErrorType for BufferedUartTx<'d, T> {
|
|
type Error = Error;
|
|
}
|
|
|
|
impl<'d, T: Instance> embedded_hal_nb::serial::ErrorType for BufferedUart<'d, T> {
|
|
type Error = Error;
|
|
}
|
|
|
|
impl<'d, T: Instance> embedded_hal_nb::serial::Read for BufferedUartRx<'d, T> {
|
|
fn read(&mut self) -> nb::Result<u8, Self::Error> {
|
|
embedded_hal_02::serial::Read::read(self)
|
|
}
|
|
}
|
|
|
|
impl<'d, T: Instance> embedded_hal_nb::serial::Write for BufferedUartTx<'d, T> {
|
|
fn write(&mut self, char: u8) -> nb::Result<(), Self::Error> {
|
|
self.blocking_write(&[char]).map(drop).map_err(nb::Error::Other)
|
|
}
|
|
|
|
fn flush(&mut self) -> nb::Result<(), Self::Error> {
|
|
self.blocking_flush().map_err(nb::Error::Other)
|
|
}
|
|
}
|
|
|
|
impl<'d, T: Instance> embedded_hal_nb::serial::Read for BufferedUart<'d, T> {
|
|
fn read(&mut self) -> Result<u8, nb::Error<Self::Error>> {
|
|
embedded_hal_02::serial::Read::read(&mut self.rx)
|
|
}
|
|
}
|
|
|
|
impl<'d, T: Instance> embedded_hal_nb::serial::Write for BufferedUart<'d, T> {
|
|
fn write(&mut self, char: u8) -> nb::Result<(), Self::Error> {
|
|
self.blocking_write(&[char]).map(drop).map_err(nb::Error::Other)
|
|
}
|
|
|
|
fn flush(&mut self) -> nb::Result<(), Self::Error> {
|
|
self.blocking_flush().map_err(nb::Error::Other)
|
|
}
|
|
}
|