c501b162fc
Modify init function to return a Clock instance defined by a per-chip SystemClock type and use this in macro setup A proof of concept implementation for STM32 L0 chips. This allows using embassy::main macros for STM32 devices that have the clock setup logic.
534 lines
18 KiB
Rust
534 lines
18 KiB
Rust
use core::marker::PhantomData;
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use embassy::util::Unborrow;
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use crate::fmt::{assert, panic};
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use crate::pac::peripherals;
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use crate::pac::rcc::vals::Timpre;
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use crate::pac::{DBGMCU, RCC, SYSCFG};
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use crate::pwr::{Power, VoltageScale};
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use crate::time::Hertz;
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mod pll;
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use pll::pll_setup;
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pub use pll::PllConfig;
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const HSI: Hertz = Hertz(64_000_000);
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const CSI: Hertz = Hertz(4_000_000);
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const HSI48: Hertz = Hertz(48_000_000);
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const LSI: Hertz = Hertz(32_000);
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/// Core clock frequencies
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#[derive(Clone, Copy)]
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pub struct CoreClocks {
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pub hclk: Hertz,
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pub pclk1: Hertz,
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pub pclk2: Hertz,
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pub pclk3: Hertz,
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pub pclk4: Hertz,
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pub ppre1: u8,
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pub ppre2: u8,
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pub ppre3: u8,
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pub ppre4: u8,
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pub csi_ck: Option<Hertz>,
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pub hsi_ck: Option<Hertz>,
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pub hsi48_ck: Option<Hertz>,
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pub lsi_ck: Option<Hertz>,
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pub per_ck: Option<Hertz>,
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pub hse_ck: Option<Hertz>,
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pub pll1_p_ck: Option<Hertz>,
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pub pll1_q_ck: Option<Hertz>,
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pub pll1_r_ck: Option<Hertz>,
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pub pll2_p_ck: Option<Hertz>,
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pub pll2_q_ck: Option<Hertz>,
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pub pll2_r_ck: Option<Hertz>,
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pub pll3_p_ck: Option<Hertz>,
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pub pll3_q_ck: Option<Hertz>,
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pub pll3_r_ck: Option<Hertz>,
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pub timx_ker_ck: Option<Hertz>,
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pub timy_ker_ck: Option<Hertz>,
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pub sys_ck: Hertz,
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pub c_ck: Hertz,
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}
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/// Configuration of the core clocks
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#[non_exhaustive]
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#[derive(Default)]
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pub struct Config {
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pub hse: Option<Hertz>,
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pub bypass_hse: bool,
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pub sys_ck: Option<Hertz>,
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pub per_ck: Option<Hertz>,
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rcc_hclk: Option<Hertz>,
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pub hclk: Option<Hertz>,
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pub pclk1: Option<Hertz>,
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pub pclk2: Option<Hertz>,
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pub pclk3: Option<Hertz>,
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pub pclk4: Option<Hertz>,
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pub pll1: PllConfig,
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pub pll2: PllConfig,
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pub pll3: PllConfig,
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}
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pub struct Rcc<'d> {
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inner: PhantomData<&'d ()>,
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config: Config,
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}
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impl<'d> Rcc<'d> {
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pub fn new(_rcc: impl Unborrow<Target = peripherals::RCC> + 'd, config: Config) -> Self {
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Self {
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inner: PhantomData,
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config,
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}
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}
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/// Freeze the core clocks, returning a Core Clocks Distribution
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/// and Reset (CCDR) structure. The actual frequency of the clocks
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/// configured is returned in the `clocks` member of the CCDR
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/// structure.
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///
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/// Note that `freeze` will never result in a clock _faster_ than
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/// that specified. It may result in a clock that is a factor of [1,
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/// 2) slower.
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///
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/// `syscfg` is required to enable the I/O compensation cell.
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///
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/// # Panics
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///
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/// If a clock specification cannot be achieved within the
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/// hardware specification then this function will panic. This
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/// function may also panic if a clock specification can be
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/// achieved, but the mechanism for doing so is not yet
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/// implemented here.
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pub fn freeze(mut self, pwr: &Power) -> CoreClocks {
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use crate::pac::rcc::vals::{
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Apb4enrSyscfgen, Ckpersel, D1ppre, D2ppre1, D3ppre, Hpre, Hsebyp, Hsidiv, Hsion, Lsion,
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Pllsrc, Sw,
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};
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let srcclk = self.config.hse.unwrap_or(HSI); // Available clocks
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let (sys_ck, sys_use_pll1_p) = self.sys_ck_setup(srcclk);
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// Configure traceclk from PLL if needed
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self.traceclk_setup(sys_use_pll1_p);
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// NOTE(unsafe) We have exclusive access to the RCC
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let (pll1_p_ck, pll1_q_ck, pll1_r_ck) =
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unsafe { pll_setup(srcclk.0, &self.config.pll1, 0) };
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let (pll2_p_ck, pll2_q_ck, pll2_r_ck) =
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unsafe { pll_setup(srcclk.0, &self.config.pll2, 1) };
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let (pll3_p_ck, pll3_q_ck, pll3_r_ck) =
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unsafe { pll_setup(srcclk.0, &self.config.pll3, 2) };
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let sys_ck = if sys_use_pll1_p {
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Hertz(pll1_p_ck.unwrap()) // Must have been set by sys_ck_setup
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} else {
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sys_ck
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};
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// NOTE(unsafe) We own the regblock
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unsafe {
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// This routine does not support HSIDIV != 1. To
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// do so it would need to ensure all PLLxON bits are clear
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// before changing the value of HSIDIV
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let cr = RCC.cr().read();
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assert!(cr.hsion() == Hsion::ON);
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assert!(cr.hsidiv() == Hsidiv::DIV1);
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RCC.csr().modify(|w| w.set_lsion(Lsion::ON));
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while !RCC.csr().read().lsirdy() {}
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}
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// per_ck from HSI by default
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let (per_ck, ckpersel) = match (self.config.per_ck == self.config.hse, self.config.per_ck) {
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(true, Some(hse)) => (hse, Ckpersel::HSE), // HSE
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(_, Some(CSI)) => (CSI, Ckpersel::CSI), // CSI
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_ => (HSI, Ckpersel::HSI), // HSI
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};
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// D1 Core Prescaler
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// Set to 1
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let d1cpre_bits = 0;
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let d1cpre_div = 1;
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let sys_d1cpre_ck = sys_ck.0 / d1cpre_div;
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// Refer to part datasheet "General operating conditions"
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// table for (rev V). We do not assert checks for earlier
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// revisions which may have lower limits.
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let (sys_d1cpre_ck_max, rcc_hclk_max, pclk_max) = match pwr.vos {
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VoltageScale::Scale0 => (480_000_000, 240_000_000, 120_000_000),
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VoltageScale::Scale1 => (400_000_000, 200_000_000, 100_000_000),
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VoltageScale::Scale2 => (300_000_000, 150_000_000, 75_000_000),
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_ => (200_000_000, 100_000_000, 50_000_000),
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};
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assert!(sys_d1cpre_ck <= sys_d1cpre_ck_max);
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let rcc_hclk = self
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.config
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.rcc_hclk
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.map(|v| v.0)
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.unwrap_or(sys_d1cpre_ck / 2);
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assert!(rcc_hclk <= rcc_hclk_max);
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// Estimate divisor
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let (hpre_bits, hpre_div) = match (sys_d1cpre_ck + rcc_hclk - 1) / rcc_hclk {
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0 => panic!(),
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1 => (Hpre::DIV1, 1),
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2 => (Hpre::DIV2, 2),
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3..=5 => (Hpre::DIV4, 4),
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6..=11 => (Hpre::DIV8, 8),
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12..=39 => (Hpre::DIV16, 16),
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40..=95 => (Hpre::DIV64, 64),
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96..=191 => (Hpre::DIV128, 128),
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192..=383 => (Hpre::DIV256, 256),
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_ => (Hpre::DIV512, 512),
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};
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// Calculate real AXI and AHB clock
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let rcc_hclk = sys_d1cpre_ck / hpre_div;
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assert!(rcc_hclk <= rcc_hclk_max);
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let rcc_aclk = rcc_hclk; // AXI clock is always equal to AHB clock on H7
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// Timer prescaler selection
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let timpre = Timpre::DEFAULTX2;
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let requested_pclk1 = self
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.config
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.pclk1
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.map(|v| v.0)
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.unwrap_or_else(|| pclk_max.min(rcc_hclk / 2));
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let (rcc_pclk1, ppre1_bits, ppre1, rcc_timerx_ker_ck) =
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Self::ppre_calculate(requested_pclk1, rcc_hclk, pclk_max, Some(timpre));
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let requested_pclk2 = self
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.config
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.pclk2
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.map(|v| v.0)
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.unwrap_or_else(|| pclk_max.min(rcc_hclk / 2));
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let (rcc_pclk2, ppre2_bits, ppre2, rcc_timery_ker_ck) =
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Self::ppre_calculate(requested_pclk2, rcc_hclk, pclk_max, Some(timpre));
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let requested_pclk3 = self
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.config
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.pclk3
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.map(|v| v.0)
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.unwrap_or_else(|| pclk_max.min(rcc_hclk / 2));
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let (rcc_pclk3, ppre3_bits, ppre3, _) =
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Self::ppre_calculate(requested_pclk3, rcc_hclk, pclk_max, None);
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let requested_pclk4 = self
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.config
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.pclk4
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.map(|v| v.0)
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.unwrap_or_else(|| pclk_max.min(rcc_hclk / 2));
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let (rcc_pclk4, ppre4_bits, ppre4, _) =
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Self::ppre_calculate(requested_pclk4, rcc_hclk, pclk_max, None);
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Self::flash_setup(rcc_aclk, pwr.vos);
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// Start switching clocks -------------------
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// NOTE(unsafe) We have the RCC singleton
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unsafe {
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// Ensure CSI is on and stable
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RCC.cr().modify(|w| w.set_csion(Hsion::ON));
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while !RCC.cr().read().csirdy() {}
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// Ensure HSI48 is on and stable
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RCC.cr().modify(|w| w.set_hsi48on(Hsion::ON));
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while RCC.cr().read().hsi48on() == Hsion::OFF {}
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// XXX: support MCO ?
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let hse_ck = match self.config.hse {
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Some(hse) => {
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// Ensure HSE is on and stable
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RCC.cr().modify(|w| {
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w.set_hseon(Hsion::ON);
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w.set_hsebyp(if self.config.bypass_hse {
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Hsebyp::BYPASSED
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} else {
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Hsebyp::NOTBYPASSED
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});
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});
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while !RCC.cr().read().hserdy() {}
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Some(hse)
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}
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None => None,
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};
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let pllsrc = if self.config.hse.is_some() {
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Pllsrc::HSE
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} else {
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Pllsrc::HSI
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};
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RCC.pllckselr().modify(|w| w.set_pllsrc(pllsrc));
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if pll1_p_ck.is_some() {
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RCC.cr().modify(|w| w.set_pll1on(Hsion::ON));
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while !RCC.cr().read().pll1rdy() {}
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}
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if pll2_p_ck.is_some() {
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RCC.cr().modify(|w| w.set_pll2on(Hsion::ON));
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while !RCC.cr().read().pll2rdy() {}
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}
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if pll3_p_ck.is_some() {
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RCC.cr().modify(|w| w.set_pll3on(Hsion::ON));
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while !RCC.cr().read().pll3rdy() {}
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}
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// Core Prescaler / AHB Prescaler / APB3 Prescaler
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RCC.d1cfgr().modify(|w| {
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w.set_d1cpre(Hpre(d1cpre_bits));
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w.set_d1ppre(D1ppre(ppre3_bits));
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w.set_hpre(hpre_bits)
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});
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// Ensure core prescaler value is valid before future lower
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// core voltage
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while RCC.d1cfgr().read().d1cpre().0 != d1cpre_bits {}
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// APB1 / APB2 Prescaler
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RCC.d2cfgr().modify(|w| {
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w.set_d2ppre1(D2ppre1(ppre1_bits));
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w.set_d2ppre2(D2ppre1(ppre2_bits));
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});
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// APB4 Prescaler
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RCC.d3cfgr().modify(|w| w.set_d3ppre(D3ppre(ppre4_bits)));
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// Peripheral Clock (per_ck)
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RCC.d1ccipr().modify(|w| w.set_ckpersel(ckpersel));
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// Set timer clocks prescaler setting
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RCC.cfgr().modify(|w| w.set_timpre(timpre));
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// Select system clock source
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let sw = match (sys_use_pll1_p, self.config.hse.is_some()) {
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(true, _) => Sw::PLL1,
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(false, true) => Sw::HSE,
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_ => Sw::HSI,
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};
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RCC.cfgr().modify(|w| w.set_sw(sw));
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while RCC.cfgr().read().sws() != sw.0 {}
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// IO compensation cell - Requires CSI clock and SYSCFG
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assert!(RCC.cr().read().csirdy());
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RCC.apb4enr()
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.modify(|w| w.set_syscfgen(Apb4enrSyscfgen::ENABLED));
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// Enable the compensation cell, using back-bias voltage code
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// provide by the cell.
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critical_section::with(|_| {
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SYSCFG.cccsr().modify(|w| {
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w.set_en(true);
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w.set_cs(false);
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w.set_hslv(false);
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})
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});
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while !SYSCFG.cccsr().read().ready() {}
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CoreClocks {
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hclk: Hertz(rcc_hclk),
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pclk1: Hertz(rcc_pclk1),
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pclk2: Hertz(rcc_pclk2),
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pclk3: Hertz(rcc_pclk3),
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pclk4: Hertz(rcc_pclk4),
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ppre1,
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ppre2,
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ppre3,
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ppre4,
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csi_ck: Some(CSI),
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hsi_ck: Some(HSI),
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hsi48_ck: Some(HSI48),
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lsi_ck: Some(LSI),
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per_ck: Some(per_ck),
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hse_ck,
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pll1_p_ck: pll1_p_ck.map(Hertz),
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pll1_q_ck: pll1_q_ck.map(Hertz),
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pll1_r_ck: pll1_r_ck.map(Hertz),
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pll2_p_ck: pll2_p_ck.map(Hertz),
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pll2_q_ck: pll2_q_ck.map(Hertz),
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pll2_r_ck: pll2_r_ck.map(Hertz),
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pll3_p_ck: pll3_p_ck.map(Hertz),
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pll3_q_ck: pll3_q_ck.map(Hertz),
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pll3_r_ck: pll3_r_ck.map(Hertz),
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timx_ker_ck: rcc_timerx_ker_ck.map(Hertz),
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timy_ker_ck: rcc_timery_ker_ck.map(Hertz),
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sys_ck,
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c_ck: Hertz(sys_d1cpre_ck),
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}
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}
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}
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/// Enables debugging during WFI/WFE
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///
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/// Set `enable_dma1` to true if you do not have at least one bus master (other than the CPU)
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/// enable during WFI/WFE
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pub fn enable_debug_wfe(&mut self, _dbg: &mut peripherals::DBGMCU, enable_dma1: bool) {
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use crate::pac::rcc::vals::Ahb1enrDma1en;
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// NOTE(unsafe) We have exclusive access to the RCC and DBGMCU
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unsafe {
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if enable_dma1 {
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RCC.ahb1enr()
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.modify(|w| w.set_dma1en(Ahb1enrDma1en::ENABLED));
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}
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DBGMCU.cr().modify(|w| {
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w.set_dbgsleep_d1(true);
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w.set_dbgstby_d1(true);
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w.set_dbgstop_d1(true);
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});
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}
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}
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/// Setup traceclk
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/// Returns a pll1_r_ck
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fn traceclk_setup(&mut self, sys_use_pll1_p: bool) {
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let pll1_r_ck = match (sys_use_pll1_p, self.config.pll1.r_ck) {
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// pll1_p_ck selected as system clock but pll1_r_ck not
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// set. The traceclk mux is synchronous with the system
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// clock mux, but has pll1_r_ck as an input. In order to
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// keep traceclk running, we force a pll1_r_ck.
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(true, None) => Some(Hertz(self.config.pll1.p_ck.unwrap().0 / 2)),
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// Either pll1 not selected as system clock, free choice
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// of pll1_r_ck. Or pll1 is selected, assume user has set
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// a suitable pll1_r_ck frequency.
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_ => self.config.pll1.r_ck,
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};
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self.config.pll1.r_ck = pll1_r_ck;
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}
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/// Divider calculator for pclk 1 - 4
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///
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/// Returns real pclk, bits, ppre and the timer kernel clock
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fn ppre_calculate(
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requested_pclk: u32,
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hclk: u32,
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max_pclk: u32,
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tim_pre: Option<Timpre>,
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) -> (u32, u8, u8, Option<u32>) {
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let (bits, ppre) = match (hclk + requested_pclk - 1) / requested_pclk {
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0 => panic!(),
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1 => (0b000, 1),
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2 => (0b100, 2),
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3..=5 => (0b101, 4),
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6..=11 => (0b110, 8),
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_ => (0b111, 16),
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};
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let real_pclk = hclk / u32::from(ppre);
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assert!(real_pclk <= max_pclk);
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let tim_ker_clk = if let Some(tim_pre) = tim_pre {
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let clk = match (bits, tim_pre) {
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(0b101, Timpre::DEFAULTX2) => hclk / 2,
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(0b110, Timpre::DEFAULTX4) => hclk / 2,
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(0b110, Timpre::DEFAULTX2) => hclk / 4,
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(0b111, Timpre::DEFAULTX4) => hclk / 4,
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(0b111, Timpre::DEFAULTX2) => hclk / 8,
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_ => hclk,
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};
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Some(clk)
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} else {
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None
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};
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(real_pclk, bits, ppre, tim_ker_clk)
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}
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/// Setup sys_ck
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/// Returns sys_ck frequency, and a pll1_p_ck
|
|
fn sys_ck_setup(&mut self, srcclk: Hertz) -> (Hertz, bool) {
|
|
// Compare available with wanted clocks
|
|
let sys_ck = self.config.sys_ck.unwrap_or(srcclk);
|
|
|
|
if sys_ck != srcclk {
|
|
// The requested system clock is not the immediately available
|
|
// HSE/HSI clock. Perhaps there are other ways of obtaining
|
|
// the requested system clock (such as `HSIDIV`) but we will
|
|
// ignore those for now.
|
|
//
|
|
// Therefore we must use pll1_p_ck
|
|
let pll1_p_ck = match self.config.pll1.p_ck {
|
|
Some(p_ck) => {
|
|
assert!(p_ck == sys_ck,
|
|
"Error: Cannot set pll1_p_ck independently as it must be used to generate sys_ck");
|
|
Some(p_ck)
|
|
}
|
|
None => Some(sys_ck),
|
|
};
|
|
self.config.pll1.p_ck = pll1_p_ck;
|
|
|
|
(sys_ck, true)
|
|
} else {
|
|
// sys_ck is derived directly from a source clock
|
|
// (HSE/HSI). pll1_p_ck can be as requested
|
|
(sys_ck, false)
|
|
}
|
|
}
|
|
|
|
fn flash_setup(rcc_aclk: u32, vos: VoltageScale) {
|
|
use crate::pac::FLASH;
|
|
|
|
// ACLK in MHz, round down and subtract 1 from integers. eg.
|
|
// 61_999_999 -> 61MHz
|
|
// 62_000_000 -> 61MHz
|
|
// 62_000_001 -> 62MHz
|
|
let rcc_aclk_mhz = (rcc_aclk - 1) / 1_000_000;
|
|
|
|
// See RM0433 Rev 7 Table 17. FLASH recommended number of wait
|
|
// states and programming delay
|
|
let (wait_states, progr_delay) = match vos {
|
|
// VOS 0 range VCORE 1.26V - 1.40V
|
|
VoltageScale::Scale0 => match rcc_aclk_mhz {
|
|
0..=69 => (0, 0),
|
|
70..=139 => (1, 1),
|
|
140..=184 => (2, 1),
|
|
185..=209 => (2, 2),
|
|
210..=224 => (3, 2),
|
|
225..=239 => (4, 2),
|
|
_ => (7, 3),
|
|
},
|
|
// VOS 1 range VCORE 1.15V - 1.26V
|
|
VoltageScale::Scale1 => match rcc_aclk_mhz {
|
|
0..=69 => (0, 0),
|
|
70..=139 => (1, 1),
|
|
140..=184 => (2, 1),
|
|
185..=209 => (2, 2),
|
|
210..=224 => (3, 2),
|
|
_ => (7, 3),
|
|
},
|
|
// VOS 2 range VCORE 1.05V - 1.15V
|
|
VoltageScale::Scale2 => match rcc_aclk_mhz {
|
|
0..=54 => (0, 0),
|
|
55..=109 => (1, 1),
|
|
110..=164 => (2, 1),
|
|
165..=224 => (3, 2),
|
|
_ => (7, 3),
|
|
},
|
|
// VOS 3 range VCORE 0.95V - 1.05V
|
|
VoltageScale::Scale3 => match rcc_aclk_mhz {
|
|
0..=44 => (0, 0),
|
|
45..=89 => (1, 1),
|
|
90..=134 => (2, 1),
|
|
135..=179 => (3, 2),
|
|
180..=224 => (4, 2),
|
|
_ => (7, 3),
|
|
},
|
|
};
|
|
|
|
// NOTE(unsafe) Atomic write
|
|
unsafe {
|
|
FLASH.acr().write(|w| {
|
|
w.set_wrhighfreq(progr_delay);
|
|
w.set_latency(wait_states)
|
|
});
|
|
while FLASH.acr().read().latency() != wait_states {}
|
|
}
|
|
}
|
|
}
|
|
|
|
// TODO
|
|
pub type SystemClock = ();
|
|
pub unsafe fn init(_config: Config) -> SystemClock {}
|