612 lines
19 KiB
Rust
612 lines
19 KiB
Rust
use chiptool::generate::CommonModule;
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use proc_macro2::TokenStream;
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use regex::Regex;
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use std::collections::{BTreeMap, HashMap, HashSet};
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use std::fmt::Write as _;
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use std::fs;
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use std::fs::File;
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use std::io::Write;
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use std::path::Path;
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use std::path::PathBuf;
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use std::str::FromStr;
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use chiptool::util::ToSanitizedSnakeCase;
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use chiptool::{generate, ir, transform};
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mod data;
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use data::*;
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fn make_peripheral_counts(out: &mut String, data: &BTreeMap<String, u8>) {
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write!(
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out,
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"#[macro_export]
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macro_rules! peripheral_count {{
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"
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)
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.unwrap();
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for (name, count) in data {
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write!(out, "({}) => ({});\n", name, count,).unwrap();
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}
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write!(out, " }}\n").unwrap();
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}
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fn make_dma_channel_counts(out: &mut String, data: &BTreeMap<String, u8>) {
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if data.len() == 0 {
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return;
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}
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write!(
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out,
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"#[macro_export]
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macro_rules! dma_channels_count {{
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"
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)
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.unwrap();
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for (name, count) in data {
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write!(out, "({}) => ({});\n", name, count,).unwrap();
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}
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write!(out, " }}\n").unwrap();
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}
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fn make_table(out: &mut String, name: &str, data: &Vec<Vec<String>>) {
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write!(
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out,
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"#[macro_export]
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macro_rules! {} {{
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($($pat:tt => $code:tt;)*) => {{
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macro_rules! __{}_inner {{
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$(($pat) => $code;)*
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($_:tt) => {{}}
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}}
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",
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name, name
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)
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.unwrap();
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for row in data {
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write!(out, " __{}_inner!(({}));\n", name, row.join(",")).unwrap();
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}
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write!(
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out,
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" }};
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}}"
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)
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.unwrap();
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}
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pub struct Options {
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pub chips: Vec<String>,
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pub out_dir: PathBuf,
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pub data_dir: PathBuf,
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}
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pub fn gen_chip(
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options: &Options,
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chip_core_name: &str,
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chip: &Chip,
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core: &Core,
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core_index: usize,
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all_peripheral_versions: &mut HashSet<(String, String)>,
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) {
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let mut ir = ir::IR::new();
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let mut dev = ir::Device {
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interrupts: Vec::new(),
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peripherals: Vec::new(),
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};
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// Load DBGMCU register for chip
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let mut dbgmcu: Option<ir::IR> = core.peripherals.iter().find_map(|p| {
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if p.name == "DBGMCU" {
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p.block.as_ref().map(|block| {
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let bi = BlockInfo::parse(block);
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let dbgmcu_reg_path = options
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.data_dir
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.join("registers")
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.join(&format!("{}_{}.yaml", bi.module, bi.version));
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serde_yaml::from_reader(File::open(dbgmcu_reg_path).unwrap()).unwrap()
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})
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} else {
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None
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}
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});
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let mut peripheral_versions: BTreeMap<String, String> = BTreeMap::new();
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let mut pin_table: Vec<Vec<String>> = Vec::new();
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let mut interrupt_table: Vec<Vec<String>> = Vec::new();
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let mut peripherals_table: Vec<Vec<String>> = Vec::new();
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let mut peripheral_pins_table: Vec<Vec<String>> = Vec::new();
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let mut peripheral_rcc_table: Vec<Vec<String>> = Vec::new();
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let mut dma_channels_table: Vec<Vec<String>> = Vec::new();
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let mut peripheral_dma_channels_table: Vec<Vec<String>> = Vec::new();
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let mut peripheral_counts: BTreeMap<String, u8> = BTreeMap::new();
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let mut dma_channel_counts: BTreeMap<String, u8> = BTreeMap::new();
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let mut dbgmcu_table: Vec<Vec<String>> = Vec::new();
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let gpio_base = core
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.peripherals
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.iter()
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.find(|p| p.name == "GPIOA")
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.unwrap()
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.address as u32;
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let gpio_stride = 0x400;
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let number_suffix_re = Regex::new("^(.*?)[0-9]*$").unwrap();
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if let Some(ref mut reg) = dbgmcu {
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if let Some(ref cr) = reg.fieldsets.get("CR") {
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for field in cr.fields.iter().filter(|e| e.name.contains("DBG")) {
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let mut fn_name = String::new();
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fn_name.push_str("set_");
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fn_name.push_str(&field.name.to_sanitized_snake_case());
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dbgmcu_table.push(vec!["cr".into(), fn_name]);
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}
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}
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}
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for p in &core.peripherals {
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let captures = number_suffix_re.captures(&p.name).unwrap();
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let root_peri_name = captures.get(1).unwrap().as_str().to_string();
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peripheral_counts.insert(
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root_peri_name.clone(),
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peripheral_counts.get(&root_peri_name).map_or(1, |v| v + 1),
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);
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let mut ir_peri = ir::Peripheral {
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name: p.name.clone(),
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array: None,
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base_address: p.address,
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block: None,
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description: None,
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interrupts: HashMap::new(),
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};
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if let Some(block) = &p.block {
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let bi = BlockInfo::parse(block);
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peripheral_counts.insert(
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bi.module.clone(),
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peripheral_counts.get(&bi.module).map_or(1, |v| v + 1),
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);
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for pin in &p.pins {
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let mut row = Vec::new();
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row.push(p.name.clone());
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row.push(bi.module.clone());
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row.push(bi.block.clone());
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row.push(pin.pin.clone());
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row.push(pin.signal.clone());
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if let Some(ref af) = pin.af {
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row.push(af.clone());
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}
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peripheral_pins_table.push(row);
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}
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for irq in &p.interrupts {
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let mut row = Vec::new();
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row.push(p.name.clone());
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row.push(bi.module.clone());
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row.push(bi.block.clone());
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row.push(irq.signal.clone());
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row.push(irq.interrupt.to_ascii_uppercase());
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interrupt_table.push(row)
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}
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for ch in &p.dma_channels {
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let mut row = Vec::new();
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row.push(p.name.clone());
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row.push(bi.module.clone());
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row.push(bi.block.clone());
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row.push(ch.signal.clone());
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row.push(if let Some(channel) = &ch.channel {
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format!("{{channel: {}}}", channel)
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} else if let Some(dmamux) = &ch.dmamux {
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format!("{{dmamux: {}}}", dmamux)
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} else {
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unreachable!();
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});
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row.push(if let Some(request) = ch.request {
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request.to_string()
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} else {
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"()".to_string()
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});
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if peripheral_dma_channels_table
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.iter()
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.find(|a| a[..a.len() - 1] == row[..row.len() - 1])
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.is_none()
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{
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peripheral_dma_channels_table.push(row);
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}
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}
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let mut peripheral_row = Vec::new();
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peripheral_row.push(bi.module.clone());
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peripheral_row.push(p.name.clone());
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peripherals_table.push(peripheral_row);
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if let Some(old_version) =
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peripheral_versions.insert(bi.module.clone(), bi.version.clone())
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{
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if old_version != bi.version {
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panic!(
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"Peripheral {} has multiple versions: {} and {}",
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bi.module, old_version, bi.version
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);
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}
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}
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ir_peri.block = Some(format!("{}::{}", bi.module, bi.block));
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match bi.module.as_str() {
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"gpio" => {
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let port_letter = p.name.chars().skip(4).next().unwrap();
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assert_eq!(0, (p.address as u32 - gpio_base) % gpio_stride);
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let port_num = (p.address as u32 - gpio_base) / gpio_stride;
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for pin_num in 0u32..16 {
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let pin_name = format!("P{}{}", port_letter, pin_num);
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pin_table.push(vec![
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pin_name.clone(),
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p.name.clone(),
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port_num.to_string(),
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pin_num.to_string(),
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format!("EXTI{}", pin_num),
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]);
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}
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}
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_ => {}
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}
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if let Some(rcc) = &p.rcc {
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let mut clock = rcc.clock.to_ascii_lowercase();
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if p.name.starts_with("TIM") {
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clock = format!("{}_tim", clock)
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}
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let mut row = Vec::new();
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row.push(p.name.clone());
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row.push(bi.module.clone());
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row.push(bi.block.clone());
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row.push(clock);
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for reg in [&rcc.registers.enable, &rcc.registers.reset] {
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if let Some(reg) = reg {
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row.push(format!(
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"({}, {}, set_{})",
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reg.register.to_ascii_lowercase(),
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reg.field.to_ascii_lowercase(),
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reg.field.to_ascii_lowercase()
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));
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} else {
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row.push("_".to_string())
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}
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}
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peripheral_rcc_table.push(row);
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}
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}
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dev.peripherals.push(ir_peri);
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}
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for ch in &core.dma_channels {
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let mut row = Vec::new();
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let dma_peri = core.peripherals.iter().find(|p| p.name == ch.dma).unwrap();
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let bi = BlockInfo::parse(dma_peri.block.as_ref().unwrap());
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row.push(ch.name.clone());
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row.push(ch.dma.clone());
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row.push(bi.module.clone());
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row.push(ch.channel.to_string());
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if let Some(dmamux) = &ch.dmamux {
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let dmamux_channel = ch.dmamux_channel.unwrap();
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row.push(format!(
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"{{dmamux: {}, dmamux_channel: {}}}",
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dmamux, dmamux_channel
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));
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} else {
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row.push("{}".to_string());
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}
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dma_channels_table.push(row);
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let dma_peri_name = ch.dma.clone();
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dma_channel_counts.insert(
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dma_peri_name.clone(),
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dma_channel_counts.get(&dma_peri_name).map_or(1, |v| v + 1),
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);
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}
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for irq in &core.interrupts {
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dev.interrupts.push(ir::Interrupt {
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name: irq.name.clone(),
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description: None,
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value: irq.number,
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});
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let name = irq.name.to_ascii_uppercase();
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interrupt_table.push(vec![name.clone()]);
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if name.contains("EXTI") {
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interrupt_table.push(vec!["EXTI".to_string(), name.clone()]);
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}
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}
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ir.devices.insert("".to_string(), dev);
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let mut extra = format!(
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"pub fn GPIO(n: usize) -> gpio::Gpio {{
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gpio::Gpio(({} + {}*n) as _)
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}}",
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gpio_base, gpio_stride,
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);
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for (module, version) in &peripheral_versions {
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all_peripheral_versions.insert((module.clone(), version.clone()));
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write!(
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&mut extra,
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"#[path=\"../../peripherals/{}_{}.rs\"] pub mod {};\n",
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module, version, module
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)
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.unwrap();
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}
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write!(
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&mut extra,
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"pub const CORE_INDEX: usize = {};\n",
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core_index
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)
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.unwrap();
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// Cleanups!
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transform::sort::Sort {}.run(&mut ir).unwrap();
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transform::Sanitize {}.run(&mut ir).unwrap();
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// ==============================
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// Setup chip dir
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let chip_dir = options
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.out_dir
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.join("src/chips")
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.join(chip_core_name.to_ascii_lowercase());
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fs::create_dir_all(&chip_dir).unwrap();
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// ==============================
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// generate pac.rs
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let data = generate::render(&ir, &gen_opts()).unwrap().to_string();
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let data = data.replace("] ", "]\n");
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// Remove inner attributes like #![no_std]
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let data = Regex::new("# *! *\\[.*\\]").unwrap().replace_all(&data, "");
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let mut file = File::create(chip_dir.join("pac.rs")).unwrap();
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file.write_all(data.as_bytes()).unwrap();
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file.write_all(extra.as_bytes()).unwrap();
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let mut device_x = String::new();
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for irq in &core.interrupts {
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write!(
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&mut device_x,
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"PROVIDE({} = DefaultHandler);\n",
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irq.name.to_ascii_uppercase()
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)
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.unwrap();
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}
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// ==============================
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// generate mod.rs
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let mut data = String::new();
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write!(&mut data, "#[cfg(feature=\"pac\")] mod pac;").unwrap();
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write!(&mut data, "#[cfg(feature=\"pac\")] pub use pac::*; ").unwrap();
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let peripheral_version_table = peripheral_versions
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.iter()
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.map(|(kind, version)| vec![kind.clone(), version.clone()])
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.collect();
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make_table(&mut data, "pins", &pin_table);
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make_table(&mut data, "interrupts", &interrupt_table);
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make_table(&mut data, "peripherals", &peripherals_table);
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make_table(&mut data, "peripheral_versions", &peripheral_version_table);
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make_table(&mut data, "peripheral_pins", &peripheral_pins_table);
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make_table(
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&mut data,
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"peripheral_dma_channels",
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&peripheral_dma_channels_table,
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);
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make_table(&mut data, "peripheral_rcc", &peripheral_rcc_table);
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make_table(&mut data, "dma_channels", &dma_channels_table);
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make_table(&mut data, "dbgmcu", &dbgmcu_table);
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make_peripheral_counts(&mut data, &peripheral_counts);
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make_dma_channel_counts(&mut data, &dma_channel_counts);
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let mut file = File::create(chip_dir.join("mod.rs")).unwrap();
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file.write_all(data.as_bytes()).unwrap();
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// ==============================
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// generate device.x
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File::create(chip_dir.join("device.x"))
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.unwrap()
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.write_all(device_x.as_bytes())
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.unwrap();
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// ==============================
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// generate default memory.x
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gen_memory_x(&chip_dir, &chip);
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}
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fn load_chip(options: &Options, name: &str) -> Chip {
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let chip_path = options
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.data_dir
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.join("chips")
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.join(&format!("{}.json", name));
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let chip = fs::read(chip_path).expect(&format!("Could not load chip {}", name));
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serde_yaml::from_slice(&chip).unwrap()
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}
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fn gen_opts() -> generate::Options {
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generate::Options {
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common_module: CommonModule::External(TokenStream::from_str("crate::common").unwrap()),
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}
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}
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pub fn gen(options: Options) {
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fs::create_dir_all(options.out_dir.join("src/peripherals")).unwrap();
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fs::create_dir_all(options.out_dir.join("src/chips")).unwrap();
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let mut all_peripheral_versions: HashSet<(String, String)> = HashSet::new();
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let mut chip_core_names: Vec<String> = Vec::new();
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for chip_name in &options.chips {
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println!("Generating {}...", chip_name);
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let chip = load_chip(&options, chip_name);
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for (core_index, core) in chip.cores.iter().enumerate() {
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let chip_core_name = match chip.cores.len() {
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1 => chip_name.clone(),
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_ => format!("{}-{}", chip_name, core.name),
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};
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chip_core_names.push(chip_core_name.clone());
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gen_chip(
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&options,
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&chip_core_name,
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&chip,
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core,
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core_index,
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&mut all_peripheral_versions,
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)
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}
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}
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for (module, version) in all_peripheral_versions {
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println!("loading {} {}", module, version);
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let regs_path = Path::new(&options.data_dir)
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.join("registers")
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.join(&format!("{}_{}.yaml", module, version));
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let mut ir: ir::IR = serde_yaml::from_reader(File::open(regs_path).unwrap()).unwrap();
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transform::expand_extends::ExpandExtends {}
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.run(&mut ir)
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.unwrap();
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transform::map_names(&mut ir, |k, s| match k {
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transform::NameKind::Block => *s = format!("{}", s),
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transform::NameKind::Fieldset => *s = format!("regs::{}", s),
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transform::NameKind::Enum => *s = format!("vals::{}", s),
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_ => {}
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});
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transform::sort::Sort {}.run(&mut ir).unwrap();
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transform::Sanitize {}.run(&mut ir).unwrap();
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let items = generate::render(&ir, &gen_opts()).unwrap();
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let mut file = File::create(
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options
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.out_dir
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.join("src/peripherals")
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.join(format!("{}_{}.rs", module, version)),
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)
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.unwrap();
|
|
let data = items.to_string().replace("] ", "]\n");
|
|
|
|
// Remove inner attributes like #![no_std]
|
|
let re = Regex::new("# *! *\\[.*\\]").unwrap();
|
|
let data = re.replace_all(&data, "");
|
|
file.write_all(data.as_bytes()).unwrap();
|
|
}
|
|
|
|
// Generate src/lib_inner.rs
|
|
const PATHS_MARKER: &[u8] = b"// GEN PATHS HERE";
|
|
let librs = include_bytes!("assets/lib_inner.rs");
|
|
let i = bytes_find(librs, PATHS_MARKER).unwrap();
|
|
let mut paths = String::new();
|
|
|
|
for name in chip_core_names {
|
|
let x = name.to_ascii_lowercase();
|
|
write!(
|
|
&mut paths,
|
|
"#[cfg_attr(feature=\"{}\", path = \"chips/{}/mod.rs\")]",
|
|
x, x
|
|
)
|
|
.unwrap();
|
|
}
|
|
let mut contents: Vec<u8> = Vec::new();
|
|
contents.extend(&librs[..i]);
|
|
contents.extend(paths.as_bytes());
|
|
contents.extend(&librs[i + PATHS_MARKER.len()..]);
|
|
fs::write(options.out_dir.join("src").join("lib_inner.rs"), &contents).unwrap();
|
|
|
|
// Generate src/lib.rs
|
|
const CUT_MARKER: &[u8] = b"// GEN CUT HERE";
|
|
let librs = include_bytes!("../../stm32-metapac/src/lib.rs");
|
|
let i = bytes_find(librs, CUT_MARKER).unwrap();
|
|
let mut contents: Vec<u8> = Vec::new();
|
|
contents.extend(&librs[..i]);
|
|
contents.extend(b"include!(\"lib_inner.rs\");\n");
|
|
fs::write(options.out_dir.join("src").join("lib.rs"), contents).unwrap();
|
|
|
|
// Generate src/common.rs
|
|
fs::write(
|
|
options.out_dir.join("src").join("common.rs"),
|
|
generate::COMMON_MODULE,
|
|
)
|
|
.unwrap();
|
|
|
|
// Generate Cargo.toml
|
|
const BUILDDEP_BEGIN: &[u8] = b"# BEGIN BUILD DEPENDENCIES";
|
|
const BUILDDEP_END: &[u8] = b"# END BUILD DEPENDENCIES";
|
|
|
|
let mut contents = include_bytes!("../../stm32-metapac/Cargo.toml").to_vec();
|
|
let begin = bytes_find(&contents, BUILDDEP_BEGIN).unwrap();
|
|
let end = bytes_find(&contents, BUILDDEP_END).unwrap() + BUILDDEP_END.len();
|
|
contents.drain(begin..end);
|
|
fs::write(options.out_dir.join("Cargo.toml"), contents).unwrap();
|
|
|
|
// Generate build.rs
|
|
fs::write(
|
|
options.out_dir.join("build.rs"),
|
|
include_bytes!("assets/build.rs"),
|
|
)
|
|
.unwrap();
|
|
}
|
|
|
|
fn bytes_find(haystack: &[u8], needle: &[u8]) -> Option<usize> {
|
|
haystack
|
|
.windows(needle.len())
|
|
.position(|window| window == needle)
|
|
}
|
|
|
|
fn gen_memory_x(out_dir: &PathBuf, chip: &Chip) {
|
|
let mut memory_x = String::new();
|
|
|
|
let flash = chip.memory.iter().find(|r| r.name == "BANK_1").unwrap();
|
|
let ram = chip.memory.iter().find(|r| r.name == "SRAM").unwrap();
|
|
|
|
write!(memory_x, "MEMORY\n{{\n").unwrap();
|
|
write!(
|
|
memory_x,
|
|
" FLASH : ORIGIN = 0x{:x}, LENGTH = {}\n",
|
|
flash.address, flash.size,
|
|
)
|
|
.unwrap();
|
|
write!(
|
|
memory_x,
|
|
" RAM : ORIGIN = 0x{:x}, LENGTH = {}\n",
|
|
ram.address, ram.size,
|
|
)
|
|
.unwrap();
|
|
write!(memory_x, "}}").unwrap();
|
|
|
|
fs::create_dir_all(out_dir.join("memory_x")).unwrap();
|
|
let mut file = File::create(out_dir.join("memory_x").join("memory.x")).unwrap();
|
|
file.write_all(memory_x.as_bytes()).unwrap();
|
|
}
|