152 lines
4.4 KiB
Rust
152 lines
4.4 KiB
Rust
#[derive(Copy, Clone, Debug, PartialEq)]
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#[repr(u8)]
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#[allow(dead_code)]
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pub enum RtcClockSource {
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/// 00: No clock
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NoClock = 0b00,
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/// 01: LSE oscillator clock used as RTC clock
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LSE = 0b01,
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/// 10: LSI oscillator clock used as RTC clock
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LSI = 0b10,
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/// 11: HSE oscillator clock divided by 32 used as RTC clock
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HSE = 0b11,
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}
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#[cfg(not(any(rtc_v2l0, rtc_v2l1, stm32c0)))]
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#[allow(dead_code)]
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type Bdcr = crate::pac::rcc::regs::Bdcr;
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#[cfg(any(rtc_v2l0, rtc_v2l1))]
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#[allow(dead_code)]
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type Bdcr = crate::pac::rcc::regs::Csr;
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#[allow(dead_code)]
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pub struct BackupDomain {}
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impl BackupDomain {
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#[cfg(any(
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rtc_v2f0, rtc_v2f2, rtc_v2f3, rtc_v2f4, rtc_v2f7, rtc_v2h7, rtc_v2l0, rtc_v2l1, rtc_v2l4, rtc_v2wb, rtc_v3,
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rtc_v3u5
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))]
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#[allow(dead_code, unused_variables)]
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fn modify<R>(f: impl FnOnce(&mut Bdcr) -> R) -> R {
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#[cfg(any(rtc_v2f2, rtc_v2f3, rtc_v2l1))]
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let cr = crate::pac::PWR.cr();
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#[cfg(any(rtc_v2f4, rtc_v2f7, rtc_v2h7, rtc_v2l4, rtc_v2wb, rtc_v3, rtc_v3u5))]
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let cr = crate::pac::PWR.cr1();
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// TODO: Missing from PAC for l0 and f0?
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#[cfg(not(any(rtc_v2f0, rtc_v2l0, rtc_v3u5)))]
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{
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cr.modify(|w| w.set_dbp(true));
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while !cr.read().dbp() {}
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}
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#[cfg(any(rtc_v2l0, rtc_v2l1))]
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let cr = crate::pac::RCC.csr();
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#[cfg(not(any(rtc_v2l0, rtc_v2l1)))]
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let cr = crate::pac::RCC.bdcr();
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cr.modify(|w| f(w))
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}
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#[cfg(any(
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rtc_v2f0, rtc_v2f2, rtc_v2f3, rtc_v2f4, rtc_v2f7, rtc_v2h7, rtc_v2l0, rtc_v2l1, rtc_v2l4, rtc_v2wb, rtc_v3,
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rtc_v3u5
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))]
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#[allow(dead_code)]
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fn read() -> Bdcr {
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#[cfg(any(rtc_v2l0, rtc_v2l1))]
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let r = crate::pac::RCC.csr().read();
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#[cfg(not(any(rtc_v2l0, rtc_v2l1)))]
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let r = crate::pac::RCC.bdcr().read();
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r
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}
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#[cfg(any(
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rtc_v2f0, rtc_v2f2, rtc_v2f3, rtc_v2f4, rtc_v2f7, rtc_v2h7, rtc_v2l0, rtc_v2l1, rtc_v2l4, rtc_v2wb, rtc_v3,
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rtc_v3u5
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))]
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#[allow(dead_code, unused_variables)]
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pub fn set_rtc_clock_source(clock_source: RtcClockSource) {
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let clock_source = clock_source as u8;
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#[cfg(any(
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all(not(any(rtc_v3, rtc_v3u5)), not(rtc_v2wb)),
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all(any(rtc_v3, rtc_v3u5), not(any(rcc_wl5, rcc_wle)))
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))]
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let clock_source = crate::pac::rcc::vals::Rtcsel::from_bits(clock_source);
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#[cfg(not(rtc_v2wb))]
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Self::modify(|w| {
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// Select RTC source
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w.set_rtcsel(clock_source);
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});
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}
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#[cfg(any(
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rtc_v2f0, rtc_v2f2, rtc_v2f3, rtc_v2f4, rtc_v2f7, rtc_v2h7, rtc_v2l0, rtc_v2l1, rtc_v2l4, rtc_v2wb
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))]
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#[allow(dead_code)]
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pub fn enable_rtc() {
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let reg = Self::read();
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#[cfg(any(rtc_v2h7, rtc_v2l4, rtc_v2wb))]
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assert!(!reg.lsecsson(), "RTC is not compatible with LSE CSS, yet.");
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if !reg.rtcen() {
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#[cfg(not(any(rtc_v2l0, rtc_v2l1, rtc_v2f2)))]
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Self::modify(|w| w.set_bdrst(true));
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Self::modify(|w| {
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// Reset
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#[cfg(not(any(rtc_v2l0, rtc_v2l1)))]
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w.set_bdrst(false);
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w.set_rtcen(true);
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w.set_rtcsel(reg.rtcsel());
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// Restore bcdr
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#[cfg(any(rtc_v2l4, rtc_v2wb))]
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w.set_lscosel(reg.lscosel());
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#[cfg(any(rtc_v2l4, rtc_v2wb))]
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w.set_lscoen(reg.lscoen());
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w.set_lseon(reg.lseon());
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#[cfg(any(rtc_v2f0, rtc_v2f7, rtc_v2h7, rtc_v2l4, rtc_v2wb))]
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w.set_lsedrv(reg.lsedrv());
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w.set_lsebyp(reg.lsebyp());
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});
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}
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}
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#[cfg(any(rtc_v3, rtc_v3u5))]
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#[allow(dead_code)]
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pub fn enable_rtc() {
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let reg = Self::read();
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assert!(!reg.lsecsson(), "RTC is not compatible with LSE CSS, yet.");
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if !reg.rtcen() {
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Self::modify(|w| w.set_bdrst(true));
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Self::modify(|w| {
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w.set_bdrst(false);
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w.set_rtcen(true);
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w.set_rtcsel(reg.rtcsel());
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// Restore bcdr
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w.set_lscosel(reg.lscosel());
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w.set_lscoen(reg.lscoen());
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w.set_lseon(reg.lseon());
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w.set_lsedrv(reg.lsedrv());
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w.set_lsebyp(reg.lsebyp());
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});
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}
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}
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}
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