509 lines
14 KiB
Rust
509 lines
14 KiB
Rust
use core::marker::PhantomData;
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use embassy_hal_common::into_ref;
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use stm32_metapac::rcc::vals::{Mco1, Mco2, Mcopre};
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use super::sealed::RccPeripheral;
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use crate::gpio::sealed::AFType;
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use crate::gpio::Speed;
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use crate::pac::rcc::vals::{Hpre, Ppre, Sw};
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use crate::pac::{FLASH, PWR, RCC};
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use crate::rcc::{set_freqs, Clocks};
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use crate::time::Hertz;
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use crate::{peripherals, Peripheral};
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/// HSI speed
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pub const HSI_FREQ: Hertz = Hertz(16_000_000);
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/// LSI speed
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pub const LSI_FREQ: Hertz = Hertz(32_000);
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/// Clocks configuration
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#[non_exhaustive]
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#[derive(Default)]
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pub struct Config {
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pub hse: Option<Hertz>,
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pub bypass_hse: bool,
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pub hclk: Option<Hertz>,
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pub sys_ck: Option<Hertz>,
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pub pclk1: Option<Hertz>,
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pub pclk2: Option<Hertz>,
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pub plli2s: Option<Hertz>,
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pub pll48: bool,
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}
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#[cfg(stm32f410)]
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unsafe fn setup_i2s_pll(_vco_in: u32, _plli2s: Option<u32>) -> Option<u32> {
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None
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}
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// Not currently implemented, but will be in the future
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#[cfg(any(stm32f411, stm32f412, stm32f413, stm32f423, stm32f446))]
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unsafe fn setup_i2s_pll(_vco_in: u32, _plli2s: Option<u32>) -> Option<u32> {
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None
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}
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#[cfg(not(any(stm32f410, stm32f411, stm32f412, stm32f413, stm32f423, stm32f446)))]
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unsafe fn setup_i2s_pll(vco_in: u32, plli2s: Option<u32>) -> Option<u32> {
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let min_div = 2;
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let max_div = 7;
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let target = match plli2s {
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Some(target) => target,
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None => return None,
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};
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// We loop through the possible divider values to find the best configuration. Looping
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// through all possible "N" values would result in more iterations.
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let (n, outdiv, output, _error) = (min_div..=max_div)
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.filter_map(|outdiv| {
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let target_vco_out = match target.checked_mul(outdiv) {
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Some(x) => x,
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None => return None,
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};
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let n = (target_vco_out + (vco_in >> 1)) / vco_in;
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let vco_out = vco_in * n;
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if !(100_000_000..=432_000_000).contains(&vco_out) {
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return None;
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}
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let output = vco_out / outdiv;
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let error = (output as i32 - target as i32).unsigned_abs();
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Some((n, outdiv, output, error))
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})
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.min_by_key(|(_, _, _, error)| *error)?;
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RCC.plli2scfgr().modify(|w| {
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w.set_plli2sn(n as u16);
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w.set_plli2sr(outdiv as u8);
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});
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Some(output)
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}
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unsafe fn setup_pll(
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pllsrcclk: u32,
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use_hse: bool,
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pllsysclk: Option<u32>,
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plli2s: Option<u32>,
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pll48clk: bool,
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) -> PllResults {
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use crate::pac::rcc::vals::{Pllp, Pllsrc};
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let sysclk = pllsysclk.unwrap_or(pllsrcclk);
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if pllsysclk.is_none() && !pll48clk {
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RCC.pllcfgr().modify(|w| w.set_pllsrc(Pllsrc(use_hse as u8)));
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return PllResults {
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use_pll: false,
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pllsysclk: None,
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pll48clk: None,
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plli2sclk: None,
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};
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}
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// Input divisor from PLL source clock, must result to frequency in
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// the range from 1 to 2 MHz
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let pllm_min = (pllsrcclk + 1_999_999) / 2_000_000;
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let pllm_max = pllsrcclk / 1_000_000;
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// Sysclk output divisor must be one of 2, 4, 6 or 8
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let sysclk_div = core::cmp::min(8, (432_000_000 / sysclk) & !1);
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let target_freq = if pll48clk { 48_000_000 } else { sysclk * sysclk_div };
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// Find the lowest pllm value that minimize the difference between
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// target frequency and the real vco_out frequency.
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let pllm = unwrap!((pllm_min..=pllm_max).min_by_key(|pllm| {
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let vco_in = pllsrcclk / pllm;
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let plln = target_freq / vco_in;
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target_freq - vco_in * plln
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}));
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let vco_in = pllsrcclk / pllm;
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assert!((1_000_000..=2_000_000).contains(&vco_in));
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// Main scaler, must result in >= 100MHz (>= 192MHz for F401)
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// and <= 432MHz, min 50, max 432
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let plln = if pll48clk {
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// try the different valid pllq according to the valid
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// main scaller values, and take the best
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let pllq = unwrap!((4..=9).min_by_key(|pllq| {
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let plln = 48_000_000 * pllq / vco_in;
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let pll48_diff = 48_000_000 - vco_in * plln / pllq;
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let sysclk_diff = (sysclk as i32 - (vco_in * plln / sysclk_div) as i32).abs();
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(pll48_diff, sysclk_diff)
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}));
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48_000_000 * pllq / vco_in
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} else {
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sysclk * sysclk_div / vco_in
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};
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let pllp = (sysclk_div / 2) - 1;
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let pllq = (vco_in * plln + 47_999_999) / 48_000_000;
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let real_pll48clk = vco_in * plln / pllq;
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RCC.pllcfgr().modify(|w| {
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w.set_pllm(pllm as u8);
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w.set_plln(plln as u16);
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w.set_pllp(Pllp(pllp as u8));
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w.set_pllq(pllq as u8);
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w.set_pllsrc(Pllsrc(use_hse as u8));
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});
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let real_pllsysclk = vco_in * plln / sysclk_div;
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PllResults {
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use_pll: true,
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pllsysclk: Some(real_pllsysclk),
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pll48clk: if pll48clk { Some(real_pll48clk) } else { None },
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plli2sclk: setup_i2s_pll(vco_in, plli2s),
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}
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}
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pub enum McoClock {
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DIV1,
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DIV2,
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DIV3,
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DIV4,
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DIV5,
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}
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impl McoClock {
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fn into_raw(&self) -> Mcopre {
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match self {
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McoClock::DIV1 => Mcopre::DIV1,
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McoClock::DIV2 => Mcopre::DIV2,
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McoClock::DIV3 => Mcopre::DIV3,
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McoClock::DIV4 => Mcopre::DIV4,
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McoClock::DIV5 => Mcopre::DIV5,
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}
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}
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}
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#[derive(Copy, Clone)]
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pub enum Mco1Source {
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Hsi,
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Lse,
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Hse,
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Pll,
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}
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impl Default for Mco1Source {
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fn default() -> Self {
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Self::Hsi
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}
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}
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pub trait McoSource {
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type Raw;
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fn into_raw(&self) -> Self::Raw;
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}
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impl McoSource for Mco1Source {
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type Raw = Mco1;
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fn into_raw(&self) -> Self::Raw {
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match self {
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Mco1Source::Hsi => Mco1::HSI,
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Mco1Source::Lse => Mco1::LSE,
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Mco1Source::Hse => Mco1::HSE,
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Mco1Source::Pll => Mco1::PLL,
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}
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}
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}
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#[derive(Copy, Clone)]
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pub enum Mco2Source {
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SysClk,
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Plli2s,
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Hse,
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Pll,
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}
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impl Default for Mco2Source {
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fn default() -> Self {
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Self::SysClk
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}
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}
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impl McoSource for Mco2Source {
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type Raw = Mco2;
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fn into_raw(&self) -> Self::Raw {
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match self {
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Mco2Source::SysClk => Mco2::SYSCLK,
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Mco2Source::Plli2s => Mco2::PLLI2S,
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Mco2Source::Hse => Mco2::HSE,
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Mco2Source::Pll => Mco2::PLL,
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}
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}
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}
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pub(crate) mod sealed {
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use stm32_metapac::rcc::vals::Mcopre;
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pub trait McoInstance {
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type Source;
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unsafe fn apply_clock_settings(source: Self::Source, prescaler: Mcopre);
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}
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}
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pub trait McoInstance: sealed::McoInstance + 'static {}
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pin_trait!(McoPin, McoInstance);
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impl sealed::McoInstance for peripherals::MCO1 {
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type Source = Mco1;
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unsafe fn apply_clock_settings(source: Self::Source, prescaler: Mcopre) {
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RCC.cfgr().modify(|w| {
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w.set_mco1(source);
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w.set_mco1pre(prescaler);
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});
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match source {
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Mco1::PLL => {
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RCC.cr().modify(|w| w.set_pllon(true));
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while !RCC.cr().read().pllrdy() {}
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}
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Mco1::HSI => {
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RCC.cr().modify(|w| w.set_hsion(true));
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while !RCC.cr().read().hsirdy() {}
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}
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_ => {}
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}
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}
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}
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impl McoInstance for peripherals::MCO1 {}
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impl sealed::McoInstance for peripherals::MCO2 {
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type Source = Mco2;
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unsafe fn apply_clock_settings(source: Self::Source, prescaler: Mcopre) {
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RCC.cfgr().modify(|w| {
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w.set_mco2(source);
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w.set_mco2pre(prescaler);
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});
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match source {
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Mco2::PLL => {
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RCC.cr().modify(|w| w.set_pllon(true));
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while !RCC.cr().read().pllrdy() {}
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}
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#[cfg(not(stm32f410))]
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Mco2::PLLI2S => {
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RCC.cr().modify(|w| w.set_plli2son(true));
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while !RCC.cr().read().plli2srdy() {}
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}
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_ => {}
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}
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}
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}
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impl McoInstance for peripherals::MCO2 {}
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pub struct Mco<'d, T: McoInstance> {
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phantom: PhantomData<&'d mut T>,
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}
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impl<'d, T: McoInstance> Mco<'d, T> {
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pub fn new(
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_peri: impl Peripheral<P = T> + 'd,
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pin: impl Peripheral<P = impl McoPin<T>> + 'd,
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source: impl McoSource<Raw = T::Source>,
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prescaler: McoClock,
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) -> Self {
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into_ref!(pin);
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critical_section::with(|_| unsafe {
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T::apply_clock_settings(source.into_raw(), prescaler.into_raw());
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pin.set_as_af(pin.af_num(), AFType::OutputPushPull);
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pin.set_speed(Speed::VeryHigh);
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});
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Self { phantom: PhantomData }
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}
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}
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unsafe fn flash_setup(sysclk: u32) {
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use crate::pac::flash::vals::Latency;
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// Be conservative with voltage ranges
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const FLASH_LATENCY_STEP: u32 = 30_000_000;
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critical_section::with(|_| {
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FLASH
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.acr()
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.modify(|w| w.set_latency(Latency(((sysclk - 1) / FLASH_LATENCY_STEP) as u8)));
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});
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}
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pub(crate) unsafe fn init(config: Config) {
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crate::peripherals::PWR::enable();
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let pllsrcclk = config.hse.map(|hse| hse.0).unwrap_or(HSI_FREQ.0);
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let sysclk = config.sys_ck.map(|sys| sys.0).unwrap_or(pllsrcclk);
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let sysclk_on_pll = sysclk != pllsrcclk;
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let plls = setup_pll(
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pllsrcclk,
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config.hse.is_some(),
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if sysclk_on_pll { Some(sysclk) } else { None },
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config.plli2s.map(|i2s| i2s.0),
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config.pll48,
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);
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if config.pll48 {
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let freq = unwrap!(plls.pll48clk);
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assert!((max::PLL_48_CLK as i32 - freq as i32).abs() <= max::PLL_48_TOLERANCE as i32);
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}
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let sysclk = if sysclk_on_pll { unwrap!(plls.pllsysclk) } else { sysclk };
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// AHB prescaler
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let hclk = config.hclk.map(|h| h.0).unwrap_or(sysclk);
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let (hpre_bits, hpre_div) = match (sysclk + hclk - 1) / hclk {
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0 => unreachable!(),
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1 => (Hpre::DIV1, 1),
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2 => (Hpre::DIV2, 2),
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3..=5 => (Hpre::DIV4, 4),
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6..=11 => (Hpre::DIV8, 8),
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12..=39 => (Hpre::DIV16, 16),
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40..=95 => (Hpre::DIV64, 64),
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96..=191 => (Hpre::DIV128, 128),
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192..=383 => (Hpre::DIV256, 256),
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_ => (Hpre::DIV512, 512),
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};
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// Calculate real AHB clock
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let hclk = sysclk / hpre_div;
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let pclk1 = config
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.pclk1
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.map(|p| p.0)
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.unwrap_or_else(|| core::cmp::min(max::PCLK1_MAX, hclk));
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let (ppre1_bits, ppre1) = match (hclk + pclk1 - 1) / pclk1 {
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0 => unreachable!(),
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1 => (0b000, 1),
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2 => (0b100, 2),
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3..=5 => (0b101, 4),
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6..=11 => (0b110, 8),
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_ => (0b111, 16),
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};
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let timer_mul1 = if ppre1 == 1 { 1 } else { 2 };
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// Calculate real APB1 clock
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let pclk1 = hclk / ppre1;
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assert!(pclk1 <= max::PCLK1_MAX);
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let pclk2 = config
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.pclk2
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.map(|p| p.0)
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.unwrap_or_else(|| core::cmp::min(max::PCLK2_MAX, hclk));
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let (ppre2_bits, ppre2) = match (hclk + pclk2 - 1) / pclk2 {
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0 => unreachable!(),
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1 => (0b000, 1),
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2 => (0b100, 2),
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3..=5 => (0b101, 4),
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6..=11 => (0b110, 8),
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_ => (0b111, 16),
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};
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let timer_mul2 = if ppre2 == 1 { 1 } else { 2 };
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// Calculate real APB2 clock
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let pclk2 = hclk / ppre2;
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assert!(pclk2 <= max::PCLK2_MAX);
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flash_setup(sysclk);
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if config.hse.is_some() {
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RCC.cr().modify(|w| {
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w.set_hsebyp(config.bypass_hse);
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w.set_hseon(true);
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});
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while !RCC.cr().read().hserdy() {}
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}
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if plls.use_pll {
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RCC.cr().modify(|w| w.set_pllon(true));
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if hclk > max::HCLK_OVERDRIVE_FREQUENCY {
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PWR.cr1().modify(|w| w.set_oden(true));
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while !PWR.csr1().read().odrdy() {}
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PWR.cr1().modify(|w| w.set_odswen(true));
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while !PWR.csr1().read().odswrdy() {}
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}
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while !RCC.cr().read().pllrdy() {}
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}
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#[cfg(not(stm32f410))]
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if plls.plli2sclk.is_some() {
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RCC.cr().modify(|w| w.set_plli2son(true));
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while !RCC.cr().read().plli2srdy() {}
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}
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RCC.cfgr().modify(|w| {
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w.set_ppre2(Ppre(ppre2_bits));
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w.set_ppre1(Ppre(ppre1_bits));
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w.set_hpre(hpre_bits);
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});
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// Wait for the new prescalers to kick in
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// "The clocks are divided with the new prescaler factor from 1 to 16 AHB cycles after write"
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cortex_m::asm::delay(16);
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RCC.cfgr().modify(|w| {
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w.set_sw(if sysclk_on_pll {
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Sw::PLL
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} else if config.hse.is_some() {
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Sw::HSE
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} else {
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Sw::HSI
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})
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});
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set_freqs(Clocks {
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sys: Hertz(sysclk),
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apb1: Hertz(pclk1),
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apb2: Hertz(pclk2),
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apb1_tim: Hertz(pclk1 * timer_mul1),
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apb2_tim: Hertz(pclk2 * timer_mul2),
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ahb1: Hertz(hclk),
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ahb2: Hertz(hclk),
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ahb3: Hertz(hclk),
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pll48: plls.pll48clk.map(Hertz),
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});
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}
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struct PllResults {
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use_pll: bool,
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pllsysclk: Option<u32>,
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pll48clk: Option<u32>,
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#[allow(dead_code)]
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plli2sclk: Option<u32>,
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}
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mod max {
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#[cfg(stm32f401)]
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pub(crate) const SYSCLK_MAX: u32 = 84_000_000;
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#[cfg(any(stm32f405, stm32f407, stm32f415, stm32f417,))]
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pub(crate) const SYSCLK_MAX: u32 = 168_000_000;
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#[cfg(any(stm32f410, stm32f411, stm32f412, stm32f413, stm32f423,))]
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pub(crate) const SYSCLK_MAX: u32 = 100_000_000;
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#[cfg(any(stm32f427, stm32f429, stm32f437, stm32f439, stm32f446, stm32f469, stm32f479,))]
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pub(crate) const SYSCLK_MAX: u32 = 180_000_000;
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pub(crate) const HCLK_OVERDRIVE_FREQUENCY: u32 = 168_000_000;
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pub(crate) const PCLK1_MAX: u32 = PCLK2_MAX / 2;
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#[cfg(any(stm32f401, stm32f410, stm32f411, stm32f412, stm32f413, stm32f423,))]
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pub(crate) const PCLK2_MAX: u32 = SYSCLK_MAX;
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#[cfg(not(any(stm32f401, stm32f410, stm32f411, stm32f412, stm32f413, stm32f423,)))]
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pub(crate) const PCLK2_MAX: u32 = SYSCLK_MAX / 2;
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pub(crate) const PLL_48_CLK: u32 = 48_000_000;
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pub(crate) const PLL_48_TOLERANCE: u32 = 120_000;
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}
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