79 lines
2.7 KiB
Rust
79 lines
2.7 KiB
Rust
use embedded_hal_async::spi::SpiDevice;
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use crate::device::RegisterBlock;
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use crate::spi::{Address, SpiInterface};
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pub const MODE: Address = (RegisterBlock::Socket0, 0x00);
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pub const COMMAND: Address = (RegisterBlock::Socket0, 0x01);
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pub const RXBUF_SIZE: Address = (RegisterBlock::Socket0, 0x1E);
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pub const TXBUF_SIZE: Address = (RegisterBlock::Socket0, 0x1F);
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pub const TX_FREE_SIZE: Address = (RegisterBlock::Socket0, 0x20);
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pub const TX_DATA_WRITE_PTR: Address = (RegisterBlock::Socket0, 0x24);
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pub const RECVD_SIZE: Address = (RegisterBlock::Socket0, 0x26);
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pub const RX_DATA_READ_PTR: Address = (RegisterBlock::Socket0, 0x28);
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pub const SOCKET_INTR_MASK: Address = (RegisterBlock::Socket0, 0x2C);
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pub const INTR: Address = (RegisterBlock::Socket0, 0x02);
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#[repr(u8)]
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pub enum Command {
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Open = 0x01,
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Send = 0x20,
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Receive = 0x40,
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}
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#[repr(u8)]
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pub enum Interrupt {
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Receive = 0b00100_u8,
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}
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pub async fn reset_interrupt<SPI: SpiDevice>(bus: &mut SpiInterface<SPI>, code: Interrupt) -> Result<(), SPI::Error> {
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let data = [code as u8];
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bus.write_frame(INTR, &data).await
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}
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pub async fn get_tx_write_ptr<SPI: SpiDevice>(bus: &mut SpiInterface<SPI>) -> Result<u16, SPI::Error> {
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let mut data = [0u8; 2];
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bus.read_frame(TX_DATA_WRITE_PTR, &mut data).await?;
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Ok(u16::from_be_bytes(data))
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}
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pub async fn set_tx_write_ptr<SPI: SpiDevice>(bus: &mut SpiInterface<SPI>, ptr: u16) -> Result<(), SPI::Error> {
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let data = ptr.to_be_bytes();
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bus.write_frame(TX_DATA_WRITE_PTR, &data).await
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}
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pub async fn get_rx_read_ptr<SPI: SpiDevice>(bus: &mut SpiInterface<SPI>) -> Result<u16, SPI::Error> {
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let mut data = [0u8; 2];
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bus.read_frame(RX_DATA_READ_PTR, &mut data).await?;
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Ok(u16::from_be_bytes(data))
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}
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pub async fn set_rx_read_ptr<SPI: SpiDevice>(bus: &mut SpiInterface<SPI>, ptr: u16) -> Result<(), SPI::Error> {
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let data = ptr.to_be_bytes();
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bus.write_frame(RX_DATA_READ_PTR, &data).await
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}
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pub async fn command<SPI: SpiDevice>(bus: &mut SpiInterface<SPI>, command: Command) -> Result<(), SPI::Error> {
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let data = [command as u8];
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bus.write_frame(COMMAND, &data).await
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}
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pub async fn get_rx_size<SPI: SpiDevice>(bus: &mut SpiInterface<SPI>) -> Result<u16, SPI::Error> {
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loop {
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// Wait until two sequential reads are equal
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let mut res0 = [0u8; 2];
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bus.read_frame(RECVD_SIZE, &mut res0).await?;
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let mut res1 = [0u8; 2];
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bus.read_frame(RECVD_SIZE, &mut res1).await?;
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if res0 == res1 {
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break Ok(u16::from_be_bytes(res0));
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}
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}
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}
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pub async fn get_tx_free_size<SPI: SpiDevice>(bus: &mut SpiInterface<SPI>) -> Result<u16, SPI::Error> {
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let mut data = [0; 2];
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bus.read_frame(TX_FREE_SIZE, &mut data).await?;
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Ok(u16::from_be_bytes(data))
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}
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