344 lines
11 KiB
Rust
344 lines
11 KiB
Rust
use crate::pac::flash::vals::Latency;
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use crate::pac::rcc::vals::{Hpre, Pllmul, Pllsrc, Ppre, Prediv, Sw, Usbpre};
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use crate::pac::{FLASH, RCC};
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use crate::rcc::{set_freqs, Clocks};
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use crate::time::Hertz;
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/// HSI speed
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pub const HSI_FREQ: Hertz = Hertz(8_000_000);
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/// LSI speed
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pub const LSI_FREQ: Hertz = Hertz(40_000);
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/// Clocks configutation
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#[non_exhaustive]
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#[derive(Default)]
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pub struct Config {
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/// Frequency of HSE oscillator
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/// 4MHz to 32MHz
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pub hse: Option<Hertz>,
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/// Bypass HSE for an external clock
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pub bypass_hse: bool,
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/// Frequency of the System Clock
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pub sysclk: Option<Hertz>,
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/// Frequency of AHB bus
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pub hclk: Option<Hertz>,
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/// Frequency of APB1 bus
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/// - Max frequency 36MHz
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pub pclk1: Option<Hertz>,
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/// Frequency of APB2 bus
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/// - Max frequency with HSE is 72MHz
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/// - Max frequency without HSE is 64MHz
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pub pclk2: Option<Hertz>,
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/// USB clock setup
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/// It is valid only when,
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/// - HSE is enabled,
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/// - The System clock frequency is either 48MHz or 72MHz
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/// - APB1 clock has a minimum frequency of 10MHz
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pub pll48: bool,
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}
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// Information required to setup the PLL clock
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struct PllConfig {
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pll_src: Pllsrc,
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pll_mul: Pllmul,
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pll_div: Option<Prediv>,
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}
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/// Initialize and Set the clock frequencies
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pub(crate) unsafe fn init(config: Config) {
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// Calculate the real System clock, and PLL configuration if applicable
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let (Hertz(sysclk), pll_config) = get_sysclk(&config);
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assert!(sysclk <= 72_000_000);
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// Calculate real AHB clock
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let hclk = config.hclk.map(|h| h.0).unwrap_or(sysclk);
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let (hpre_bits, hpre_div) = match sysclk / hclk {
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0 => unreachable!(),
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1 => (Hpre::DIV1, 1),
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2 => (Hpre::DIV2, 2),
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3..=5 => (Hpre::DIV4, 4),
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6..=11 => (Hpre::DIV8, 8),
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12..=39 => (Hpre::DIV16, 16),
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40..=95 => (Hpre::DIV64, 64),
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96..=191 => (Hpre::DIV128, 128),
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192..=383 => (Hpre::DIV256, 256),
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_ => (Hpre::DIV512, 512),
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};
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let hclk = sysclk / hpre_div;
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assert!(hclk <= 72_000_000);
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// Calculate real APB1 clock
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let pclk1 = config.pclk1.map(|p| p.0).unwrap_or(hclk);
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let (ppre1_bits, ppre1) = match hclk / pclk1 {
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0 => unreachable!(),
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1 => (Ppre::DIV1, 1),
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2 => (Ppre::DIV2, 2),
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3..=5 => (Ppre::DIV4, 4),
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6..=11 => (Ppre::DIV8, 8),
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_ => (Ppre::DIV16, 16),
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};
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let timer_mul1 = if ppre1 == 1 { 1 } else { 2 };
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let pclk1 = hclk / ppre1;
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assert!(pclk1 <= 36_000_000);
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// Calculate real APB2 clock
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let pclk2 = config.pclk2.map(|p| p.0).unwrap_or(hclk);
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let (ppre2_bits, ppre2) = match hclk / pclk2 {
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0 => unreachable!(),
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1 => (Ppre::DIV1, 1),
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2 => (Ppre::DIV2, 2),
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3..=5 => (Ppre::DIV4, 4),
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6..=11 => (Ppre::DIV8, 8),
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_ => (Ppre::DIV16, 16),
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};
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let timer_mul2 = if ppre2 == 1 { 1 } else { 2 };
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let pclk2 = hclk / ppre2;
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assert!(pclk2 <= 72_000_000);
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// Set latency based on HCLK frquency
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// RM0316: "The prefetch buffer must be kept on when using a prescaler
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// different from 1 on the AHB clock.", "Half-cycle access cannot be
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// used when there is a prescaler different from 1 on the AHB clock"
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FLASH.acr().modify(|w| {
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w.set_latency(if hclk <= 24_000_000 {
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Latency::WS0
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} else if hclk <= 48_000_000 {
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Latency::WS1
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} else {
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Latency::WS2
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});
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if hpre_div != 1 {
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w.set_hlfcya(false);
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w.set_prftbe(true);
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}
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});
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// Enable HSE
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// RM0316: "Bits 31:26 Reserved, must be kept at reset value."
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if config.hse.is_some() {
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RCC.cr().modify(|w| {
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w.set_hsebyp(config.bypass_hse);
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// We turn on clock security to switch to HSI when HSE fails
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w.set_csson(true);
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w.set_hseon(true);
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});
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while !RCC.cr().read().hserdy() {}
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}
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// Enable PLL
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// RM0316: "Reserved, must be kept at reset value."
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if let Some(ref pll_config) = pll_config {
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RCC.cfgr().modify(|w| {
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w.set_pllmul(pll_config.pll_mul);
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w.set_pllsrc(pll_config.pll_src);
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});
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if let Some(pll_div) = pll_config.pll_div {
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RCC.cfgr2().modify(|w| w.set_prediv(pll_div));
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}
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RCC.cr().modify(|w| w.set_pllon(true));
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while !RCC.cr().read().pllrdy() {}
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}
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// CFGR has been written before (PLL) don't overwrite these settings
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if config.pll48 {
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let usb_pre = get_usb_pre(&config, sysclk, pclk1, &pll_config);
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RCC.cfgr().modify(|w| {
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w.set_usbpre(usb_pre);
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});
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}
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// Set prescalers
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// CFGR has been written before (PLL, PLL48) don't overwrite these settings
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RCC.cfgr().modify(|w| {
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w.set_ppre2(ppre2_bits);
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w.set_ppre1(ppre1_bits);
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w.set_hpre(hpre_bits);
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});
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// Wait for the new prescalers to kick in
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// "The clocks are divided with the new prescaler factor from
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// 1 to 16 AHB cycles after write"
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cortex_m::asm::delay(16);
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// CFGR has been written before (PLL, PLL48, clock divider) don't overwrite these settings
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RCC.cfgr().modify(|w| {
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w.set_sw(match (pll_config, config.hse) {
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(Some(_), _) => Sw::PLL,
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(None, Some(_)) => Sw::HSE,
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(None, None) => Sw::HSI,
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})
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});
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set_freqs(Clocks {
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sys: Hertz(sysclk),
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apb1: Hertz(pclk1),
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apb2: Hertz(pclk2),
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apb1_tim: Hertz(pclk1 * timer_mul1),
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apb2_tim: Hertz(pclk2 * timer_mul2),
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ahb1: Hertz(hclk),
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});
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}
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#[inline]
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fn get_sysclk(config: &Config) -> (Hertz, Option<PllConfig>) {
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match (config.sysclk, config.hse) {
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(Some(sysclk), Some(hse)) if sysclk == hse => (hse, None),
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(Some(sysclk), None) if sysclk == HSI_FREQ => (HSI_FREQ, None),
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// If the user selected System clock is different from HSI or HSE
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// we will have to setup PLL clock source
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(Some(sysclk), _) => {
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let (sysclk, pll_config) = calc_pll(config, sysclk);
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(sysclk, Some(pll_config))
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}
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(None, Some(hse)) => (hse, None),
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(None, None) => (HSI_FREQ, None),
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}
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}
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#[inline]
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fn calc_pll(config: &Config, Hertz(sysclk): Hertz) -> (Hertz, PllConfig) {
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// Calculates the Multiplier and the Divisor to arrive at
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// the required System clock from PLL source frequency
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let get_mul_div = |sysclk, pllsrcclk| {
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let common_div = gcd(sysclk, pllsrcclk);
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let mut multiplier = sysclk / common_div;
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let mut divisor = pllsrcclk / common_div;
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// Minimum PLL multiplier is two
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if multiplier == 1 {
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multiplier *= 2;
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divisor *= 2;
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}
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assert!(multiplier <= 16);
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assert!(divisor <= 16);
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(multiplier, divisor)
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};
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// Based on the source of Pll, we calculate the actual system clock
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// frequency, PLL's source identifier, multiplier and divisor
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let (act_sysclk, pll_src, pll_mul, pll_div) = match config.hse {
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Some(Hertz(hse)) => {
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let (multiplier, divisor) = get_mul_div(sysclk, hse);
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(
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Hertz((hse / divisor) * multiplier),
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Pllsrc::HSE_DIV_PREDIV,
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into_pll_mul(multiplier),
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Some(into_pre_div(divisor)),
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)
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}
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None => {
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cfg_if::cfg_if! {
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// For some chips PREDIV is always two, and cannot be changed
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if #[cfg(any(
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stm32f302xd, stm32f302xe, stm32f303xd,
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stm32f303xe, stm32f398xe
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))] {
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let (multiplier, divisor) = get_mul_div(sysclk, HSI_FREQ.0);
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(
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Hertz((HSI_FREQ.0 / divisor) * multiplier),
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Pllsrc::HSI_DIV_PREDIV,
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into_pll_mul(multiplier),
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Some(into_pre_div(divisor)),
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)
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} else {
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let pllsrcclk = HSI_FREQ.0 / 2;
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let multiplier = sysclk / pllsrcclk;
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assert!(multiplier <= 16);
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(
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Hertz(pllsrcclk * multiplier),
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Pllsrc::HSI_DIV2,
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into_pll_mul(multiplier),
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None,
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)
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}
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}
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}
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};
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(
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act_sysclk,
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PllConfig {
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pll_src,
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pll_mul,
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pll_div,
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},
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)
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}
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#[inline]
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fn get_usb_pre(config: &Config, sysclk: u32, pclk1: u32, pll_config: &Option<PllConfig>) -> Usbpre {
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cfg_if::cfg_if! {
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// Some chips do not have USB
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if #[cfg(any(stm32f301, stm32f318, stm32f334))] {
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panic!("USB clock not supported by the chip");
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} else {
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let usb_ok = config.hse.is_some() && pll_config.is_some() && (pclk1 >= 10_000_000);
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match (usb_ok, sysclk) {
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(true, 72_000_000) => Usbpre::DIV1_5,
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(true, 48_000_000) => Usbpre::DIV1,
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_ => panic!(
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"USB clock is only valid if the PLL output frequency is either 48MHz or 72MHz"
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),
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}
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}
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}
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}
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// This function assumes cases when multiplier is one and it
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// being greater than 16 is made impossible
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#[inline]
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fn into_pll_mul(multiplier: u32) -> Pllmul {
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match multiplier {
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2 => Pllmul::MUL2,
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3 => Pllmul::MUL3,
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4 => Pllmul::MUL4,
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5 => Pllmul::MUL5,
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6 => Pllmul::MUL6,
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7 => Pllmul::MUL7,
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8 => Pllmul::MUL8,
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9 => Pllmul::MUL9,
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10 => Pllmul::MUL10,
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11 => Pllmul::MUL11,
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12 => Pllmul::MUL12,
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13 => Pllmul::MUL13,
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14 => Pllmul::MUL14,
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15 => Pllmul::MUL15,
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16 => Pllmul::MUL16,
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_ => unreachable!(),
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}
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}
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// This function assumes the incoming divisor cannot be greater
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// than 16
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#[inline]
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fn into_pre_div(divisor: u32) -> Prediv {
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match divisor {
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1 => Prediv::DIV1,
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2 => Prediv::DIV2,
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3 => Prediv::DIV3,
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4 => Prediv::DIV4,
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5 => Prediv::DIV5,
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6 => Prediv::DIV6,
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7 => Prediv::DIV7,
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8 => Prediv::DIV8,
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9 => Prediv::DIV9,
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10 => Prediv::DIV10,
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11 => Prediv::DIV11,
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12 => Prediv::DIV12,
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13 => Prediv::DIV13,
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14 => Prediv::DIV14,
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15 => Prediv::DIV15,
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16 => Prediv::DIV16,
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_ => unreachable!(),
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}
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}
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// Determine GCD using Euclidean algorithm
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#[inline]
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fn gcd(mut a: u32, mut b: u32) -> u32 {
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while b != 0 {
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let r = a % b;
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a = b;
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b = r;
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}
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a
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}
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