345 lines
11 KiB
Rust
345 lines
11 KiB
Rust
#![macro_use]
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pub mod enums;
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use embassy_hal_common::{into_ref, PeripheralRef};
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use enums::*;
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use crate::dma::Transfer;
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use crate::gpio::sealed::AFType;
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use crate::gpio::AnyPin;
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use crate::pac::quadspi::Quadspi as Regs;
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use crate::rcc::RccPeripheral;
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use crate::{peripherals, Peripheral};
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pub struct TransferConfig {
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/// Instraction width (IMODE)
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pub iwidth: QspiWidth,
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/// Address width (ADMODE)
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pub awidth: QspiWidth,
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/// Data width (DMODE)
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pub dwidth: QspiWidth,
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/// Instruction Id
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pub instruction: u8,
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/// Flash memory address
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pub address: Option<u32>,
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/// Number of dummy cycles (DCYC)
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pub dummy: DummyCycles,
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/// Length of data
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pub data_len: Option<usize>,
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}
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impl Default for TransferConfig {
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fn default() -> Self {
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Self {
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iwidth: QspiWidth::NONE,
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awidth: QspiWidth::NONE,
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dwidth: QspiWidth::NONE,
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instruction: 0,
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address: None,
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dummy: DummyCycles::_0,
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data_len: None,
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}
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}
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}
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pub struct Config {
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/// Flash memory size representend as 2^[0-32], as reasonable minimum 1KiB(9) was chosen.
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/// If you need other value the whose predefined use `Other` variant.
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pub memory_size: MemorySize,
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/// Address size (8/16/24/32-bit)
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pub address_size: AddressSize,
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/// Scalar factor for generating CLK [0-255]
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pub prescaler: u8,
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/// Number of bytes to trigger FIFO threshold flag.
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pub fifo_threshold: FIFOThresholdLevel,
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/// Minimum number of cycles that chip select must be high between issued commands
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pub cs_high_time: ChipSelectHightTime,
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}
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impl Default for Config {
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fn default() -> Self {
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Self {
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memory_size: MemorySize::Other(0),
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address_size: AddressSize::_24bit,
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prescaler: 128,
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fifo_threshold: FIFOThresholdLevel::_17Bytes,
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cs_high_time: ChipSelectHightTime::_5Cycle,
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}
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}
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}
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#[allow(dead_code)]
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pub struct Qspi<'d, T: Instance, Dma> {
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_peri: PeripheralRef<'d, T>,
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sck: Option<PeripheralRef<'d, AnyPin>>,
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d0: Option<PeripheralRef<'d, AnyPin>>,
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d1: Option<PeripheralRef<'d, AnyPin>>,
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d2: Option<PeripheralRef<'d, AnyPin>>,
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d3: Option<PeripheralRef<'d, AnyPin>>,
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nss: Option<PeripheralRef<'d, AnyPin>>,
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dma: PeripheralRef<'d, Dma>,
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config: Config,
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}
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impl<'d, T: Instance, Dma> Qspi<'d, T, Dma> {
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pub fn new(
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peri: impl Peripheral<P = T> + 'd,
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d0: impl Peripheral<P = impl D0Pin<T>> + 'd,
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d1: impl Peripheral<P = impl D1Pin<T>> + 'd,
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d2: impl Peripheral<P = impl D2Pin<T>> + 'd,
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d3: impl Peripheral<P = impl D3Pin<T>> + 'd,
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sck: impl Peripheral<P = impl SckPin<T>> + 'd,
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nss: impl Peripheral<P = impl NSSPin<T>> + 'd,
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dma: impl Peripheral<P = Dma> + 'd,
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config: Config,
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) -> Self {
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into_ref!(peri, d0, d1, d2, d3, sck, nss);
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unsafe {
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sck.set_as_af(sck.af_num(), AFType::OutputPushPull);
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sck.set_speed(crate::gpio::Speed::VeryHigh);
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nss.set_as_af(nss.af_num(), AFType::OutputPushPull);
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nss.set_speed(crate::gpio::Speed::VeryHigh);
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d0.set_as_af(d0.af_num(), AFType::OutputPushPull);
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d0.set_speed(crate::gpio::Speed::VeryHigh);
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d1.set_as_af(d1.af_num(), AFType::OutputPushPull);
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d1.set_speed(crate::gpio::Speed::VeryHigh);
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d2.set_as_af(d2.af_num(), AFType::OutputPushPull);
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d2.set_speed(crate::gpio::Speed::VeryHigh);
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d3.set_as_af(d3.af_num(), AFType::OutputPushPull);
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d3.set_speed(crate::gpio::Speed::VeryHigh);
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}
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Self::new_inner(
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peri,
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Some(d0.map_into()),
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Some(d1.map_into()),
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Some(d2.map_into()),
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Some(d3.map_into()),
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Some(sck.map_into()),
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Some(nss.map_into()),
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dma,
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config,
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)
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}
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fn new_inner(
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peri: impl Peripheral<P = T> + 'd,
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d0: Option<PeripheralRef<'d, AnyPin>>,
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d1: Option<PeripheralRef<'d, AnyPin>>,
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d2: Option<PeripheralRef<'d, AnyPin>>,
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d3: Option<PeripheralRef<'d, AnyPin>>,
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sck: Option<PeripheralRef<'d, AnyPin>>,
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nss: Option<PeripheralRef<'d, AnyPin>>,
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dma: impl Peripheral<P = Dma> + 'd,
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config: Config,
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) -> Self {
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into_ref!(peri, dma);
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T::enable();
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unsafe {
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T::REGS.cr().write(|w| w.set_fthres(config.fifo_threshold.into()));
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while T::REGS.sr().read().busy() {}
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T::REGS.cr().write(|w| {
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w.set_prescaler(config.prescaler);
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w.set_en(true);
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});
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T::REGS.dcr().write(|w| {
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w.set_fsize(config.memory_size.into());
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w.set_csht(config.cs_high_time.into());
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w.set_ckmode(false);
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});
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}
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Self {
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_peri: peri,
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sck,
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d0,
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d1,
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d2,
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d3,
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nss,
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dma,
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config,
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}
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}
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pub fn command(&mut self, transaction: TransferConfig) {
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unsafe {
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T::REGS.cr().modify(|v| v.set_dmaen(false));
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self.setup_transaction(QspiMode::IndirectWrite, &transaction);
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while !T::REGS.sr().read().tcf() {}
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T::REGS.fcr().modify(|v| v.set_ctcf(true));
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}
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}
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pub fn blocking_read(&mut self, buf: &mut [u8], transaction: TransferConfig) {
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unsafe {
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T::REGS.cr().modify(|v| v.set_dmaen(false));
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self.setup_transaction(QspiMode::IndirectWrite, &transaction);
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if let Some(len) = transaction.data_len {
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let current_ar = T::REGS.ar().read().address();
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T::REGS.ccr().modify(|v| {
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v.set_fmode(QspiMode::IndirectRead.into());
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});
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T::REGS.ar().write(|v| {
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v.set_address(current_ar);
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});
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for idx in 0..len {
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while !T::REGS.sr().read().tcf() && !T::REGS.sr().read().ftf() {}
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buf[idx] = *(T::REGS.dr().ptr() as *mut u8);
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}
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}
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while !T::REGS.sr().read().tcf() {}
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T::REGS.fcr().modify(|v| v.set_ctcf(true));
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}
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}
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pub fn blocking_write(&mut self, buf: &[u8], transaction: TransferConfig) {
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unsafe {
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T::REGS.cr().modify(|v| v.set_dmaen(false));
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self.setup_transaction(QspiMode::IndirectWrite, &transaction);
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if let Some(len) = transaction.data_len {
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T::REGS.ccr().modify(|v| {
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v.set_fmode(QspiMode::IndirectWrite.into());
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});
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for idx in 0..len {
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while !T::REGS.sr().read().ftf() {}
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*(T::REGS.dr().ptr() as *mut u8) = buf[idx];
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}
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}
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while !T::REGS.sr().read().tcf() {}
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T::REGS.fcr().modify(|v| v.set_ctcf(true));
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}
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}
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pub fn blocking_read_dma(&mut self, buf: &mut [u8], transaction: TransferConfig)
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where
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Dma: QuadDma<T>,
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{
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unsafe {
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self.setup_transaction(QspiMode::IndirectWrite, &transaction);
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T::REGS.ccr().modify(|v| {
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v.set_fmode(QspiMode::IndirectRead.into());
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});
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let current_ar = T::REGS.ar().read().address();
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T::REGS.ar().write(|v| {
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v.set_address(current_ar);
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});
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let request = self.dma.request();
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let transfer = Transfer::new_read(
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&mut self.dma,
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request,
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T::REGS.dr().ptr() as *mut u8,
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buf,
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Default::default(),
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);
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T::REGS.cr().modify(|v| v.set_dmaen(true));
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transfer.blocking_wait();
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}
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}
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pub fn blocking_write_dma(&mut self, buf: &[u8], transaction: TransferConfig)
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where
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Dma: QuadDma<T>,
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{
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unsafe {
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self.setup_transaction(QspiMode::IndirectWrite, &transaction);
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T::REGS.ccr().modify(|v| {
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v.set_fmode(QspiMode::IndirectWrite.into());
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});
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let request = self.dma.request();
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let transfer = Transfer::new_write(
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&mut self.dma,
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request,
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buf,
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T::REGS.dr().ptr() as *mut u8,
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Default::default(),
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);
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T::REGS.cr().modify(|v| v.set_dmaen(true));
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transfer.blocking_wait();
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}
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}
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fn setup_transaction(&mut self, fmode: QspiMode, transaction: &TransferConfig) {
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unsafe {
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T::REGS.fcr().modify(|v| {
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v.set_csmf(true);
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v.set_ctcf(true);
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v.set_ctef(true);
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v.set_ctof(true);
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});
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while T::REGS.sr().read().busy() {}
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if let Some(len) = transaction.data_len {
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T::REGS.dlr().write(|v| v.set_dl(len as u32 - 1));
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}
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T::REGS.ccr().write(|v| {
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v.set_fmode(fmode.into());
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v.set_imode(transaction.iwidth.into());
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v.set_instruction(transaction.instruction);
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v.set_admode(transaction.awidth.into());
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v.set_adsize(self.config.address_size.into());
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v.set_dmode(transaction.dwidth.into());
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v.set_abmode(QspiWidth::NONE.into());
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v.set_dcyc(transaction.dummy.into());
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});
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if let Some(addr) = transaction.address {
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T::REGS.ar().write(|v| {
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v.set_address(addr);
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});
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}
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}
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}
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}
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pub(crate) mod sealed {
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use super::*;
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pub trait Instance {
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const REGS: Regs;
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}
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}
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pub trait Instance: Peripheral<P = Self> + sealed::Instance + RccPeripheral {}
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pin_trait!(SckPin, Instance);
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pin_trait!(D0Pin, Instance);
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pin_trait!(D1Pin, Instance);
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pin_trait!(D2Pin, Instance);
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pin_trait!(D3Pin, Instance);
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pin_trait!(NSSPin, Instance);
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dma_trait!(QuadDma, Instance);
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foreach_peripheral!(
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(quadspi, $inst:ident) => {
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impl sealed::Instance for peripherals::$inst {
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const REGS: Regs = crate::pac::$inst;
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}
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impl Instance for peripherals::$inst {}
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};
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);
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