514 lines
12 KiB
Rust
514 lines
12 KiB
Rust
#![macro_use]
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use core::convert::Infallible;
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use core::hint::unreachable_unchecked;
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use core::marker::PhantomData;
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use embassy::util::Unborrow;
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use embassy_hal_common::{unborrow, unsafe_impl_unborrow};
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use embedded_hal::digital::v2::{InputPin, OutputPin, StatefulOutputPin};
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use gpio::pin_cnf::DRIVE_A;
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use crate::pac;
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use crate::pac::p0 as gpio;
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use self::sealed::Pin as _;
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/// A GPIO port with up to 32 pins.
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#[derive(Debug, Eq, PartialEq)]
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pub enum Port {
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/// Port 0, available on nRF9160 and all nRF52 and nRF51 MCUs.
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Port0,
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/// Port 1, only available on some nRF52 MCUs.
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#[cfg(any(feature = "nrf52833", feature = "nrf52840"))]
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Port1,
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}
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/// Pull setting for an input.
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#[derive(Debug, Eq, PartialEq)]
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#[cfg_attr(feature = "defmt", derive(defmt::Format))]
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pub enum Pull {
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None,
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Up,
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Down,
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}
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/// GPIO input driver.
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pub struct Input<'d, T: Pin> {
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pub(crate) pin: T,
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phantom: PhantomData<&'d mut T>,
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}
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impl<'d, T: Pin> Input<'d, T> {
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pub fn new(pin: impl Unborrow<Target = T> + 'd, pull: Pull) -> Self {
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unborrow!(pin);
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init_input(&pin, pull);
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Self {
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pin,
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phantom: PhantomData,
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}
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}
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}
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impl<'d, T: Pin> Drop for Input<'d, T> {
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fn drop(&mut self) {
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self.pin.conf().reset();
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}
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}
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impl<'d, T: Pin> InputPin for Input<'d, T> {
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type Error = Infallible;
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fn is_high(&self) -> Result<bool, Self::Error> {
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self.is_low().map(|v| !v)
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}
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fn is_low(&self) -> Result<bool, Self::Error> {
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Ok(self.pin.block().in_.read().bits() & (1 << self.pin.pin()) == 0)
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}
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}
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/// Digital input or output level.
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#[derive(Debug, Eq, PartialEq)]
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#[cfg_attr(feature = "defmt", derive(defmt::Format))]
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pub enum Level {
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Low,
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High,
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}
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// These numbers match DRIVE_A exactly so hopefully the compiler will unify them.
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#[derive(Clone, Copy, Debug, PartialEq)]
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#[cfg_attr(feature = "defmt", derive(defmt::Format))]
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#[repr(u8)]
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pub enum OutputDrive {
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/// Standard '0', standard '1'
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Standard = 0,
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/// High drive '0', standard '1'
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HighDrive0Standard1 = 1,
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/// Standard '0', high drive '1'
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Standard0HighDrive1 = 2,
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/// High drive '0', high 'drive '1'
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HighDrive = 3,
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/// Disconnect '0' standard '1' (normally used for wired-or connections)
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Disconnect0Standard1 = 4,
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/// Disconnect '0', high drive '1' (normally used for wired-or connections)
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Disconnect0HighDrive1 = 5,
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/// Standard '0'. disconnect '1' (also known as "open drain", normally used for wired-and connections)
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Standard0Disconnect1 = 6,
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/// High drive '0', disconnect '1' (also known as "open drain", normally used for wired-and connections)
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HighDrive0Disconnect1 = 7,
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}
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/// GPIO output driver.
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pub struct Output<'d, T: Pin> {
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pub(crate) pin: T,
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phantom: PhantomData<&'d mut T>,
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}
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impl<'d, T: Pin> Output<'d, T> {
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pub fn new(
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pin: impl Unborrow<Target = T> + 'd,
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initial_output: Level,
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drive: OutputDrive,
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) -> Self {
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unborrow!(pin);
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match initial_output {
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Level::High => pin.set_high(),
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Level::Low => pin.set_low(),
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}
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init_output(&pin, drive);
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Self {
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pin,
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phantom: PhantomData,
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}
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}
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}
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impl<'d, T: Pin> Drop for Output<'d, T> {
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fn drop(&mut self) {
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self.pin.conf().reset();
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}
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}
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impl<'d, T: Pin> OutputPin for Output<'d, T> {
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type Error = Infallible;
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/// Set the output as high.
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fn set_high(&mut self) -> Result<(), Self::Error> {
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unsafe {
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self.pin
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.block()
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.outset
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.write(|w| w.bits(1u32 << self.pin.pin()));
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}
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Ok(())
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}
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/// Set the output as low.
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fn set_low(&mut self) -> Result<(), Self::Error> {
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unsafe {
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self.pin
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.block()
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.outclr
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.write(|w| w.bits(1u32 << self.pin.pin()));
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}
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Ok(())
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}
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}
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impl<'d, T: Pin> StatefulOutputPin for Output<'d, T> {
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/// Is the output pin set as high?
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fn is_set_high(&self) -> Result<bool, Self::Error> {
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self.is_set_low().map(|v| !v)
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}
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/// Is the output pin set as low?
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fn is_set_low(&self) -> Result<bool, Self::Error> {
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Ok(self.pin.block().out.read().bits() & (1 << self.pin.pin()) == 0)
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}
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}
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/// GPIO flexible pin.
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///
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/// This pin can either be a disconnected, input, or output pin. The level register bit will remain
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/// set while not in output mode, so the pin's level will be 'remembered' when it is not in output
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/// mode.
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pub struct FlexPin<'d, T: Pin> {
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pub(crate) pin: T,
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phantom: PhantomData<&'d mut T>,
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}
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impl<'d, T: Pin> FlexPin<'d, T> {
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/// Wrap the pin in a `FlexPin`.
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///
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/// The pin remains disconnected. The initial output level is unspecified, but can be changed
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/// before the pin is put into output mode.
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pub fn new(pin: impl Unborrow<Target = T> + 'd) -> Self {
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unborrow!(pin);
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// Pin will be in disconnected state.
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Self {
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pin,
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phantom: PhantomData,
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}
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}
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/// Put the pin into input mode.
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pub fn set_as_input(&mut self, pull: Pull) {
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init_input(&self.pin, pull);
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}
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/// Put the pin into output mode.
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///
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/// The pin level will be whatever was set before (or low by default). If you want it to begin
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/// at a specific level, call `set_high`/`set_low` on the pin first.
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pub fn set_as_output(&mut self, drive: OutputDrive) {
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init_output(&self.pin, drive);
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}
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/// Put the pin into disconnected mode.
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pub fn set_as_disconnected(&mut self) {
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self.pin.conf().reset();
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}
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}
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impl<'d, T: Pin> Drop for FlexPin<'d, T> {
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fn drop(&mut self) {
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self.pin.conf().reset();
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}
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}
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/// Implement [`InputPin`] for [`FlexPin`];
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///
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/// If the pin is not in input mode the result is unspecified.
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impl<'d, T: Pin> InputPin for FlexPin<'d, T> {
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type Error = Infallible;
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fn is_high(&self) -> Result<bool, Self::Error> {
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self.is_low().map(|v| !v)
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}
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fn is_low(&self) -> Result<bool, Self::Error> {
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Ok(self.pin.block().in_.read().bits() & (1 << self.pin.pin()) == 0)
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}
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}
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impl<'d, T: Pin> OutputPin for FlexPin<'d, T> {
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type Error = Infallible;
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/// Set the output as high.
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fn set_high(&mut self) -> Result<(), Self::Error> {
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unsafe {
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self.pin
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.block()
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.outset
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.write(|w| w.bits(1u32 << self.pin.pin()));
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}
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Ok(())
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}
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/// Set the output as low.
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fn set_low(&mut self) -> Result<(), Self::Error> {
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unsafe {
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self.pin
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.block()
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.outclr
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.write(|w| w.bits(1u32 << self.pin.pin()));
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}
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Ok(())
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}
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}
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impl<'d, T: Pin> StatefulOutputPin for FlexPin<'d, T> {
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/// Is the output pin set as high?
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fn is_set_high(&self) -> Result<bool, Self::Error> {
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self.is_set_low().map(|v| !v)
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}
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/// Is the output pin set as low?
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fn is_set_low(&self) -> Result<bool, Self::Error> {
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Ok(self.pin.block().out.read().bits() & (1 << self.pin.pin()) == 0)
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}
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}
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pub(crate) mod sealed {
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use super::*;
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pub trait Pin {
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fn pin_port(&self) -> u8;
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#[inline]
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fn _pin(&self) -> u8 {
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#[cfg(any(feature = "nrf52833", feature = "nrf52840"))]
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{
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self.pin_port() % 32
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}
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#[cfg(not(any(feature = "nrf52833", feature = "nrf52840")))]
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{
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self.pin_port()
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}
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}
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#[inline]
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fn block(&self) -> &gpio::RegisterBlock {
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unsafe {
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match self.pin_port() / 32 {
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0 => &*pac::P0::ptr(),
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#[cfg(any(feature = "nrf52833", feature = "nrf52840"))]
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1 => &*pac::P1::ptr(),
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_ => unreachable_unchecked(),
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}
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}
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}
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#[inline]
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fn conf(&self) -> &gpio::PIN_CNF {
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&self.block().pin_cnf[self._pin() as usize]
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}
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/// Set the output as high.
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#[inline]
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fn set_high(&self) {
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unsafe {
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self.block().outset.write(|w| w.bits(1u32 << self._pin()));
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}
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}
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/// Set the output as low.
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#[inline]
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fn set_low(&self) {
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unsafe {
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self.block().outclr.write(|w| w.bits(1u32 << self._pin()));
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}
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}
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}
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pub trait OptionalPin {}
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}
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pub trait Pin: Unborrow<Target = Self> + sealed::Pin + Sized + 'static {
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/// Number of the pin within the port (0..31)
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#[inline]
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fn pin(&self) -> u8 {
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self._pin()
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}
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/// Port of the pin
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#[inline]
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fn port(&self) -> Port {
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match self.pin_port() / 32 {
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0 => Port::Port0,
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#[cfg(any(feature = "nrf52833", feature = "nrf52840"))]
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1 => Port::Port1,
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_ => unsafe { unreachable_unchecked() },
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}
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}
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#[inline]
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fn psel_bits(&self) -> u32 {
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self.pin_port() as u32
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}
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/// Convert from concrete pin type PX_XX to type erased `AnyPin`.
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#[inline]
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fn degrade(self) -> AnyPin {
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AnyPin {
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pin_port: self.pin_port(),
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}
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}
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}
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// Type-erased GPIO pin
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pub struct AnyPin {
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pin_port: u8,
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}
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impl AnyPin {
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#[inline]
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pub unsafe fn steal(pin_port: u8) -> Self {
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Self { pin_port }
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}
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}
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unsafe_impl_unborrow!(AnyPin);
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impl Pin for AnyPin {}
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impl sealed::Pin for AnyPin {
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#[inline]
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fn pin_port(&self) -> u8 {
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self.pin_port
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}
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}
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// =====================
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/// Set up a pin for input
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#[inline]
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fn init_input<T: Pin>(pin: &T, pull: Pull) {
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pin.conf().write(|w| {
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w.dir().input();
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w.input().connect();
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match pull {
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Pull::None => {
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w.pull().disabled();
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}
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Pull::Up => {
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w.pull().pullup();
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}
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Pull::Down => {
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w.pull().pulldown();
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}
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}
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w.drive().s0s1();
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w.sense().disabled();
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w
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});
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}
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/// Set up a pin for output
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#[inline]
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fn init_output<T: Pin>(pin: &T, drive: OutputDrive) {
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let drive = match drive {
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OutputDrive::Standard => DRIVE_A::S0S1,
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OutputDrive::HighDrive0Standard1 => DRIVE_A::H0S1,
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OutputDrive::Standard0HighDrive1 => DRIVE_A::S0H1,
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OutputDrive::HighDrive => DRIVE_A::H0H1,
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OutputDrive::Disconnect0Standard1 => DRIVE_A::D0S1,
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OutputDrive::Disconnect0HighDrive1 => DRIVE_A::D0H1,
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OutputDrive::Standard0Disconnect1 => DRIVE_A::S0D1,
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OutputDrive::HighDrive0Disconnect1 => DRIVE_A::H0D1,
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};
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pin.conf().write(|w| {
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w.dir().output();
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w.input().disconnect();
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w.pull().disabled();
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w.drive().variant(drive);
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w.sense().disabled();
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w
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});
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}
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// ====================
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pub trait OptionalPin: Unborrow<Target = Self> + sealed::OptionalPin + Sized {
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type Pin: Pin;
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fn pin(&self) -> Option<&Self::Pin>;
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fn pin_mut(&mut self) -> Option<&mut Self::Pin>;
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#[inline]
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fn psel_bits(&self) -> u32 {
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self.pin().map_or(1u32 << 31, Pin::psel_bits)
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}
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/// Convert from concrete pin type PX_XX to type erased `Option<AnyPin>`.
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#[inline]
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fn degrade_optional(mut self) -> Option<AnyPin> {
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self.pin_mut()
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.map(|pin| unsafe { core::ptr::read(pin) }.degrade())
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}
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}
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impl<T: Pin> sealed::OptionalPin for T {}
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impl<T: Pin> OptionalPin for T {
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type Pin = T;
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#[inline]
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fn pin(&self) -> Option<&T> {
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Some(self)
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}
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#[inline]
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fn pin_mut(&mut self) -> Option<&mut T> {
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Some(self)
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}
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}
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#[derive(Clone, Copy, Debug)]
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pub struct NoPin;
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unsafe_impl_unborrow!(NoPin);
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impl sealed::OptionalPin for NoPin {}
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impl OptionalPin for NoPin {
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type Pin = AnyPin;
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#[inline]
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fn pin(&self) -> Option<&AnyPin> {
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None
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}
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#[inline]
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fn pin_mut(&mut self) -> Option<&mut AnyPin> {
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None
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}
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}
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// ====================
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pub(crate) fn deconfigure_pin(psel_bits: u32) {
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if psel_bits & 0x8000_0000 != 0 {
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return;
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}
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unsafe {
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AnyPin::steal(psel_bits as _).conf().reset();
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}
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}
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// ====================
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macro_rules! impl_pin {
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($type:ident, $port_num:expr, $pin_num:expr) => {
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impl crate::gpio::Pin for peripherals::$type {}
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impl crate::gpio::sealed::Pin for peripherals::$type {
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#[inline]
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fn pin_port(&self) -> u8 {
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$port_num * 32 + $pin_num
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}
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}
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};
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}
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