228 lines
6.9 KiB
Rust
228 lines
6.9 KiB
Rust
#![no_std]
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#![feature(async_fn_in_trait)]
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#![allow(stable_features, unknown_lints, async_fn_in_trait)]
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use core::slice;
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use cyw43::SpiBusCyw43;
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use embassy_rp::dma::Channel;
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use embassy_rp::gpio::{Drive, Level, Output, Pin, Pull, SlewRate};
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use embassy_rp::pio::{Common, Config, Direction, Instance, Irq, PioPin, ShiftDirection, StateMachine};
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use embassy_rp::{pio_instr_util, Peripheral, PeripheralRef};
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use fixed::FixedU32;
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use pio_proc::pio_asm;
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pub struct PioSpi<'d, CS: Pin, PIO: Instance, const SM: usize, DMA> {
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cs: Output<'d, CS>,
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sm: StateMachine<'d, PIO, SM>,
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irq: Irq<'d, PIO, 0>,
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dma: PeripheralRef<'d, DMA>,
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wrap_target: u8,
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}
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impl<'d, CS, PIO, const SM: usize, DMA> PioSpi<'d, CS, PIO, SM, DMA>
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where
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DMA: Channel,
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CS: Pin,
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PIO: Instance,
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{
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pub fn new<DIO, CLK>(
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common: &mut Common<'d, PIO>,
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mut sm: StateMachine<'d, PIO, SM>,
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irq: Irq<'d, PIO, 0>,
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cs: Output<'d, CS>,
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dio: DIO,
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clk: CLK,
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dma: impl Peripheral<P = DMA> + 'd,
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) -> Self
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where
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DIO: PioPin,
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CLK: PioPin,
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{
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#[cfg(feature = "overclock")]
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let program = pio_asm!(
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".side_set 1"
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".wrap_target"
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// write out x-1 bits
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"lp:"
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"out pins, 1 side 0"
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"jmp x-- lp side 1"
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// switch directions
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"set pindirs, 0 side 0"
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"nop side 1" // necessary for clkdiv=1.
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"nop side 0"
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// read in y-1 bits
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"lp2:"
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"in pins, 1 side 1"
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"jmp y-- lp2 side 0"
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// wait for event and irq host
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"wait 1 pin 0 side 0"
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"irq 0 side 0"
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".wrap"
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);
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#[cfg(not(feature = "overclock"))]
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let program = pio_asm!(
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".side_set 1"
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".wrap_target"
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// write out x-1 bits
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"lp:"
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"out pins, 1 side 0"
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"jmp x-- lp side 1"
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// switch directions
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"set pindirs, 0 side 0"
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"nop side 0"
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// read in y-1 bits
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"lp2:"
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"in pins, 1 side 1"
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"jmp y-- lp2 side 0"
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// wait for event and irq host
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"wait 1 pin 0 side 0"
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"irq 0 side 0"
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".wrap"
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);
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let mut pin_io: embassy_rp::pio::Pin<PIO> = common.make_pio_pin(dio);
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pin_io.set_pull(Pull::None);
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pin_io.set_schmitt(true);
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pin_io.set_input_sync_bypass(true);
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pin_io.set_drive_strength(Drive::_12mA);
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pin_io.set_slew_rate(SlewRate::Fast);
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let mut pin_clk = common.make_pio_pin(clk);
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pin_clk.set_drive_strength(Drive::_12mA);
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pin_clk.set_slew_rate(SlewRate::Fast);
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let mut cfg = Config::default();
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let loaded_program = common.load_program(&program.program);
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cfg.use_program(&loaded_program, &[&pin_clk]);
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cfg.set_out_pins(&[&pin_io]);
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cfg.set_in_pins(&[&pin_io]);
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cfg.set_set_pins(&[&pin_io]);
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cfg.shift_out.direction = ShiftDirection::Left;
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cfg.shift_out.auto_fill = true;
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//cfg.shift_out.threshold = 32;
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cfg.shift_in.direction = ShiftDirection::Left;
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cfg.shift_in.auto_fill = true;
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//cfg.shift_in.threshold = 32;
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#[cfg(feature = "overclock")]
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{
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// 125mhz Pio => 62.5Mhz SPI Freq. 25% higher than theoretical maximum according to
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// data sheet, but seems to work fine.
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cfg.clock_divider = FixedU32::from_bits(0x0100);
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}
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#[cfg(not(feature = "overclock"))]
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{
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// same speed as pico-sdk, 62.5Mhz
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// This is actually the fastest we can go without overclocking.
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// According to data sheet, the theoretical maximum is 100Mhz Pio => 50Mhz SPI Freq.
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// However, the PIO uses a fractional divider, which works by introducing jitter when
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// the divider is not an integer. It does some clocks at 125mhz and others at 62.5mhz
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// so that it averages out to the desired frequency of 100mhz. The 125mhz clock cycles
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// violate the maximum from the data sheet.
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cfg.clock_divider = FixedU32::from_bits(0x0200);
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}
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sm.set_config(&cfg);
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sm.set_pin_dirs(Direction::Out, &[&pin_clk, &pin_io]);
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sm.set_pins(Level::Low, &[&pin_clk, &pin_io]);
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Self {
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cs,
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sm,
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irq,
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dma: dma.into_ref(),
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wrap_target: loaded_program.wrap.target,
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}
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}
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pub async fn write(&mut self, write: &[u32]) -> u32 {
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self.sm.set_enable(false);
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let write_bits = write.len() * 32 - 1;
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let read_bits = 31;
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#[cfg(feature = "defmt")]
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defmt::trace!("write={} read={}", write_bits, read_bits);
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unsafe {
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pio_instr_util::set_x(&mut self.sm, write_bits as u32);
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pio_instr_util::set_y(&mut self.sm, read_bits as u32);
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pio_instr_util::set_pindir(&mut self.sm, 0b1);
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pio_instr_util::exec_jmp(&mut self.sm, self.wrap_target);
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}
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self.sm.set_enable(true);
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self.sm.tx().dma_push(self.dma.reborrow(), write).await;
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let mut status = 0;
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self.sm
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.rx()
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.dma_pull(self.dma.reborrow(), slice::from_mut(&mut status))
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.await;
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status
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}
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pub async fn cmd_read(&mut self, cmd: u32, read: &mut [u32]) -> u32 {
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self.sm.set_enable(false);
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let write_bits = 31;
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let read_bits = read.len() * 32 + 32 - 1;
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#[cfg(feature = "defmt")]
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defmt::trace!("write={} read={}", write_bits, read_bits);
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unsafe {
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pio_instr_util::set_y(&mut self.sm, read_bits as u32);
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pio_instr_util::set_x(&mut self.sm, write_bits as u32);
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pio_instr_util::set_pindir(&mut self.sm, 0b1);
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pio_instr_util::exec_jmp(&mut self.sm, self.wrap_target);
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}
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// self.cs.set_low();
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self.sm.set_enable(true);
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self.sm.tx().dma_push(self.dma.reborrow(), slice::from_ref(&cmd)).await;
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self.sm.rx().dma_pull(self.dma.reborrow(), read).await;
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let mut status = 0;
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self.sm
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.rx()
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.dma_pull(self.dma.reborrow(), slice::from_mut(&mut status))
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.await;
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status
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}
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}
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impl<'d, CS, PIO, const SM: usize, DMA> SpiBusCyw43 for PioSpi<'d, CS, PIO, SM, DMA>
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where
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CS: Pin,
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PIO: Instance,
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DMA: Channel,
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{
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async fn cmd_write(&mut self, write: &[u32]) -> u32 {
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self.cs.set_low();
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let status = self.write(write).await;
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self.cs.set_high();
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status
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}
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async fn cmd_read(&mut self, write: u32, read: &mut [u32]) -> u32 {
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self.cs.set_low();
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let status = self.cmd_read(write, read).await;
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self.cs.set_high();
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status
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}
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async fn wait_for_event(&mut self) {
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self.irq.wait().await;
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}
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}
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