127 lines
3.6 KiB
Rust
127 lines
3.6 KiB
Rust
use embassy_hal_internal::into_ref;
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use embedded_hal_02::blocking::delay::DelayUs;
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use crate::adc::{Adc, AdcPin, Instance, SampleTime};
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use crate::time::Hertz;
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use crate::Peripheral;
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pub const VDDA_CALIB_MV: u32 = 3300;
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pub const ADC_MAX: u32 = (1 << 12) - 1;
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pub const VREF_INT: u32 = 1230;
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pub struct Vref;
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impl<T: Instance> AdcPin<T> for Vref {}
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impl<T: Instance> super::sealed::AdcPin<T> for Vref {
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fn channel(&self) -> u8 {
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18
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}
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}
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pub struct Temperature;
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impl<T: Instance> AdcPin<T> for Temperature {}
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impl<T: Instance> super::sealed::AdcPin<T> for Temperature {
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fn channel(&self) -> u8 {
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16
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}
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}
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impl<'d, T: Instance> Adc<'d, T> {
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pub fn new(adc: impl Peripheral<P = T> + 'd, delay: &mut impl DelayUs<u32>) -> Self {
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use crate::pac::adc::vals;
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into_ref!(adc);
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T::enable();
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T::reset();
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// Enable the adc regulator
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T::regs().cr().modify(|w| w.set_advregen(vals::Advregen::INTERMEDIATE));
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T::regs().cr().modify(|w| w.set_advregen(vals::Advregen::ENABLED));
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// Wait for the regulator to stabilize
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delay.delay_us(10);
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assert!(!T::regs().cr().read().aden());
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// Begin calibration
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T::regs().cr().modify(|w| w.set_adcaldif(false));
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T::regs().cr().modify(|w| w.set_adcal(true));
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while T::regs().cr().read().adcal() {}
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// Wait more than 4 clock cycles after adcal is cleared (RM0364 p. 223)
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delay.delay_us(1 + (6 * 1_000_000 / Self::freq().0));
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// Enable the adc
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T::regs().cr().modify(|w| w.set_aden(true));
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// Wait until the adc is ready
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while !T::regs().isr().read().adrdy() {}
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Self {
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adc,
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sample_time: Default::default(),
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}
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}
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fn freq() -> Hertz {
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<T as crate::adc::sealed::Instance>::frequency()
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}
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pub fn sample_time_for_us(&self, us: u32) -> SampleTime {
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match us * Self::freq().0 / 1_000_000 {
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0..=1 => SampleTime::Cycles1_5,
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2..=4 => SampleTime::Cycles4_5,
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5..=7 => SampleTime::Cycles7_5,
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8..=19 => SampleTime::Cycles19_5,
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20..=61 => SampleTime::Cycles61_5,
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62..=181 => SampleTime::Cycles181_5,
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_ => SampleTime::Cycles601_5,
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}
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}
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pub fn enable_vref(&self, _delay: &mut impl DelayUs<u32>) -> Vref {
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T::common_regs().ccr().modify(|w| w.set_vrefen(true));
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Vref {}
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}
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pub fn enable_temperature(&self) -> Temperature {
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T::common_regs().ccr().modify(|w| w.set_tsen(true));
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Temperature {}
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}
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pub fn set_sample_time(&mut self, sample_time: SampleTime) {
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self.sample_time = sample_time;
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}
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/// Perform a single conversion.
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fn convert(&mut self) -> u16 {
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T::regs().isr().write(|_| {});
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T::regs().cr().modify(|w| w.set_adstart(true));
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while !T::regs().isr().read().eoc() && !T::regs().isr().read().eos() {}
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T::regs().isr().write(|_| {});
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T::regs().dr().read().rdata()
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}
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pub fn read(&mut self, pin: &mut impl AdcPin<T>) -> u16 {
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Self::set_channel_sample_time(pin.channel(), self.sample_time);
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// Configure the channel to sample
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T::regs().sqr1().write(|w| w.set_sq(0, pin.channel()));
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self.convert()
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}
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fn set_channel_sample_time(ch: u8, sample_time: SampleTime) {
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let sample_time = sample_time.into();
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if ch <= 9 {
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T::regs().smpr2().modify(|reg| reg.set_smp(ch as _, sample_time));
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} else {
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T::regs().smpr1().modify(|reg| reg.set_smp((ch - 10) as _, sample_time));
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}
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}
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}
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