1195 lines
32 KiB
Rust
1195 lines
32 KiB
Rust
//! Inter-IC Sound (I2S) driver.
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#![macro_use]
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use core::future::poll_fn;
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use core::marker::PhantomData;
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use core::mem::size_of;
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use core::ops::{Deref, DerefMut};
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use core::sync::atomic::{compiler_fence, Ordering};
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use core::task::Poll;
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use embassy_hal_internal::drop::OnDrop;
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use embassy_hal_internal::{into_ref, PeripheralRef};
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use crate::gpio::{AnyPin, Pin as GpioPin};
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use crate::interrupt::typelevel::Interrupt;
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use crate::pac::i2s::RegisterBlock;
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use crate::util::{slice_in_ram_or, slice_ptr_parts};
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use crate::{interrupt, Peripheral, EASY_DMA_SIZE};
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/// Type alias for `MultiBuffering` with 2 buffers.
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pub type DoubleBuffering<S, const NS: usize> = MultiBuffering<S, 2, NS>;
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/// I2S transfer error.
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#[derive(Debug, Clone, Copy, PartialEq, Eq)]
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#[cfg_attr(feature = "defmt", derive(defmt::Format))]
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#[non_exhaustive]
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pub enum Error {
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/// The buffer is too long.
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BufferTooLong,
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/// The buffer is empty.
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BufferZeroLength,
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/// The buffer is not in data RAM. It's most likely in flash, and nRF's DMA cannot access flash.
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BufferNotInRAM,
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/// The buffer address is not aligned.
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BufferMisaligned,
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/// The buffer length is not a multiple of the alignment.
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BufferLengthMisaligned,
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}
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/// I2S configuration.
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#[derive(Clone)]
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#[non_exhaustive]
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pub struct Config {
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/// Sample width
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pub sample_width: SampleWidth,
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/// Alignment
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pub align: Align,
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/// Sample format
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pub format: Format,
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/// Channel configuration.
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pub channels: Channels,
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}
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impl Default for Config {
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fn default() -> Self {
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Self {
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sample_width: SampleWidth::_16bit,
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align: Align::Left,
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format: Format::I2S,
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channels: Channels::Stereo,
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}
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}
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}
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/// I2S clock configuration.
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#[derive(Debug, Eq, PartialEq, Clone, Copy)]
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pub struct MasterClock {
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freq: MckFreq,
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ratio: Ratio,
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}
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impl MasterClock {
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/// Create a new `MasterClock`.
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pub fn new(freq: MckFreq, ratio: Ratio) -> Self {
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Self { freq, ratio }
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}
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}
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impl MasterClock {
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/// Get the sample rate for this clock configuration.
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pub fn sample_rate(&self) -> u32 {
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self.freq.to_frequency() / self.ratio.to_divisor()
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}
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}
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/// Master clock generator frequency.
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#[derive(Debug, Eq, PartialEq, Clone, Copy)]
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pub enum MckFreq {
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/// 32 Mhz / 8 = 4000.00 kHz
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_32MDiv8,
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/// 32 Mhz / 10 = 3200.00 kHz
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_32MDiv10,
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/// 32 Mhz / 11 = 2909.09 kHz
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_32MDiv11,
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/// 32 Mhz / 15 = 2133.33 kHz
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_32MDiv15,
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/// 32 Mhz / 16 = 2000.00 kHz
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_32MDiv16,
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/// 32 Mhz / 21 = 1523.81 kHz
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_32MDiv21,
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/// 32 Mhz / 23 = 1391.30 kHz
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_32MDiv23,
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/// 32 Mhz / 30 = 1066.67 kHz
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_32MDiv30,
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/// 32 Mhz / 31 = 1032.26 kHz
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_32MDiv31,
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/// 32 Mhz / 32 = 1000.00 kHz
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_32MDiv32,
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/// 32 Mhz / 42 = 761.90 kHz
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_32MDiv42,
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/// 32 Mhz / 63 = 507.94 kHz
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_32MDiv63,
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/// 32 Mhz / 125 = 256.00 kHz
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_32MDiv125,
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}
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impl MckFreq {
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const REGISTER_VALUES: &'static [u32] = &[
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0x20000000, 0x18000000, 0x16000000, 0x11000000, 0x10000000, 0x0C000000, 0x0B000000, 0x08800000, 0x08400000,
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0x08000000, 0x06000000, 0x04100000, 0x020C0000,
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];
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const FREQUENCIES: &'static [u32] = &[
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4000000, 3200000, 2909090, 2133333, 2000000, 1523809, 1391304, 1066666, 1032258, 1000000, 761904, 507936,
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256000,
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];
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/// Return the value that needs to be written to the register.
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pub fn to_register_value(&self) -> u32 {
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Self::REGISTER_VALUES[usize::from(*self)]
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}
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/// Return the master clock frequency.
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pub fn to_frequency(&self) -> u32 {
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Self::FREQUENCIES[usize::from(*self)]
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}
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}
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impl From<MckFreq> for usize {
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fn from(variant: MckFreq) -> Self {
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variant as _
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}
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}
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/// Master clock frequency ratio
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///
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/// Sample Rate = LRCK = MCK / Ratio
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///
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#[derive(Debug, Eq, PartialEq, Clone, Copy)]
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pub enum Ratio {
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/// Divide by 32
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_32x,
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/// Divide by 48
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_48x,
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/// Divide by 64
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_64x,
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/// Divide by 96
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_96x,
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/// Divide by 128
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_128x,
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/// Divide by 192
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_192x,
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/// Divide by 256
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_256x,
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/// Divide by 384
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_384x,
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/// Divide by 512
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_512x,
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}
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impl Ratio {
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const RATIOS: &'static [u32] = &[32, 48, 64, 96, 128, 192, 256, 384, 512];
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/// Return the value that needs to be written to the register.
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pub fn to_register_value(&self) -> u8 {
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usize::from(*self) as u8
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}
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/// Return the divisor for this ratio
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pub fn to_divisor(&self) -> u32 {
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Self::RATIOS[usize::from(*self)]
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}
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}
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impl From<Ratio> for usize {
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fn from(variant: Ratio) -> Self {
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variant as _
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}
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}
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/// Approximate sample rates.
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///
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/// Those are common sample rates that can not be configured without an small error.
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///
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/// For custom master clock configuration, please refer to [MasterClock].
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#[derive(Clone, Copy)]
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pub enum ApproxSampleRate {
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/// 11025 Hz
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_11025,
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/// 16000 Hz
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_16000,
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/// 22050 Hz
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_22050,
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/// 32000 Hz
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_32000,
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/// 44100 Hz
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_44100,
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/// 48000 Hz
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_48000,
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}
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impl From<ApproxSampleRate> for MasterClock {
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fn from(value: ApproxSampleRate) -> Self {
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match value {
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// error = 86
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ApproxSampleRate::_11025 => MasterClock::new(MckFreq::_32MDiv15, Ratio::_192x),
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// error = 127
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ApproxSampleRate::_16000 => MasterClock::new(MckFreq::_32MDiv21, Ratio::_96x),
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// error = 172
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ApproxSampleRate::_22050 => MasterClock::new(MckFreq::_32MDiv15, Ratio::_96x),
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// error = 254
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ApproxSampleRate::_32000 => MasterClock::new(MckFreq::_32MDiv21, Ratio::_48x),
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// error = 344
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ApproxSampleRate::_44100 => MasterClock::new(MckFreq::_32MDiv15, Ratio::_48x),
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// error = 381
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ApproxSampleRate::_48000 => MasterClock::new(MckFreq::_32MDiv21, Ratio::_32x),
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}
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}
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}
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impl ApproxSampleRate {
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/// Get the sample rate as an integer.
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pub fn sample_rate(&self) -> u32 {
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MasterClock::from(*self).sample_rate()
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}
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}
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/// Exact sample rates.
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///
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/// Those are non standard sample rates that can be configured without error.
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///
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/// For custom master clock configuration, please refer to [Mode].
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#[derive(Clone, Copy)]
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pub enum ExactSampleRate {
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/// 8000 Hz
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_8000,
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/// 10582 Hz
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_10582,
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/// 12500 Hz
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_12500,
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/// 15625 Hz
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_15625,
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/// 15873 Hz
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_15873,
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/// 25000 Hz
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_25000,
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/// 31250 Hz
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_31250,
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/// 50000 Hz
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_50000,
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/// 62500 Hz
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_62500,
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/// 100000 Hz
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_100000,
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/// 125000 Hz
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_125000,
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}
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impl ExactSampleRate {
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/// Get the sample rate as an integer.
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pub fn sample_rate(&self) -> u32 {
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MasterClock::from(*self).sample_rate()
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}
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}
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impl From<ExactSampleRate> for MasterClock {
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fn from(value: ExactSampleRate) -> Self {
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match value {
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ExactSampleRate::_8000 => MasterClock::new(MckFreq::_32MDiv125, Ratio::_32x),
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ExactSampleRate::_10582 => MasterClock::new(MckFreq::_32MDiv63, Ratio::_48x),
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ExactSampleRate::_12500 => MasterClock::new(MckFreq::_32MDiv10, Ratio::_256x),
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ExactSampleRate::_15625 => MasterClock::new(MckFreq::_32MDiv32, Ratio::_64x),
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ExactSampleRate::_15873 => MasterClock::new(MckFreq::_32MDiv63, Ratio::_32x),
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ExactSampleRate::_25000 => MasterClock::new(MckFreq::_32MDiv10, Ratio::_128x),
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ExactSampleRate::_31250 => MasterClock::new(MckFreq::_32MDiv32, Ratio::_32x),
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ExactSampleRate::_50000 => MasterClock::new(MckFreq::_32MDiv10, Ratio::_64x),
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ExactSampleRate::_62500 => MasterClock::new(MckFreq::_32MDiv16, Ratio::_32x),
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ExactSampleRate::_100000 => MasterClock::new(MckFreq::_32MDiv10, Ratio::_32x),
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ExactSampleRate::_125000 => MasterClock::new(MckFreq::_32MDiv8, Ratio::_32x),
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}
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}
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}
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/// Sample width.
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#[derive(Debug, Eq, PartialEq, Clone, Copy)]
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pub enum SampleWidth {
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/// 8 bit samples.
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_8bit,
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/// 16 bit samples.
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_16bit,
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/// 24 bit samples.
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_24bit,
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}
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impl From<SampleWidth> for u8 {
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fn from(variant: SampleWidth) -> Self {
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variant as _
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}
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}
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/// Channel used for the most significant sample value in a frame.
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#[derive(Debug, Eq, PartialEq, Clone, Copy)]
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pub enum Align {
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/// Left-align samples.
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Left,
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/// Right-align samples.
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Right,
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}
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impl From<Align> for bool {
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fn from(variant: Align) -> Self {
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match variant {
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Align::Left => false,
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Align::Right => true,
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}
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}
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}
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/// Frame format.
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#[derive(Debug, Eq, PartialEq, Clone, Copy)]
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pub enum Format {
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/// I2S frame format
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I2S,
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/// Aligned frame format
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Aligned,
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}
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impl From<Format> for bool {
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fn from(variant: Format) -> Self {
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match variant {
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Format::I2S => false,
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Format::Aligned => true,
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}
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}
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}
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/// Channels
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#[derive(Debug, Eq, PartialEq, Clone, Copy)]
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pub enum Channels {
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/// Stereo (2 channels).
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Stereo,
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/// Mono, left channel only.
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MonoLeft,
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/// Mono, right channel only.
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MonoRight,
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}
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impl From<Channels> for u8 {
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fn from(variant: Channels) -> Self {
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variant as _
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}
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}
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/// Interrupt handler.
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pub struct InterruptHandler<T: Instance> {
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_phantom: PhantomData<T>,
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}
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impl<T: Instance> interrupt::typelevel::Handler<T::Interrupt> for InterruptHandler<T> {
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unsafe fn on_interrupt() {
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let device = Device::<T>::new();
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let s = T::state();
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if device.is_tx_ptr_updated() {
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trace!("TX INT");
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s.tx_waker.wake();
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device.disable_tx_ptr_interrupt();
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}
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if device.is_rx_ptr_updated() {
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trace!("RX INT");
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s.rx_waker.wake();
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device.disable_rx_ptr_interrupt();
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}
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if device.is_stopped() {
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trace!("STOPPED INT");
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s.stop_waker.wake();
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device.disable_stopped_interrupt();
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}
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}
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}
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/// I2S driver.
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pub struct I2S<'d, T: Instance> {
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i2s: PeripheralRef<'d, T>,
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mck: Option<PeripheralRef<'d, AnyPin>>,
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sck: PeripheralRef<'d, AnyPin>,
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lrck: PeripheralRef<'d, AnyPin>,
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sdin: Option<PeripheralRef<'d, AnyPin>>,
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sdout: Option<PeripheralRef<'d, AnyPin>>,
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master_clock: Option<MasterClock>,
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config: Config,
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}
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impl<'d, T: Instance> I2S<'d, T> {
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/// Create a new I2S in master mode
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pub fn new_master(
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i2s: impl Peripheral<P = T> + 'd,
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_irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
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mck: impl Peripheral<P = impl GpioPin> + 'd,
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sck: impl Peripheral<P = impl GpioPin> + 'd,
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lrck: impl Peripheral<P = impl GpioPin> + 'd,
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master_clock: MasterClock,
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config: Config,
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) -> Self {
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into_ref!(i2s, mck, sck, lrck);
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Self {
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i2s,
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mck: Some(mck.map_into()),
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sck: sck.map_into(),
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lrck: lrck.map_into(),
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sdin: None,
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sdout: None,
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master_clock: Some(master_clock),
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config,
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}
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}
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/// Create a new I2S in slave mode
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pub fn new_slave(
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i2s: impl Peripheral<P = T> + 'd,
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_irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
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sck: impl Peripheral<P = impl GpioPin> + 'd,
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lrck: impl Peripheral<P = impl GpioPin> + 'd,
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config: Config,
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) -> Self {
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into_ref!(i2s, sck, lrck);
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Self {
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i2s,
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mck: None,
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sck: sck.map_into(),
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lrck: lrck.map_into(),
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sdin: None,
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sdout: None,
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master_clock: None,
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config,
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}
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}
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/// I2S output only
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pub fn output<S: Sample, const NB: usize, const NS: usize>(
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mut self,
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sdout: impl Peripheral<P = impl GpioPin> + 'd,
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buffers: MultiBuffering<S, NB, NS>,
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) -> OutputStream<'d, T, S, NB, NS> {
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self.sdout = Some(sdout.into_ref().map_into());
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OutputStream {
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_p: self.build(),
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buffers,
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}
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}
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/// I2S input only
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pub fn input<S: Sample, const NB: usize, const NS: usize>(
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mut self,
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sdin: impl Peripheral<P = impl GpioPin> + 'd,
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buffers: MultiBuffering<S, NB, NS>,
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) -> InputStream<'d, T, S, NB, NS> {
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self.sdin = Some(sdin.into_ref().map_into());
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InputStream {
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_p: self.build(),
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buffers,
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}
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}
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/// I2S full duplex (input and output)
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pub fn full_duplex<S: Sample, const NB: usize, const NS: usize>(
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mut self,
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sdin: impl Peripheral<P = impl GpioPin> + 'd,
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sdout: impl Peripheral<P = impl GpioPin> + 'd,
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buffers_out: MultiBuffering<S, NB, NS>,
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buffers_in: MultiBuffering<S, NB, NS>,
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) -> FullDuplexStream<'d, T, S, NB, NS> {
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self.sdout = Some(sdout.into_ref().map_into());
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self.sdin = Some(sdin.into_ref().map_into());
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FullDuplexStream {
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_p: self.build(),
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buffers_out,
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buffers_in,
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}
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}
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fn build(self) -> PeripheralRef<'d, T> {
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self.apply_config();
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self.select_pins();
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self.setup_interrupt();
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let device = Device::<T>::new();
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device.enable();
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self.i2s
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}
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fn apply_config(&self) {
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let c = &T::regs().config;
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match &self.master_clock {
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Some(MasterClock { freq, ratio }) => {
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c.mode.write(|w| w.mode().master());
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c.mcken.write(|w| w.mcken().enabled());
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c.mckfreq
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.write(|w| unsafe { w.mckfreq().bits(freq.to_register_value()) });
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c.ratio.write(|w| unsafe { w.ratio().bits(ratio.to_register_value()) });
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}
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None => {
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c.mode.write(|w| w.mode().slave());
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}
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};
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c.swidth
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.write(|w| unsafe { w.swidth().bits(self.config.sample_width.into()) });
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c.align.write(|w| w.align().bit(self.config.align.into()));
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c.format.write(|w| w.format().bit(self.config.format.into()));
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c.channels
|
|
.write(|w| unsafe { w.channels().bits(self.config.channels.into()) });
|
|
}
|
|
|
|
fn select_pins(&self) {
|
|
let psel = &T::regs().psel;
|
|
|
|
if let Some(mck) = &self.mck {
|
|
psel.mck.write(|w| {
|
|
unsafe { w.bits(mck.psel_bits()) };
|
|
w.connect().connected()
|
|
});
|
|
}
|
|
|
|
psel.sck.write(|w| {
|
|
unsafe { w.bits(self.sck.psel_bits()) };
|
|
w.connect().connected()
|
|
});
|
|
|
|
psel.lrck.write(|w| {
|
|
unsafe { w.bits(self.lrck.psel_bits()) };
|
|
w.connect().connected()
|
|
});
|
|
|
|
if let Some(sdin) = &self.sdin {
|
|
psel.sdin.write(|w| {
|
|
unsafe { w.bits(sdin.psel_bits()) };
|
|
w.connect().connected()
|
|
});
|
|
}
|
|
|
|
if let Some(sdout) = &self.sdout {
|
|
psel.sdout.write(|w| {
|
|
unsafe { w.bits(sdout.psel_bits()) };
|
|
w.connect().connected()
|
|
});
|
|
}
|
|
}
|
|
|
|
fn setup_interrupt(&self) {
|
|
T::Interrupt::unpend();
|
|
unsafe { T::Interrupt::enable() };
|
|
|
|
let device = Device::<T>::new();
|
|
device.disable_tx_ptr_interrupt();
|
|
device.disable_rx_ptr_interrupt();
|
|
device.disable_stopped_interrupt();
|
|
|
|
device.reset_tx_ptr_event();
|
|
device.reset_rx_ptr_event();
|
|
device.reset_stopped_event();
|
|
|
|
device.enable_tx_ptr_interrupt();
|
|
device.enable_rx_ptr_interrupt();
|
|
device.enable_stopped_interrupt();
|
|
}
|
|
|
|
async fn stop() {
|
|
compiler_fence(Ordering::SeqCst);
|
|
|
|
let device = Device::<T>::new();
|
|
device.stop();
|
|
|
|
T::state().started.store(false, Ordering::Relaxed);
|
|
|
|
poll_fn(|cx| {
|
|
T::state().stop_waker.register(cx.waker());
|
|
|
|
if device.is_stopped() {
|
|
trace!("STOP: Ready");
|
|
device.reset_stopped_event();
|
|
Poll::Ready(())
|
|
} else {
|
|
trace!("STOP: Pending");
|
|
Poll::Pending
|
|
}
|
|
})
|
|
.await;
|
|
|
|
device.disable();
|
|
}
|
|
|
|
async fn send_from_ram<S>(buffer_ptr: *const [S]) -> Result<(), Error>
|
|
where
|
|
S: Sample,
|
|
{
|
|
trace!("SEND: {}", buffer_ptr as *const S as u32);
|
|
|
|
slice_in_ram_or(buffer_ptr, Error::BufferNotInRAM)?;
|
|
|
|
compiler_fence(Ordering::SeqCst);
|
|
|
|
let device = Device::<T>::new();
|
|
|
|
device.update_tx(buffer_ptr)?;
|
|
|
|
Self::wait_tx_ptr_update().await;
|
|
|
|
compiler_fence(Ordering::SeqCst);
|
|
|
|
Ok(())
|
|
}
|
|
|
|
async fn wait_tx_ptr_update() {
|
|
let drop = OnDrop::new(move || {
|
|
trace!("TX DROP: Stopping");
|
|
|
|
let device = Device::<T>::new();
|
|
device.disable_tx_ptr_interrupt();
|
|
device.reset_tx_ptr_event();
|
|
device.disable_tx();
|
|
|
|
// TX is stopped almost instantly, spinning is fine.
|
|
while !device.is_tx_ptr_updated() {}
|
|
|
|
trace!("TX DROP: Stopped");
|
|
});
|
|
|
|
poll_fn(|cx| {
|
|
T::state().tx_waker.register(cx.waker());
|
|
|
|
let device = Device::<T>::new();
|
|
if device.is_tx_ptr_updated() {
|
|
trace!("TX POLL: Ready");
|
|
device.reset_tx_ptr_event();
|
|
device.enable_tx_ptr_interrupt();
|
|
Poll::Ready(())
|
|
} else {
|
|
trace!("TX POLL: Pending");
|
|
Poll::Pending
|
|
}
|
|
})
|
|
.await;
|
|
|
|
drop.defuse();
|
|
}
|
|
|
|
async fn receive_from_ram<S>(buffer_ptr: *mut [S]) -> Result<(), Error>
|
|
where
|
|
S: Sample,
|
|
{
|
|
trace!("RECEIVE: {}", buffer_ptr as *const S as u32);
|
|
|
|
// NOTE: RAM slice check for rx is not necessary, as a mutable
|
|
// slice can only be built from data located in RAM.
|
|
|
|
compiler_fence(Ordering::SeqCst);
|
|
|
|
let device = Device::<T>::new();
|
|
|
|
device.update_rx(buffer_ptr)?;
|
|
|
|
Self::wait_rx_ptr_update().await;
|
|
|
|
compiler_fence(Ordering::SeqCst);
|
|
|
|
Ok(())
|
|
}
|
|
|
|
async fn wait_rx_ptr_update() {
|
|
let drop = OnDrop::new(move || {
|
|
trace!("RX DROP: Stopping");
|
|
|
|
let device = Device::<T>::new();
|
|
device.disable_rx_ptr_interrupt();
|
|
device.reset_rx_ptr_event();
|
|
device.disable_rx();
|
|
|
|
// TX is stopped almost instantly, spinning is fine.
|
|
while !device.is_rx_ptr_updated() {}
|
|
|
|
trace!("RX DROP: Stopped");
|
|
});
|
|
|
|
poll_fn(|cx| {
|
|
T::state().rx_waker.register(cx.waker());
|
|
|
|
let device = Device::<T>::new();
|
|
if device.is_rx_ptr_updated() {
|
|
trace!("RX POLL: Ready");
|
|
device.reset_rx_ptr_event();
|
|
device.enable_rx_ptr_interrupt();
|
|
Poll::Ready(())
|
|
} else {
|
|
trace!("RX POLL: Pending");
|
|
Poll::Pending
|
|
}
|
|
})
|
|
.await;
|
|
|
|
drop.defuse();
|
|
}
|
|
}
|
|
|
|
/// I2S output
|
|
pub struct OutputStream<'d, T: Instance, S: Sample, const NB: usize, const NS: usize> {
|
|
_p: PeripheralRef<'d, T>,
|
|
buffers: MultiBuffering<S, NB, NS>,
|
|
}
|
|
|
|
impl<'d, T: Instance, S: Sample, const NB: usize, const NS: usize> OutputStream<'d, T, S, NB, NS> {
|
|
/// Get a mutable reference to the current buffer.
|
|
pub fn buffer(&mut self) -> &mut [S] {
|
|
self.buffers.get_mut()
|
|
}
|
|
|
|
/// Prepare the initial buffer and start the I2S transfer.
|
|
pub async fn start(&mut self) -> Result<(), Error>
|
|
where
|
|
S: Sample,
|
|
{
|
|
let device = Device::<T>::new();
|
|
|
|
let s = T::state();
|
|
if s.started.load(Ordering::Relaxed) {
|
|
self.stop().await;
|
|
}
|
|
|
|
device.enable();
|
|
device.enable_tx();
|
|
|
|
device.update_tx(self.buffers.switch())?;
|
|
|
|
s.started.store(true, Ordering::Relaxed);
|
|
|
|
device.start();
|
|
|
|
I2S::<T>::wait_tx_ptr_update().await;
|
|
|
|
Ok(())
|
|
}
|
|
|
|
/// Stops the I2S transfer and waits until it has stopped.
|
|
#[inline(always)]
|
|
pub async fn stop(&self) {
|
|
I2S::<T>::stop().await
|
|
}
|
|
|
|
/// Sends the current buffer for transmission in the DMA.
|
|
/// Switches to use the next available buffer.
|
|
pub async fn send(&mut self) -> Result<(), Error>
|
|
where
|
|
S: Sample,
|
|
{
|
|
I2S::<T>::send_from_ram(self.buffers.switch()).await
|
|
}
|
|
}
|
|
|
|
/// I2S input
|
|
pub struct InputStream<'d, T: Instance, S: Sample, const NB: usize, const NS: usize> {
|
|
_p: PeripheralRef<'d, T>,
|
|
buffers: MultiBuffering<S, NB, NS>,
|
|
}
|
|
|
|
impl<'d, T: Instance, S: Sample, const NB: usize, const NS: usize> InputStream<'d, T, S, NB, NS> {
|
|
/// Get a mutable reference to the current buffer.
|
|
pub fn buffer(&mut self) -> &mut [S] {
|
|
self.buffers.get_mut()
|
|
}
|
|
|
|
/// Prepare the initial buffer and start the I2S transfer.
|
|
pub async fn start(&mut self) -> Result<(), Error>
|
|
where
|
|
S: Sample,
|
|
{
|
|
let device = Device::<T>::new();
|
|
|
|
let s = T::state();
|
|
if s.started.load(Ordering::Relaxed) {
|
|
self.stop().await;
|
|
}
|
|
|
|
device.enable();
|
|
device.enable_rx();
|
|
|
|
device.update_rx(self.buffers.switch())?;
|
|
|
|
s.started.store(true, Ordering::Relaxed);
|
|
|
|
device.start();
|
|
|
|
I2S::<T>::wait_rx_ptr_update().await;
|
|
|
|
Ok(())
|
|
}
|
|
|
|
/// Stops the I2S transfer and waits until it has stopped.
|
|
#[inline(always)]
|
|
pub async fn stop(&self) {
|
|
I2S::<T>::stop().await
|
|
}
|
|
|
|
/// Sets the current buffer for reception from the DMA.
|
|
/// Switches to use the next available buffer.
|
|
#[allow(unused_mut)]
|
|
pub async fn receive(&mut self) -> Result<(), Error>
|
|
where
|
|
S: Sample,
|
|
{
|
|
I2S::<T>::receive_from_ram(self.buffers.switch_mut()).await
|
|
}
|
|
}
|
|
|
|
/// I2S full duplex stream (input & output)
|
|
pub struct FullDuplexStream<'d, T: Instance, S: Sample, const NB: usize, const NS: usize> {
|
|
_p: PeripheralRef<'d, T>,
|
|
buffers_out: MultiBuffering<S, NB, NS>,
|
|
buffers_in: MultiBuffering<S, NB, NS>,
|
|
}
|
|
|
|
impl<'d, T: Instance, S: Sample, const NB: usize, const NS: usize> FullDuplexStream<'d, T, S, NB, NS> {
|
|
/// Get the current output and input buffers.
|
|
pub fn buffers(&mut self) -> (&mut [S], &[S]) {
|
|
(self.buffers_out.get_mut(), self.buffers_in.get())
|
|
}
|
|
|
|
/// Prepare the initial buffers and start the I2S transfer.
|
|
pub async fn start(&mut self) -> Result<(), Error>
|
|
where
|
|
S: Sample,
|
|
{
|
|
let device = Device::<T>::new();
|
|
|
|
let s = T::state();
|
|
if s.started.load(Ordering::Relaxed) {
|
|
self.stop().await;
|
|
}
|
|
|
|
device.enable();
|
|
device.enable_tx();
|
|
device.enable_rx();
|
|
|
|
device.update_tx(self.buffers_out.switch())?;
|
|
device.update_rx(self.buffers_in.switch_mut())?;
|
|
|
|
s.started.store(true, Ordering::Relaxed);
|
|
|
|
device.start();
|
|
|
|
I2S::<T>::wait_tx_ptr_update().await;
|
|
I2S::<T>::wait_rx_ptr_update().await;
|
|
|
|
Ok(())
|
|
}
|
|
|
|
/// Stops the I2S transfer and waits until it has stopped.
|
|
#[inline(always)]
|
|
pub async fn stop(&self) {
|
|
I2S::<T>::stop().await
|
|
}
|
|
|
|
/// Sets the current buffers for output and input for transmission/reception from the DMA.
|
|
/// Switch to use the next available buffers for output/input.
|
|
pub async fn send_and_receive(&mut self) -> Result<(), Error>
|
|
where
|
|
S: Sample,
|
|
{
|
|
I2S::<T>::send_from_ram(self.buffers_out.switch()).await?;
|
|
I2S::<T>::receive_from_ram(self.buffers_in.switch_mut()).await?;
|
|
Ok(())
|
|
}
|
|
}
|
|
|
|
/// Helper encapsulating common I2S device operations.
|
|
struct Device<T>(&'static RegisterBlock, PhantomData<T>);
|
|
|
|
impl<T: Instance> Device<T> {
|
|
fn new() -> Self {
|
|
Self(T::regs(), PhantomData)
|
|
}
|
|
|
|
#[inline(always)]
|
|
pub fn enable(&self) {
|
|
trace!("ENABLED");
|
|
self.0.enable.write(|w| w.enable().enabled());
|
|
}
|
|
|
|
#[inline(always)]
|
|
pub fn disable(&self) {
|
|
trace!("DISABLED");
|
|
self.0.enable.write(|w| w.enable().disabled());
|
|
}
|
|
|
|
#[inline(always)]
|
|
fn enable_tx(&self) {
|
|
trace!("TX ENABLED");
|
|
self.0.config.txen.write(|w| w.txen().enabled());
|
|
}
|
|
|
|
#[inline(always)]
|
|
fn disable_tx(&self) {
|
|
trace!("TX DISABLED");
|
|
self.0.config.txen.write(|w| w.txen().disabled());
|
|
}
|
|
|
|
#[inline(always)]
|
|
fn enable_rx(&self) {
|
|
trace!("RX ENABLED");
|
|
self.0.config.rxen.write(|w| w.rxen().enabled());
|
|
}
|
|
|
|
#[inline(always)]
|
|
fn disable_rx(&self) {
|
|
trace!("RX DISABLED");
|
|
self.0.config.rxen.write(|w| w.rxen().disabled());
|
|
}
|
|
|
|
#[inline(always)]
|
|
fn start(&self) {
|
|
trace!("START");
|
|
self.0.tasks_start.write(|w| unsafe { w.bits(1) });
|
|
}
|
|
|
|
#[inline(always)]
|
|
fn stop(&self) {
|
|
self.0.tasks_stop.write(|w| unsafe { w.bits(1) });
|
|
}
|
|
|
|
#[inline(always)]
|
|
fn is_stopped(&self) -> bool {
|
|
self.0.events_stopped.read().bits() != 0
|
|
}
|
|
|
|
#[inline(always)]
|
|
fn reset_stopped_event(&self) {
|
|
trace!("STOPPED EVENT: Reset");
|
|
self.0.events_stopped.reset();
|
|
}
|
|
|
|
#[inline(always)]
|
|
fn disable_stopped_interrupt(&self) {
|
|
trace!("STOPPED INTERRUPT: Disabled");
|
|
self.0.intenclr.write(|w| w.stopped().clear());
|
|
}
|
|
|
|
#[inline(always)]
|
|
fn enable_stopped_interrupt(&self) {
|
|
trace!("STOPPED INTERRUPT: Enabled");
|
|
self.0.intenset.write(|w| w.stopped().set());
|
|
}
|
|
|
|
#[inline(always)]
|
|
fn reset_tx_ptr_event(&self) {
|
|
trace!("TX PTR EVENT: Reset");
|
|
self.0.events_txptrupd.reset();
|
|
}
|
|
|
|
#[inline(always)]
|
|
fn reset_rx_ptr_event(&self) {
|
|
trace!("RX PTR EVENT: Reset");
|
|
self.0.events_rxptrupd.reset();
|
|
}
|
|
|
|
#[inline(always)]
|
|
fn disable_tx_ptr_interrupt(&self) {
|
|
trace!("TX PTR INTERRUPT: Disabled");
|
|
self.0.intenclr.write(|w| w.txptrupd().clear());
|
|
}
|
|
|
|
#[inline(always)]
|
|
fn disable_rx_ptr_interrupt(&self) {
|
|
trace!("RX PTR INTERRUPT: Disabled");
|
|
self.0.intenclr.write(|w| w.rxptrupd().clear());
|
|
}
|
|
|
|
#[inline(always)]
|
|
fn enable_tx_ptr_interrupt(&self) {
|
|
trace!("TX PTR INTERRUPT: Enabled");
|
|
self.0.intenset.write(|w| w.txptrupd().set());
|
|
}
|
|
|
|
#[inline(always)]
|
|
fn enable_rx_ptr_interrupt(&self) {
|
|
trace!("RX PTR INTERRUPT: Enabled");
|
|
self.0.intenset.write(|w| w.rxptrupd().set());
|
|
}
|
|
|
|
#[inline(always)]
|
|
fn is_tx_ptr_updated(&self) -> bool {
|
|
self.0.events_txptrupd.read().bits() != 0
|
|
}
|
|
|
|
#[inline(always)]
|
|
fn is_rx_ptr_updated(&self) -> bool {
|
|
self.0.events_rxptrupd.read().bits() != 0
|
|
}
|
|
|
|
#[inline]
|
|
fn update_tx<S>(&self, buffer_ptr: *const [S]) -> Result<(), Error> {
|
|
let (ptr, maxcnt) = Self::validated_dma_parts(buffer_ptr)?;
|
|
self.0.rxtxd.maxcnt.write(|w| unsafe { w.bits(maxcnt) });
|
|
self.0.txd.ptr.write(|w| unsafe { w.ptr().bits(ptr) });
|
|
Ok(())
|
|
}
|
|
|
|
#[inline]
|
|
fn update_rx<S>(&self, buffer_ptr: *const [S]) -> Result<(), Error> {
|
|
let (ptr, maxcnt) = Self::validated_dma_parts(buffer_ptr)?;
|
|
self.0.rxtxd.maxcnt.write(|w| unsafe { w.bits(maxcnt) });
|
|
self.0.rxd.ptr.write(|w| unsafe { w.ptr().bits(ptr) });
|
|
Ok(())
|
|
}
|
|
|
|
fn validated_dma_parts<S>(buffer_ptr: *const [S]) -> Result<(u32, u32), Error> {
|
|
let (ptr, len) = slice_ptr_parts(buffer_ptr);
|
|
let ptr = ptr as u32;
|
|
let bytes_len = len * size_of::<S>();
|
|
let maxcnt = (bytes_len / size_of::<u32>()) as u32;
|
|
|
|
trace!("PTR={}, MAXCNT={}", ptr, maxcnt);
|
|
|
|
if ptr % 4 != 0 {
|
|
Err(Error::BufferMisaligned)
|
|
} else if bytes_len % 4 != 0 {
|
|
Err(Error::BufferLengthMisaligned)
|
|
} else if maxcnt as usize > EASY_DMA_SIZE {
|
|
Err(Error::BufferTooLong)
|
|
} else {
|
|
Ok((ptr, maxcnt))
|
|
}
|
|
}
|
|
}
|
|
|
|
/// Sample details
|
|
pub trait Sample: Sized + Copy + Default {
|
|
/// Width of this sample type.
|
|
const WIDTH: usize;
|
|
|
|
/// Scale of this sample.
|
|
const SCALE: Self;
|
|
}
|
|
|
|
impl Sample for i8 {
|
|
const WIDTH: usize = 8;
|
|
const SCALE: Self = 1 << (Self::WIDTH - 1);
|
|
}
|
|
|
|
impl Sample for i16 {
|
|
const WIDTH: usize = 16;
|
|
const SCALE: Self = 1 << (Self::WIDTH - 1);
|
|
}
|
|
|
|
impl Sample for i32 {
|
|
const WIDTH: usize = 24;
|
|
const SCALE: Self = 1 << (Self::WIDTH - 1);
|
|
}
|
|
|
|
/// A 4-bytes aligned buffer. Needed for DMA access.
|
|
#[derive(Clone, Copy)]
|
|
#[repr(align(4))]
|
|
pub struct AlignedBuffer<T: Sample, const N: usize>([T; N]);
|
|
|
|
impl<T: Sample, const N: usize> AlignedBuffer<T, N> {
|
|
/// Create a new `AlignedBuffer`.
|
|
pub fn new(array: [T; N]) -> Self {
|
|
Self(array)
|
|
}
|
|
}
|
|
|
|
impl<T: Sample, const N: usize> Default for AlignedBuffer<T, N> {
|
|
fn default() -> Self {
|
|
Self([T::default(); N])
|
|
}
|
|
}
|
|
|
|
impl<T: Sample, const N: usize> Deref for AlignedBuffer<T, N> {
|
|
type Target = [T];
|
|
fn deref(&self) -> &Self::Target {
|
|
self.0.as_slice()
|
|
}
|
|
}
|
|
|
|
impl<T: Sample, const N: usize> DerefMut for AlignedBuffer<T, N> {
|
|
fn deref_mut(&mut self) -> &mut Self::Target {
|
|
self.0.as_mut_slice()
|
|
}
|
|
}
|
|
|
|
/// Set of multiple buffers, for multi-buffering transfers.
|
|
pub struct MultiBuffering<S: Sample, const NB: usize, const NS: usize> {
|
|
buffers: [AlignedBuffer<S, NS>; NB],
|
|
index: usize,
|
|
}
|
|
|
|
impl<S: Sample, const NB: usize, const NS: usize> MultiBuffering<S, NB, NS> {
|
|
/// Create a new `MultiBuffering`.
|
|
pub fn new() -> Self {
|
|
assert!(NB > 1);
|
|
Self {
|
|
buffers: [AlignedBuffer::<S, NS>::default(); NB],
|
|
index: 0,
|
|
}
|
|
}
|
|
|
|
fn get(&self) -> &[S] {
|
|
&self.buffers[self.index]
|
|
}
|
|
|
|
fn get_mut(&mut self) -> &mut [S] {
|
|
&mut self.buffers[self.index]
|
|
}
|
|
|
|
/// Advance to use the next buffer and return a non mutable pointer to the previous one.
|
|
fn switch(&mut self) -> *const [S] {
|
|
let prev_index = self.index;
|
|
self.index = (self.index + 1) % NB;
|
|
self.buffers[prev_index].deref() as *const [S]
|
|
}
|
|
|
|
/// Advance to use the next buffer and return a mutable pointer to the previous one.
|
|
fn switch_mut(&mut self) -> *mut [S] {
|
|
let prev_index = self.index;
|
|
self.index = (self.index + 1) % NB;
|
|
self.buffers[prev_index].deref_mut() as *mut [S]
|
|
}
|
|
}
|
|
|
|
pub(crate) mod sealed {
|
|
use core::sync::atomic::AtomicBool;
|
|
|
|
use embassy_sync::waitqueue::AtomicWaker;
|
|
|
|
/// Peripheral static state
|
|
pub struct State {
|
|
pub started: AtomicBool,
|
|
pub rx_waker: AtomicWaker,
|
|
pub tx_waker: AtomicWaker,
|
|
pub stop_waker: AtomicWaker,
|
|
}
|
|
|
|
impl State {
|
|
pub const fn new() -> Self {
|
|
Self {
|
|
started: AtomicBool::new(false),
|
|
rx_waker: AtomicWaker::new(),
|
|
tx_waker: AtomicWaker::new(),
|
|
stop_waker: AtomicWaker::new(),
|
|
}
|
|
}
|
|
}
|
|
|
|
pub trait Instance {
|
|
fn regs() -> &'static crate::pac::i2s::RegisterBlock;
|
|
fn state() -> &'static State;
|
|
}
|
|
}
|
|
|
|
/// I2S peripheral instance.
|
|
pub trait Instance: Peripheral<P = Self> + sealed::Instance + 'static + Send {
|
|
/// Interrupt for this peripheral.
|
|
type Interrupt: interrupt::typelevel::Interrupt;
|
|
}
|
|
|
|
macro_rules! impl_i2s {
|
|
($type:ident, $pac_type:ident, $irq:ident) => {
|
|
impl crate::i2s::sealed::Instance for peripherals::$type {
|
|
fn regs() -> &'static crate::pac::i2s::RegisterBlock {
|
|
unsafe { &*pac::$pac_type::ptr() }
|
|
}
|
|
fn state() -> &'static crate::i2s::sealed::State {
|
|
static STATE: crate::i2s::sealed::State = crate::i2s::sealed::State::new();
|
|
&STATE
|
|
}
|
|
}
|
|
impl crate::i2s::Instance for peripherals::$type {
|
|
type Interrupt = crate::interrupt::typelevel::$irq;
|
|
}
|
|
};
|
|
}
|