329 lines
11 KiB
Rust
329 lines
11 KiB
Rust
use embassy_futures::yield_now;
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use embassy_time::Timer;
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use embedded_hal_1::digital::OutputPin;
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use futures::FutureExt;
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use crate::consts::*;
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use crate::slice8_mut;
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/// Custom Spi Trait that _only_ supports the bus operation of the cyw43
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/// Implementors are expected to hold the CS pin low during an operation.
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pub trait SpiBusCyw43 {
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/// Issues a write command on the bus
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/// First 32 bits of `word` are expected to be a cmd word
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async fn cmd_write(&mut self, write: &[u32]) -> u32;
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/// Issues a read command on the bus
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/// `write` is expected to be a 32 bit cmd word
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/// `read` will contain the response of the device
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/// Backplane reads have a response delay that produces one extra unspecified word at the beginning of `read`.
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/// Callers that want to read `n` word from the backplane, have to provide a slice that is `n+1` words long.
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async fn cmd_read(&mut self, write: u32, read: &mut [u32]) -> u32;
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/// Wait for events from the Device. A typical implementation would wait for the IRQ pin to be high.
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/// The default implementation always reports ready, resulting in active polling of the device.
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async fn wait_for_event(&mut self) {
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yield_now().await;
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}
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}
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pub(crate) struct Bus<PWR, SPI> {
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backplane_window: u32,
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pwr: PWR,
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spi: SPI,
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status: u32,
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}
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impl<PWR, SPI> Bus<PWR, SPI>
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where
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PWR: OutputPin,
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SPI: SpiBusCyw43,
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{
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pub(crate) fn new(pwr: PWR, spi: SPI) -> Self {
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Self {
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backplane_window: 0xAAAA_AAAA,
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pwr,
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spi,
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status: 0,
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}
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}
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pub async fn init(&mut self) {
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// Reset
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self.pwr.set_low().unwrap();
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Timer::after_millis(20).await;
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self.pwr.set_high().unwrap();
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Timer::after_millis(250).await;
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while self
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.read32_swapped(REG_BUS_TEST_RO)
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.inspect(|v| trace!("{:#x}", v))
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.await
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!= FEEDBEAD
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{}
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self.write32_swapped(REG_BUS_TEST_RW, TEST_PATTERN).await;
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let val = self.read32_swapped(REG_BUS_TEST_RW).await;
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trace!("{:#x}", val);
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assert_eq!(val, TEST_PATTERN);
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let val = self.read32_swapped(REG_BUS_CTRL).await;
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trace!("{:#010b}", (val & 0xff));
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// 32-bit word length, little endian (which is the default endianess).
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self.write32_swapped(
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REG_BUS_CTRL,
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WORD_LENGTH_32 | HIGH_SPEED | INTERRUPT_HIGH | WAKE_UP | STATUS_ENABLE | INTERRUPT_WITH_STATUS,
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)
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.await;
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let val = self.read8(FUNC_BUS, REG_BUS_CTRL).await;
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trace!("{:#b}", val);
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let val = self.read32(FUNC_BUS, REG_BUS_TEST_RO).await;
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trace!("{:#x}", val);
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assert_eq!(val, FEEDBEAD);
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let val = self.read32(FUNC_BUS, REG_BUS_TEST_RW).await;
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trace!("{:#x}", val);
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assert_eq!(val, TEST_PATTERN);
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}
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pub async fn wlan_read(&mut self, buf: &mut [u32], len_in_u8: u32) {
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let cmd = cmd_word(READ, INC_ADDR, FUNC_WLAN, 0, len_in_u8);
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let len_in_u32 = (len_in_u8 as usize + 3) / 4;
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self.status = self.spi.cmd_read(cmd, &mut buf[..len_in_u32]).await;
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}
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pub async fn wlan_write(&mut self, buf: &[u32]) {
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let cmd = cmd_word(WRITE, INC_ADDR, FUNC_WLAN, 0, buf.len() as u32 * 4);
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//TODO try to remove copy?
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let mut cmd_buf = [0_u32; 513];
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cmd_buf[0] = cmd;
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cmd_buf[1..][..buf.len()].copy_from_slice(buf);
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self.status = self.spi.cmd_write(&cmd_buf[..buf.len() + 1]).await;
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}
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#[allow(unused)]
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pub async fn bp_read(&mut self, mut addr: u32, mut data: &mut [u8]) {
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// It seems the HW force-aligns the addr
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// to 2 if data.len() >= 2
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// to 4 if data.len() >= 4
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// To simplify, enforce 4-align for now.
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assert!(addr % 4 == 0);
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// Backplane read buffer has one extra word for the response delay.
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let mut buf = [0u32; BACKPLANE_MAX_TRANSFER_SIZE / 4 + 1];
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while !data.is_empty() {
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// Ensure transfer doesn't cross a window boundary.
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let window_offs = addr & BACKPLANE_ADDRESS_MASK;
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let window_remaining = BACKPLANE_WINDOW_SIZE - window_offs as usize;
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let len = data.len().min(BACKPLANE_MAX_TRANSFER_SIZE).min(window_remaining);
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self.backplane_set_window(addr).await;
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let cmd = cmd_word(READ, INC_ADDR, FUNC_BACKPLANE, window_offs, len as u32);
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// round `buf` to word boundary, add one extra word for the response delay
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self.status = self.spi.cmd_read(cmd, &mut buf[..(len + 3) / 4 + 1]).await;
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// when writing out the data, we skip the response-delay byte
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data[..len].copy_from_slice(&slice8_mut(&mut buf[1..])[..len]);
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// Advance ptr.
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addr += len as u32;
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data = &mut data[len..];
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}
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}
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pub async fn bp_write(&mut self, mut addr: u32, mut data: &[u8]) {
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// It seems the HW force-aligns the addr
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// to 2 if data.len() >= 2
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// to 4 if data.len() >= 4
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// To simplify, enforce 4-align for now.
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assert!(addr % 4 == 0);
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let mut buf = [0u32; BACKPLANE_MAX_TRANSFER_SIZE / 4 + 1];
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while !data.is_empty() {
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// Ensure transfer doesn't cross a window boundary.
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let window_offs = addr & BACKPLANE_ADDRESS_MASK;
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let window_remaining = BACKPLANE_WINDOW_SIZE - window_offs as usize;
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let len = data.len().min(BACKPLANE_MAX_TRANSFER_SIZE).min(window_remaining);
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slice8_mut(&mut buf[1..])[..len].copy_from_slice(&data[..len]);
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self.backplane_set_window(addr).await;
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let cmd = cmd_word(WRITE, INC_ADDR, FUNC_BACKPLANE, window_offs, len as u32);
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buf[0] = cmd;
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self.status = self.spi.cmd_write(&buf[..(len + 3) / 4 + 1]).await;
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// Advance ptr.
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addr += len as u32;
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data = &data[len..];
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}
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}
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pub async fn bp_read8(&mut self, addr: u32) -> u8 {
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self.backplane_readn(addr, 1).await as u8
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}
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pub async fn bp_write8(&mut self, addr: u32, val: u8) {
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self.backplane_writen(addr, val as u32, 1).await
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}
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pub async fn bp_read16(&mut self, addr: u32) -> u16 {
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self.backplane_readn(addr, 2).await as u16
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}
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#[allow(unused)]
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pub async fn bp_write16(&mut self, addr: u32, val: u16) {
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self.backplane_writen(addr, val as u32, 2).await
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}
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#[allow(unused)]
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pub async fn bp_read32(&mut self, addr: u32) -> u32 {
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self.backplane_readn(addr, 4).await
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}
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pub async fn bp_write32(&mut self, addr: u32, val: u32) {
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self.backplane_writen(addr, val, 4).await
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}
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async fn backplane_readn(&mut self, addr: u32, len: u32) -> u32 {
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self.backplane_set_window(addr).await;
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let mut bus_addr = addr & BACKPLANE_ADDRESS_MASK;
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if len == 4 {
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bus_addr |= BACKPLANE_ADDRESS_32BIT_FLAG
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}
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self.readn(FUNC_BACKPLANE, bus_addr, len).await
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}
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async fn backplane_writen(&mut self, addr: u32, val: u32, len: u32) {
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self.backplane_set_window(addr).await;
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let mut bus_addr = addr & BACKPLANE_ADDRESS_MASK;
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if len == 4 {
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bus_addr |= BACKPLANE_ADDRESS_32BIT_FLAG
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}
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self.writen(FUNC_BACKPLANE, bus_addr, val, len).await
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}
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async fn backplane_set_window(&mut self, addr: u32) {
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let new_window = addr & !BACKPLANE_ADDRESS_MASK;
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if (new_window >> 24) as u8 != (self.backplane_window >> 24) as u8 {
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self.write8(
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FUNC_BACKPLANE,
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REG_BACKPLANE_BACKPLANE_ADDRESS_HIGH,
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(new_window >> 24) as u8,
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)
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.await;
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}
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if (new_window >> 16) as u8 != (self.backplane_window >> 16) as u8 {
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self.write8(
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FUNC_BACKPLANE,
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REG_BACKPLANE_BACKPLANE_ADDRESS_MID,
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(new_window >> 16) as u8,
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)
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.await;
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}
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if (new_window >> 8) as u8 != (self.backplane_window >> 8) as u8 {
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self.write8(
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FUNC_BACKPLANE,
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REG_BACKPLANE_BACKPLANE_ADDRESS_LOW,
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(new_window >> 8) as u8,
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)
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.await;
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}
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self.backplane_window = new_window;
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}
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pub async fn read8(&mut self, func: u32, addr: u32) -> u8 {
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self.readn(func, addr, 1).await as u8
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}
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pub async fn write8(&mut self, func: u32, addr: u32, val: u8) {
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self.writen(func, addr, val as u32, 1).await
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}
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pub async fn read16(&mut self, func: u32, addr: u32) -> u16 {
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self.readn(func, addr, 2).await as u16
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}
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#[allow(unused)]
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pub async fn write16(&mut self, func: u32, addr: u32, val: u16) {
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self.writen(func, addr, val as u32, 2).await
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}
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pub async fn read32(&mut self, func: u32, addr: u32) -> u32 {
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self.readn(func, addr, 4).await
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}
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#[allow(unused)]
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pub async fn write32(&mut self, func: u32, addr: u32, val: u32) {
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self.writen(func, addr, val, 4).await
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}
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async fn readn(&mut self, func: u32, addr: u32, len: u32) -> u32 {
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let cmd = cmd_word(READ, INC_ADDR, func, addr, len);
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let mut buf = [0; 2];
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// if we are reading from the backplane, we need an extra word for the response delay
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let len = if func == FUNC_BACKPLANE { 2 } else { 1 };
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self.status = self.spi.cmd_read(cmd, &mut buf[..len]).await;
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// if we read from the backplane, the result is in the second word, after the response delay
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if func == FUNC_BACKPLANE {
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buf[1]
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} else {
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buf[0]
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}
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}
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async fn writen(&mut self, func: u32, addr: u32, val: u32, len: u32) {
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let cmd = cmd_word(WRITE, INC_ADDR, func, addr, len);
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self.status = self.spi.cmd_write(&[cmd, val]).await;
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}
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async fn read32_swapped(&mut self, addr: u32) -> u32 {
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let cmd = cmd_word(READ, INC_ADDR, FUNC_BUS, addr, 4);
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let cmd = swap16(cmd);
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let mut buf = [0; 1];
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self.status = self.spi.cmd_read(cmd, &mut buf).await;
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swap16(buf[0])
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}
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async fn write32_swapped(&mut self, addr: u32, val: u32) {
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let cmd = cmd_word(WRITE, INC_ADDR, FUNC_BUS, addr, 4);
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let buf = [swap16(cmd), swap16(val)];
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self.status = self.spi.cmd_write(&buf).await;
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}
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pub async fn wait_for_event(&mut self) {
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self.spi.wait_for_event().await;
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}
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pub fn status(&self) -> u32 {
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self.status
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}
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}
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fn swap16(x: u32) -> u32 {
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x.rotate_left(16)
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}
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fn cmd_word(write: bool, incr: bool, func: u32, addr: u32, len: u32) -> u32 {
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(write as u32) << 31 | (incr as u32) << 30 | (func & 0b11) << 28 | (addr & 0x1FFFF) << 11 | (len & 0x7FF)
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}
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