362 lines
11 KiB
Rust
362 lines
11 KiB
Rust
use core::future::Future;
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use core::sync::atomic::{fence, Ordering};
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use core::task::{Poll, Waker};
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use embassy::interrupt::{Interrupt, InterruptExt};
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use embassy::waitqueue::AtomicWaker;
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use embassy_hal_common::drop::OnDrop;
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use futures::future::poll_fn;
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use crate::interrupt;
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use crate::pac;
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use crate::pac::dma::{regs, vals};
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use crate::rcc::sealed::RccPeripheral;
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use super::{Channel, Request};
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const CH_COUNT: usize = pac::peripheral_count!(DMA) * 8;
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struct State {
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ch_wakers: [AtomicWaker; CH_COUNT],
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}
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impl State {
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const fn new() -> Self {
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const AW: AtomicWaker = AtomicWaker::new();
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Self {
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ch_wakers: [AW; CH_COUNT],
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}
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}
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}
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static STATE: State = State::new();
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//async unsafe fn do_transfer(ch: &mut impl Channel, ch_func: u8, src: *const u8, dst: &mut [u8]) {
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#[allow(unused)]
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pub(crate) unsafe fn do_transfer(
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dma: pac::dma::Dma,
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channel_number: u8,
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state_number: u8,
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request: Request,
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dir: vals::Dir,
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peri_addr: *const u8,
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mem_addr: *mut u8,
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mem_len: usize,
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incr_mem: bool,
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#[cfg(dmamux)] dmamux_regs: pac::dmamux::Dmamux,
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#[cfg(dmamux)] dmamux_ch_num: u8,
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) -> impl Future<Output = ()> {
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// ndtr is max 16 bits.
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assert!(mem_len <= 0xFFFF);
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// Reset status
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let isrn = channel_number as usize / 4;
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let isrbit = channel_number as usize % 4;
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_reset_status(&dma, isrn, isrbit);
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let ch = dma.st(channel_number as _);
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let on_drop = OnDrop::new(move || unsafe {
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_stop(&dma, channel_number);
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});
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// "Preceding reads and writes cannot be moved past subsequent writes."
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fence(Ordering::Release);
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// Actually start the transaction
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_start_transfer(
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request,
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dir,
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peri_addr,
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mem_addr,
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mem_len,
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incr_mem,
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ch,
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#[cfg(dmamux)]
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dmamux_regs,
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#[cfg(dmamux)]
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dmamux_ch_num,
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);
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async move {
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let res = poll_fn(|cx| {
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let n = state_number as usize;
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STATE.ch_wakers[n].register(cx.waker());
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let isr = dma.isr(isrn).read();
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// TODO handle error
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assert!(!isr.teif(isrbit));
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if isr.tcif(isrbit) {
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Poll::Ready(())
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} else {
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Poll::Pending
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}
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})
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.await;
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drop(on_drop)
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}
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}
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unsafe fn _reset_status(dma: &crate::pac::dma::Dma, isrn: usize, isrbit: usize) {
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dma.ifcr(isrn).write(|w| {
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w.set_tcif(isrbit, true);
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w.set_teif(isrbit, true);
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});
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}
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unsafe fn _start_transfer(
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request: Request,
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dir: vals::Dir,
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peri_addr: *const u8,
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mem_addr: *mut u8,
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mem_len: usize,
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incr_mem: bool,
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ch: crate::pac::dma::St,
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#[cfg(dmamux)] dmamux_regs: pac::dmamux::Dmamux,
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#[cfg(dmamux)] dmamux_ch_num: u8,
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) {
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#[cfg(dmamux)]
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super::dmamux::configure_dmamux(dmamux_regs, dmamux_ch_num, request);
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// "Preceding reads and writes cannot be moved past subsequent writes."
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fence(Ordering::Release);
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ch.par().write_value(peri_addr as u32);
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ch.m0ar().write_value(mem_addr as u32);
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ch.ndtr().write_value(regs::Ndtr(mem_len as _));
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ch.cr().write(|w| {
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w.set_dir(dir);
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w.set_msize(vals::Size::BITS8);
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w.set_psize(vals::Size::BITS8);
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if incr_mem {
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w.set_minc(vals::Inc::INCREMENTED);
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} else {
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w.set_minc(vals::Inc::FIXED);
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}
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w.set_pinc(vals::Inc::FIXED);
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w.set_teie(true);
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w.set_tcie(true);
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#[cfg(dma_v1)]
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w.set_trbuff(true);
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#[cfg(dma_v2)]
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w.set_chsel(request);
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w.set_en(true);
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});
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}
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/// Stops the DMA channel.
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unsafe fn _stop(dma: &pac::dma::Dma, ch: u8) {
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// get a handle on the channel itself
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let ch = dma.st(ch as _);
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// Disable the channel and interrupts with the default value.
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ch.cr().write(|_| ());
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// Wait for the transfer to complete when it was ongoing.
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while ch.cr().read().en() {}
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// "Subsequent reads and writes cannot be moved ahead of preceding reads."
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fence(Ordering::Acquire);
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}
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/// Gets the running status of the channel
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unsafe fn _is_stopped(dma: &pac::dma::Dma, ch: u8) -> bool {
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// get a handle on the channel itself
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let ch = dma.st(ch as _);
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// Wait for the transfer to complete when it was ongoing.
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ch.cr().read().en()
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}
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/// Gets the total remaining transfers for the channel
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/// Note: this will be zero for transfers that completed without cancellation.
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unsafe fn _get_remaining_transfers(dma: &pac::dma::Dma, ch: u8) -> u16 {
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// get a handle on the channel itself
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let ch = dma.st(ch as _);
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// read the remaining transfer count. If this is zero, the transfer completed fully.
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ch.ndtr().read().ndt()
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}
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/// Sets the waker for the specified DMA channel
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unsafe fn _set_waker(_dma: &pac::dma::Dma, state_number: u8, waker: &Waker) {
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let n = state_number as usize;
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STATE.ch_wakers[n].register(waker);
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}
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macro_rules! dma_num {
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(DMA1) => {
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0
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};
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(DMA2) => {
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1
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};
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}
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unsafe fn on_irq() {
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pac::peripherals! {
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(dma, $dma:ident) => {
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for isrn in 0..2 {
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let isr = pac::$dma.isr(isrn).read();
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for chn in 0..4 {
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let cr = pac::$dma.st(isrn * 4 + chn).cr();
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if isr.tcif(chn) && cr.read().tcie() {
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cr.write(|_| ()); // Disable channel interrupts with the default value.
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let n = dma_num!($dma) * 8 + isrn * 4 + chn;
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STATE.ch_wakers[n].wake();
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}
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}
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}
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};
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}
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}
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/// safety: must be called only once
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pub(crate) unsafe fn init() {
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pac::interrupts! {
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($peri:ident, dma, $block:ident, $signal_name:ident, $irq:ident) => {
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interrupt::$irq::steal().enable();
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};
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}
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pac::peripherals! {
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(dma, $peri:ident) => {
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crate::peripherals::$peri::enable();
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};
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}
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}
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pac::dma_channels! {
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($channel_peri:ident, $dma_peri:ident, dma, $channel_num:expr, $dmamux:tt) => {
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impl crate::dma::sealed::Channel for crate::peripherals::$channel_peri {}
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impl Channel for crate::peripherals::$channel_peri
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{
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type ReadFuture<'a> = impl Future<Output = ()> + 'a;
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type WriteFuture<'a> = impl Future<Output = ()> + 'a;
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fn read<'a>(
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&'a mut self,
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request: Request,
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src: *mut u8,
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buf: &'a mut [u8],
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) -> Self::ReadFuture<'a> {
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unsafe {
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do_transfer(
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crate::pac::$dma_peri,
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$channel_num,
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(dma_num!($dma_peri) * 8) + $channel_num,
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request,
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vals::Dir::PERIPHERALTOMEMORY,
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src,
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buf.as_mut_ptr(),
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buf.len(),
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true,
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#[cfg(dmamux)]
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<Self as super::dmamux::sealed::MuxChannel>::DMAMUX_REGS,
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#[cfg(dmamux)]
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<Self as super::dmamux::sealed::MuxChannel>::DMAMUX_CH_NUM,
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)
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}
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}
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fn write<'a>(
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&'a mut self,
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request: Request,
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buf: &'a [u8],
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dst: *mut u8,
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) -> Self::WriteFuture<'a> {
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unsafe {
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do_transfer(
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crate::pac::$dma_peri,
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$channel_num,
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(dma_num!($dma_peri) * 8) + $channel_num,
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request,
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vals::Dir::MEMORYTOPERIPHERAL,
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dst,
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buf.as_ptr() as *mut u8,
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buf.len(),
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true,
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#[cfg(dmamux)]
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<Self as super::dmamux::sealed::MuxChannel>::DMAMUX_REGS,
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#[cfg(dmamux)]
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<Self as super::dmamux::sealed::MuxChannel>::DMAMUX_CH_NUM,
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)
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}
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}
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fn write_x<'a>(
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&'a mut self,
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request: Request,
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word: &u8,
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num: usize,
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dst: *mut u8,
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) -> Self::WriteFuture<'a> {
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unsafe {
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do_transfer(
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crate::pac::$dma_peri,
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$channel_num,
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(dma_num!($dma_peri) * 8) + $channel_num,
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request,
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vals::Dir::MEMORYTOPERIPHERAL,
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dst,
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word as *const u8 as *mut u8,
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num,
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false,
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#[cfg(dmamux)]
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<Self as super::dmamux::sealed::MuxChannel>::DMAMUX_REGS,
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#[cfg(dmamux)]
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<Self as super::dmamux::sealed::MuxChannel>::DMAMUX_CH_NUM,
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)
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}
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}
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fn stop <'a>(&'a mut self){
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unsafe {_stop(&crate::pac::$dma_peri, $channel_num);}
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}
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fn is_stopped<'a>(&'a self) -> bool {
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unsafe {_is_stopped(&crate::pac::$dma_peri, $channel_num)}
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}
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fn remaining_transfers<'a>(&'a mut self) -> u16 {
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unsafe {_get_remaining_transfers(&crate::pac::$dma_peri, $channel_num)}
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}
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fn set_waker<'a>(&'a mut self, waker: &'a Waker) {
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unsafe {_set_waker(&crate::pac::$dma_peri, $channel_num, waker )}
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}
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fn start<'a>(&'a mut self, request: Request, buf: &'a [u8], dst: *mut u8){
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unsafe {
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let isrn = $channel_num as usize / 4;
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let isrbit = $channel_num as usize % 4;
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_reset_status(&crate::pac::$dma_peri, isrn, isrbit);
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_start_transfer(
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request,
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vals::Dir::MEMORYTOPERIPHERAL,
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dst,
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buf.as_ptr() as *mut u8,
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buf.len(),
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true,
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crate::pac::$dma_peri.st($channel_num as _),
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#[cfg(dmamux)]
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<Self as super::dmamux::sealed::MuxChannel>::DMAMUX_REGS,
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#[cfg(dmamux)]
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<Self as super::dmamux::sealed::MuxChannel>::DMAMUX_CH_NUM,
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)
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}
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}
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}
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};
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}
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pac::interrupts! {
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($peri:ident, dma, $block:ident, $signal_name:ident, $irq:ident) => {
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#[crate::interrupt]
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unsafe fn $irq () {
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on_irq()
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}
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};
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}
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