408 lines
10 KiB
Rust
408 lines
10 KiB
Rust
use stm32_metapac::rcc::vals::{Msirange, Msirgsel, Pllm, Pllsrc, Sw};
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pub use super::bus::{AHBPrescaler, APBPrescaler};
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use crate::pac::{FLASH, RCC};
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use crate::rcc::{set_freqs, Clocks};
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use crate::time::Hertz;
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/// HSI speed
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pub const HSI_FREQ: Hertz = Hertz(16_000_000);
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/// LSI speed
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pub const LSI_FREQ: Hertz = Hertz(32_000);
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pub use crate::pac::pwr::vals::Vos as VoltageScale;
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#[derive(Copy, Clone)]
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pub enum ClockSrc {
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MSI(MSIRange),
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HSE(Hertz),
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HSI16,
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PLL1R(PllSrc, PllM, PllN, PllClkDiv),
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}
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#[derive(Clone, Copy, Debug)]
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pub enum PllSrc {
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MSI(MSIRange),
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HSE(Hertz),
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HSI16,
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}
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impl Into<Pllsrc> for PllSrc {
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fn into(self) -> Pllsrc {
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match self {
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PllSrc::MSI(..) => Pllsrc::MSIS,
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PllSrc::HSE(..) => Pllsrc::HSE,
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PllSrc::HSI16 => Pllsrc::HSI16,
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}
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}
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}
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seq_macro::seq!(N in 2..=128 {
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#[derive(Copy, Clone, Debug)]
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pub enum PllClkDiv {
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NotDivided,
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#(
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Div~N = (N-1),
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)*
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}
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impl PllClkDiv {
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fn to_div(&self) -> u8 {
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match self {
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PllClkDiv::NotDivided => 1,
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#(
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PllClkDiv::Div~N => N + 1,
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)*
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}
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}
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}
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});
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impl Into<u8> for PllClkDiv {
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fn into(self) -> u8 {
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(self as u8) + 1
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}
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}
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seq_macro::seq!(N in 4..=512 {
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#[derive(Copy, Clone, Debug)]
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pub enum PllN {
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NotMultiplied,
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#(
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Mul~N = N-1,
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)*
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}
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impl PllN {
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fn to_mul(&self) -> u16 {
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match self {
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PllN::NotMultiplied => 1,
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#(
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PllN::Mul~N => N + 1,
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)*
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}
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}
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}
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});
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impl Into<u16> for PllN {
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fn into(self) -> u16 {
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(self as u16) + 1
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}
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}
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// Pre-division
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#[derive(Copy, Clone, Debug)]
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pub enum PllM {
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NotDivided = 0b0000,
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Div2 = 0b0001,
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Div3 = 0b0010,
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Div4 = 0b0011,
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Div5 = 0b0100,
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Div6 = 0b0101,
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Div7 = 0b0110,
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Div8 = 0b0111,
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Div9 = 0b1000,
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Div10 = 0b1001,
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Div11 = 0b1010,
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Div12 = 0b1011,
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Div13 = 0b1100,
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Div14 = 0b1101,
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Div15 = 0b1110,
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Div16 = 0b1111,
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}
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impl Into<Pllm> for PllM {
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fn into(self) -> Pllm {
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Pllm::from_bits(self as u8)
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}
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}
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impl Into<Sw> for ClockSrc {
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fn into(self) -> Sw {
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match self {
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ClockSrc::MSI(..) => Sw::MSIS,
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ClockSrc::HSE(..) => Sw::HSE,
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ClockSrc::HSI16 => Sw::HSI16,
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ClockSrc::PLL1R(..) => Sw::PLL1_R,
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}
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}
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}
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#[derive(Debug, Copy, Clone)]
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pub enum MSIRange {
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Range48mhz = 48_000_000,
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Range24mhz = 24_000_000,
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Range16mhz = 16_000_000,
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Range12mhz = 12_000_000,
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Range4mhz = 4_000_000,
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Range2mhz = 2_000_000,
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Range1_33mhz = 1_330_000,
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Range1mhz = 1_000_000,
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Range3_072mhz = 3_072_000,
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Range1_536mhz = 1_536_000,
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Range1_024mhz = 1_024_000,
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Range768khz = 768_000,
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Range400khz = 400_000,
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Range200khz = 200_000,
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Range133khz = 133_000,
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Range100khz = 100_000,
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}
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impl Into<u32> for MSIRange {
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fn into(self) -> u32 {
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self as u32
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}
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}
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impl Into<Msirange> for MSIRange {
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fn into(self) -> Msirange {
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match self {
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MSIRange::Range48mhz => Msirange::RANGE_48MHZ,
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MSIRange::Range24mhz => Msirange::RANGE_24MHZ,
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MSIRange::Range16mhz => Msirange::RANGE_16MHZ,
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MSIRange::Range12mhz => Msirange::RANGE_12MHZ,
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MSIRange::Range4mhz => Msirange::RANGE_4MHZ,
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MSIRange::Range2mhz => Msirange::RANGE_2MHZ,
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MSIRange::Range1_33mhz => Msirange::RANGE_1_33MHZ,
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MSIRange::Range1mhz => Msirange::RANGE_1MHZ,
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MSIRange::Range3_072mhz => Msirange::RANGE_3_072MHZ,
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MSIRange::Range1_536mhz => Msirange::RANGE_1_536MHZ,
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MSIRange::Range1_024mhz => Msirange::RANGE_1_024MHZ,
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MSIRange::Range768khz => Msirange::RANGE_768KHZ,
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MSIRange::Range400khz => Msirange::RANGE_400KHZ,
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MSIRange::Range200khz => Msirange::RANGE_200KHZ,
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MSIRange::Range133khz => Msirange::RANGE_133KHZ,
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MSIRange::Range100khz => Msirange::RANGE_100KHZ,
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}
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}
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}
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impl Default for MSIRange {
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fn default() -> Self {
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MSIRange::Range4mhz
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}
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}
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#[derive(Copy, Clone)]
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pub struct Config {
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pub mux: ClockSrc,
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pub ahb_pre: AHBPrescaler,
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pub apb1_pre: APBPrescaler,
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pub apb2_pre: APBPrescaler,
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pub apb3_pre: APBPrescaler,
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pub hsi48: bool,
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}
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impl Default for Config {
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fn default() -> Self {
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Self {
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mux: ClockSrc::MSI(MSIRange::default()),
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ahb_pre: AHBPrescaler::DIV1,
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apb1_pre: APBPrescaler::DIV1,
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apb2_pre: APBPrescaler::DIV1,
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apb3_pre: APBPrescaler::DIV1,
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hsi48: false,
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}
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}
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}
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pub(crate) unsafe fn init(config: Config) {
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let sys_clk = match config.mux {
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ClockSrc::MSI(range) => {
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RCC.icscr1().modify(|w| {
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let bits: Msirange = range.into();
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w.set_msisrange(bits);
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w.set_msirgsel(Msirgsel::RCC_ICSCR1);
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});
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RCC.cr().write(|w| {
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w.set_msipllen(false);
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w.set_msison(true);
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});
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while !RCC.cr().read().msisrdy() {}
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range.into()
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}
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ClockSrc::HSE(freq) => {
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RCC.cr().write(|w| w.set_hseon(true));
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while !RCC.cr().read().hserdy() {}
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freq.0
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}
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ClockSrc::HSI16 => {
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RCC.cr().write(|w| w.set_hsion(true));
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while !RCC.cr().read().hsirdy() {}
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HSI_FREQ.0
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}
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ClockSrc::PLL1R(src, m, n, div) => {
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let freq = match src {
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PllSrc::MSI(_) => {
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// TODO: enable MSI
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MSIRange::default().into()
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}
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PllSrc::HSE(hertz) => {
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// TODO: enable HSE
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hertz.0
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}
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PllSrc::HSI16 => {
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RCC.cr().write(|w| w.set_hsion(true));
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while !RCC.cr().read().hsirdy() {}
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HSI_FREQ.0
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}
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};
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// disable
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RCC.cr().modify(|w| w.set_pllon(0, false));
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while RCC.cr().read().pllrdy(0) {}
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let vco = freq * n as u8 as u32;
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let pll_ck = vco / (div as u8 as u32 + 1);
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RCC.pll1cfgr().write(|w| {
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w.set_pllm(m.into());
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w.set_pllsrc(src.into());
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w.set_pllren(true);
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});
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RCC.pll1divr().modify(|w| {
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w.set_pllr(div.to_div());
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w.set_plln(n.to_mul());
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});
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// Enable PLL
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RCC.cr().modify(|w| w.set_pllon(0, true));
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while !RCC.cr().read().pllrdy(0) {}
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pll_ck
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}
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};
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if config.hsi48 {
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RCC.cr().modify(|w| w.set_hsi48on(true));
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while !RCC.cr().read().hsi48rdy() {}
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}
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// TODO make configurable
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let power_vos = VoltageScale::RANGE3;
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// states and programming delay
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let wait_states = match power_vos {
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// VOS 1 range VCORE 1.26V - 1.40V
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VoltageScale::RANGE1 => {
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if sys_clk < 32_000_000 {
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0
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} else if sys_clk < 64_000_000 {
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1
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} else if sys_clk < 96_000_000 {
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2
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} else if sys_clk < 128_000_000 {
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3
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} else {
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4
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}
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}
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// VOS 2 range VCORE 1.15V - 1.26V
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VoltageScale::RANGE2 => {
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if sys_clk < 30_000_000 {
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0
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} else if sys_clk < 60_000_000 {
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1
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} else if sys_clk < 90_000_000 {
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2
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} else {
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3
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}
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}
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// VOS 3 range VCORE 1.05V - 1.15V
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VoltageScale::RANGE3 => {
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if sys_clk < 24_000_000 {
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0
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} else if sys_clk < 48_000_000 {
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1
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} else {
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2
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}
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}
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// VOS 4 range VCORE 0.95V - 1.05V
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VoltageScale::RANGE4 => {
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if sys_clk < 12_000_000 {
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0
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} else {
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1
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}
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}
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};
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FLASH.acr().modify(|w| {
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w.set_latency(wait_states);
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});
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RCC.cfgr1().modify(|w| {
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w.set_sw(config.mux.into());
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});
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RCC.cfgr2().modify(|w| {
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w.set_hpre(config.ahb_pre.into());
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w.set_ppre1(config.apb1_pre.into());
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w.set_ppre2(config.apb2_pre.into());
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});
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RCC.cfgr3().modify(|w| {
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w.set_ppre3(config.apb3_pre.into());
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});
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let ahb_freq: u32 = match config.ahb_pre {
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AHBPrescaler::DIV1 => sys_clk,
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pre => {
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let pre: u8 = pre.into();
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let pre = 1 << (pre as u32 - 7);
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sys_clk / pre
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}
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};
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let (apb1_freq, apb1_tim_freq) = match config.apb1_pre {
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APBPrescaler::DIV1 => (ahb_freq, ahb_freq),
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pre => {
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let pre: u8 = pre.into();
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let pre: u8 = 1 << (pre - 3);
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let freq = ahb_freq / pre as u32;
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(freq, freq * 2)
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}
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};
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let (apb2_freq, apb2_tim_freq) = match config.apb2_pre {
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APBPrescaler::DIV1 => (ahb_freq, ahb_freq),
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pre => {
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let pre: u8 = pre.into();
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let pre: u8 = 1 << (pre - 3);
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let freq = ahb_freq / pre as u32;
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(freq, freq * 2)
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}
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};
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let (apb3_freq, _apb3_tim_freq) = match config.apb3_pre {
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APBPrescaler::DIV1 => (ahb_freq, ahb_freq),
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pre => {
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let pre: u8 = pre.into();
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let pre: u8 = 1 << (pre - 3);
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let freq = ahb_freq / pre as u32;
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(freq, freq * 2)
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}
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};
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set_freqs(Clocks {
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sys: Hertz(sys_clk),
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ahb1: Hertz(ahb_freq),
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ahb2: Hertz(ahb_freq),
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ahb3: Hertz(ahb_freq),
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apb1: Hertz(apb1_freq),
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apb2: Hertz(apb2_freq),
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apb3: Hertz(apb3_freq),
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apb1_tim: Hertz(apb1_tim_freq),
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apb2_tim: Hertz(apb2_tim_freq),
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});
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}
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