356 lines
7.5 KiB
Rust
356 lines
7.5 KiB
Rust
#[allow(unused_imports)]
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#[rustfmt::skip]
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pub mod pac {
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// The nRF5340 has a secure and non-secure (NS) mode.
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// To avoid cfg spam, we remove _ns or _s suffixes here.
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#[doc(no_inline)]
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pub use nrf5340_net_pac::{
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interrupt,
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Interrupt,
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Peripherals,
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aar_ns as aar,
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acl_ns as acl,
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appmutex_ns as appmutex,
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ccm_ns as ccm,
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clock_ns as clock,
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cti_ns as cti,
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ctrlap_ns as ctrlap,
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dcnf_ns as dcnf,
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dppic_ns as dppic,
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ecb_ns as ecb,
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egu0_ns as egu0,
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ficr_ns as ficr,
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gpiote_ns as gpiote,
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ipc_ns as ipc,
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nvmc_ns as nvmc,
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p0_ns as p0,
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power_ns as power,
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radio_ns as radio,
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reset_ns as reset,
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rng_ns as rng,
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rtc0_ns as rtc0,
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spim0_ns as spim0,
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spis0_ns as spis0,
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swi0_ns as swi0,
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temp_ns as temp,
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timer0_ns as timer0,
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twim0_ns as twim0,
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twis0_ns as twis0,
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uarte0_ns as uarte0,
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uicr_ns as uicr,
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vmc_ns as vmc,
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vreqctrl_ns as vreqctrl,
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wdt_ns as wdt,
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AAR_NS as AAR,
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ACL_NS as ACL,
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APPMUTEX_NS as APPMUTEX,
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APPMUTEX_S as APPMUTEX_S,
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CBP as CBP,
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CCM_NS as CCM,
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CLOCK_NS as CLOCK,
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CPUID as CPUID,
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CTI_NS as CTI,
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CTRLAP_NS as CTRLAP,
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DCB as DCB,
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DCNF_NS as DCNF,
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DPPIC_NS as DPPIC,
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DWT as DWT,
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ECB_NS as ECB,
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EGU0_NS as EGU0,
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FICR_NS as FICR,
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FPB as FPB,
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GPIOTE_NS as GPIOTE,
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IPC_NS as IPC,
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ITM as ITM,
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MPU as MPU,
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NVIC as NVIC,
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NVMC_NS as NVMC,
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P0_NS as P0,
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P1_NS as P1,
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POWER_NS as POWER,
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RADIO_NS as RADIO,
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RESET_NS as RESET,
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RNG_NS as RNG,
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RTC0_NS as RTC0,
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RTC1_NS as RTC1,
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SCB as SCB,
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SPIM0_NS as SPIM0,
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SPIS0_NS as SPIS0,
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SWI0_NS as SWI0,
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SWI1_NS as SWI1,
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SWI2_NS as SWI2,
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SWI3_NS as SWI3,
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SYST as SYST,
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TEMP_NS as TEMP,
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TIMER0_NS as TIMER0,
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TIMER1_NS as TIMER1,
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TIMER2_NS as TIMER2,
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TPIU as TPIU,
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TWIM0_NS as TWIM0,
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TWIS0_NS as TWIS0,
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UARTE0_NS as UARTE0,
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UICR_NS as UICR,
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VMC_NS as VMC,
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VREQCTRL_NS as VREQCTRL,
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WDT_NS as WDT,
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};
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}
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/// The maximum buffer size that the EasyDMA can send/recv in one operation.
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pub const EASY_DMA_SIZE: usize = (1 << 16) - 1;
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pub const FORCE_COPY_BUFFER_SIZE: usize = 1024;
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embassy_hal_common::peripherals! {
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// RTC
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RTC0,
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RTC1,
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// WDT
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WDT,
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// UARTE, TWI & SPI
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UARTETWISPI0,
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UARTETWISPI1,
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UARTETWISPI2,
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UARTETWISPI3,
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// SAADC
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SAADC,
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// PWM
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PWM0,
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PWM1,
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PWM2,
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PWM3,
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// TIMER
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TIMER0,
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TIMER1,
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TIMER2,
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// GPIOTE
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GPIOTE_CH0,
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GPIOTE_CH1,
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GPIOTE_CH2,
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GPIOTE_CH3,
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GPIOTE_CH4,
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GPIOTE_CH5,
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GPIOTE_CH6,
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GPIOTE_CH7,
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// PPI
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PPI_CH0,
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PPI_CH1,
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PPI_CH2,
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PPI_CH3,
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PPI_CH4,
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PPI_CH5,
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PPI_CH6,
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PPI_CH7,
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PPI_CH8,
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PPI_CH9,
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PPI_CH10,
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PPI_CH11,
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PPI_CH12,
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PPI_CH13,
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PPI_CH14,
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PPI_CH15,
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PPI_CH16,
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PPI_CH17,
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PPI_CH18,
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PPI_CH19,
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PPI_CH20,
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PPI_CH21,
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PPI_CH22,
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PPI_CH23,
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PPI_CH24,
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PPI_CH25,
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PPI_CH26,
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PPI_CH27,
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PPI_CH28,
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PPI_CH29,
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PPI_CH30,
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PPI_CH31,
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PPI_GROUP0,
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PPI_GROUP1,
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PPI_GROUP2,
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PPI_GROUP3,
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PPI_GROUP4,
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PPI_GROUP5,
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// GPIO port 0
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P0_00,
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P0_01,
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P0_02,
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P0_03,
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P0_04,
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P0_05,
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P0_06,
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P0_07,
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P0_08,
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P0_09,
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P0_10,
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P0_11,
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P0_12,
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P0_13,
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P0_14,
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P0_15,
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P0_16,
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P0_17,
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P0_18,
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P0_19,
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P0_20,
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P0_21,
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P0_22,
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P0_23,
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P0_24,
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P0_25,
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P0_26,
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P0_27,
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P0_28,
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P0_29,
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P0_30,
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P0_31,
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// GPIO port 1
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P1_00,
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P1_01,
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P1_02,
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P1_03,
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P1_04,
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P1_05,
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P1_06,
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P1_07,
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P1_08,
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P1_09,
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P1_10,
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P1_11,
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P1_12,
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P1_13,
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P1_14,
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P1_15,
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}
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impl_uarte!(UARTETWISPI0, UARTE0, SERIAL0);
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impl_spim!(UARTETWISPI0, SPIM0, SERIAL0);
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impl_twim!(UARTETWISPI0, TWIM0, SERIAL0);
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impl_timer!(TIMER0, TIMER0, TIMER0);
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impl_timer!(TIMER1, TIMER1, TIMER1);
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impl_timer!(TIMER2, TIMER2, TIMER2);
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impl_pin!(P0_00, 0, 0);
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impl_pin!(P0_01, 0, 1);
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impl_pin!(P0_02, 0, 2);
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impl_pin!(P0_03, 0, 3);
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impl_pin!(P0_04, 0, 4);
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impl_pin!(P0_05, 0, 5);
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impl_pin!(P0_06, 0, 6);
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impl_pin!(P0_07, 0, 7);
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impl_pin!(P0_08, 0, 8);
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impl_pin!(P0_09, 0, 9);
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impl_pin!(P0_10, 0, 10);
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impl_pin!(P0_11, 0, 11);
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impl_pin!(P0_12, 0, 12);
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impl_pin!(P0_13, 0, 13);
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impl_pin!(P0_14, 0, 14);
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impl_pin!(P0_15, 0, 15);
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impl_pin!(P0_16, 0, 16);
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impl_pin!(P0_17, 0, 17);
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impl_pin!(P0_18, 0, 18);
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impl_pin!(P0_19, 0, 19);
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impl_pin!(P0_20, 0, 20);
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impl_pin!(P0_21, 0, 21);
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impl_pin!(P0_22, 0, 22);
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impl_pin!(P0_23, 0, 23);
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impl_pin!(P0_24, 0, 24);
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impl_pin!(P0_25, 0, 25);
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impl_pin!(P0_26, 0, 26);
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impl_pin!(P0_27, 0, 27);
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impl_pin!(P0_28, 0, 28);
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impl_pin!(P0_29, 0, 29);
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impl_pin!(P0_30, 0, 30);
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impl_pin!(P0_31, 0, 31);
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impl_pin!(P1_00, 1, 0);
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impl_pin!(P1_01, 1, 1);
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impl_pin!(P1_02, 1, 2);
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impl_pin!(P1_03, 1, 3);
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impl_pin!(P1_04, 1, 4);
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impl_pin!(P1_05, 1, 5);
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impl_pin!(P1_06, 1, 6);
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impl_pin!(P1_07, 1, 7);
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impl_pin!(P1_08, 1, 8);
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impl_pin!(P1_09, 1, 9);
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impl_pin!(P1_10, 1, 10);
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impl_pin!(P1_11, 1, 11);
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impl_pin!(P1_12, 1, 12);
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impl_pin!(P1_13, 1, 13);
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impl_pin!(P1_14, 1, 14);
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impl_pin!(P1_15, 1, 15);
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impl_ppi_channel!(PPI_CH0, 0 => configurable);
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impl_ppi_channel!(PPI_CH1, 1 => configurable);
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impl_ppi_channel!(PPI_CH2, 2 => configurable);
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impl_ppi_channel!(PPI_CH3, 3 => configurable);
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impl_ppi_channel!(PPI_CH4, 4 => configurable);
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impl_ppi_channel!(PPI_CH5, 5 => configurable);
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impl_ppi_channel!(PPI_CH6, 6 => configurable);
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impl_ppi_channel!(PPI_CH7, 7 => configurable);
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impl_ppi_channel!(PPI_CH8, 8 => configurable);
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impl_ppi_channel!(PPI_CH9, 9 => configurable);
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impl_ppi_channel!(PPI_CH10, 10 => configurable);
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impl_ppi_channel!(PPI_CH11, 11 => configurable);
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impl_ppi_channel!(PPI_CH12, 12 => configurable);
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impl_ppi_channel!(PPI_CH13, 13 => configurable);
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impl_ppi_channel!(PPI_CH14, 14 => configurable);
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impl_ppi_channel!(PPI_CH15, 15 => configurable);
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impl_ppi_channel!(PPI_CH16, 16 => configurable);
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impl_ppi_channel!(PPI_CH17, 17 => configurable);
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impl_ppi_channel!(PPI_CH18, 18 => configurable);
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impl_ppi_channel!(PPI_CH19, 19 => configurable);
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impl_ppi_channel!(PPI_CH20, 20 => configurable);
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impl_ppi_channel!(PPI_CH21, 21 => configurable);
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impl_ppi_channel!(PPI_CH22, 22 => configurable);
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impl_ppi_channel!(PPI_CH23, 23 => configurable);
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impl_ppi_channel!(PPI_CH24, 24 => configurable);
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impl_ppi_channel!(PPI_CH25, 25 => configurable);
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impl_ppi_channel!(PPI_CH26, 26 => configurable);
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impl_ppi_channel!(PPI_CH27, 27 => configurable);
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impl_ppi_channel!(PPI_CH28, 28 => configurable);
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impl_ppi_channel!(PPI_CH29, 29 => configurable);
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impl_ppi_channel!(PPI_CH30, 30 => configurable);
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impl_ppi_channel!(PPI_CH31, 31 => configurable);
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pub mod irqs {
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use embassy_cortex_m::interrupt::_export::declare;
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use crate::pac::Interrupt as InterruptEnum;
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declare!(CLOCK_POWER);
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declare!(RADIO);
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declare!(RNG);
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declare!(GPIOTE);
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declare!(WDT);
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declare!(TIMER0);
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declare!(ECB);
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declare!(AAR_CCM);
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declare!(TEMP);
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declare!(RTC0);
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declare!(IPC);
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declare!(SERIAL0);
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declare!(EGU0);
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declare!(RTC1);
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declare!(TIMER1);
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declare!(TIMER2);
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declare!(SWI0);
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declare!(SWI1);
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declare!(SWI2);
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declare!(SWI3);
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}
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