cbc8871a0b
this removed the RelocatedProgram construction step from pio uses. there's not all that much to be said for the extra step because the origin can be set on the input program itself, and the remaining information exposed by RelocatedProgram can be exposed from LoadedProgram instead (even though it's already available on the pio_asm programs, albeit perhaps less convenient). we do lose access to the relocated instruction iterator, but we also cannot think of anything this iterator would actually be useful for outside of program loading.
242 lines
7.6 KiB
Rust
242 lines
7.6 KiB
Rust
//! This example shows powerful PIO module in the RP2040 chip to communicate with a HD44780 display.
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//! See (https://www.sparkfun.com/datasheets/LCD/HD44780.pdf)
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#![no_std]
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#![no_main]
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#![feature(type_alias_impl_trait)]
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use core::fmt::Write;
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use embassy_executor::Spawner;
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use embassy_rp::dma::{AnyChannel, Channel};
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use embassy_rp::peripherals::PIO0;
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use embassy_rp::pio::{
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Config, Direction, FifoJoin, InterruptHandler, Pio, PioPin, ShiftConfig, ShiftDirection, StateMachine,
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};
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use embassy_rp::pwm::{self, Pwm};
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use embassy_rp::{bind_interrupts, into_ref, Peripheral, PeripheralRef};
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use embassy_time::{Duration, Instant, Timer};
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use {defmt_rtt as _, panic_probe as _};
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bind_interrupts!(pub struct Irqs {
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PIO0_IRQ_0 => InterruptHandler<PIO0>;
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});
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#[embassy_executor::main]
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async fn main(_spawner: Spawner) {
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// this test assumes a 2x16 HD44780 display attached as follow:
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// rs = PIN0
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// rw = PIN1
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// e = PIN2
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// db4 = PIN3
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// db5 = PIN4
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// db6 = PIN5
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// db7 = PIN6
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// additionally a pwm signal for a bias voltage charge pump is provided on pin 15,
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// allowing direct connection of the display to the RP2040 without level shifters.
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let p = embassy_rp::init(Default::default());
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let _pwm = Pwm::new_output_b(p.PWM_CH7, p.PIN_15, {
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let mut c = pwm::Config::default();
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c.divider = 125.into();
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c.top = 100;
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c.compare_b = 50;
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c
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});
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let mut hd = HD44780::new(
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p.PIO0, Irqs, p.DMA_CH3, p.PIN_0, p.PIN_1, p.PIN_2, p.PIN_3, p.PIN_4, p.PIN_5, p.PIN_6,
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)
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.await;
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loop {
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struct Buf<const N: usize>([u8; N], usize);
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impl<const N: usize> Write for Buf<N> {
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fn write_str(&mut self, s: &str) -> Result<(), core::fmt::Error> {
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for b in s.as_bytes() {
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if self.1 >= N {
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return Err(core::fmt::Error);
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}
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self.0[self.1] = *b;
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self.1 += 1;
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}
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Ok(())
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}
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}
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let mut buf = Buf([0; 16], 0);
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write!(buf, "up {}s", Instant::now().as_micros() as f32 / 1e6).unwrap();
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hd.add_line(&buf.0[0..buf.1]).await;
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Timer::after(Duration::from_secs(1)).await;
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}
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}
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pub struct HD44780<'l> {
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dma: PeripheralRef<'l, AnyChannel>,
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sm: StateMachine<'l, PIO0, 0>,
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buf: [u8; 40],
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}
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impl<'l> HD44780<'l> {
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pub async fn new(
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pio: impl Peripheral<P = PIO0> + 'l,
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irq: Irqs,
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dma: impl Peripheral<P = impl Channel> + 'l,
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rs: impl PioPin,
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rw: impl PioPin,
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e: impl PioPin,
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db4: impl PioPin,
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db5: impl PioPin,
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db6: impl PioPin,
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db7: impl PioPin,
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) -> HD44780<'l> {
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into_ref!(dma);
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let Pio {
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mut common,
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mut irq0,
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mut sm0,
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..
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} = Pio::new(pio, irq);
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// takes command words (<wait:24> <command:4> <0:4>)
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let prg = pio_proc::pio_asm!(
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r#"
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.side_set 1 opt
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.origin 20
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loop:
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out x, 24
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delay:
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jmp x--, delay
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out pins, 4 side 1
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out null, 4 side 0
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jmp !osre, loop
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irq 0
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"#,
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);
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let rs = common.make_pio_pin(rs);
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let rw = common.make_pio_pin(rw);
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let e = common.make_pio_pin(e);
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let db4 = common.make_pio_pin(db4);
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let db5 = common.make_pio_pin(db5);
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let db6 = common.make_pio_pin(db6);
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let db7 = common.make_pio_pin(db7);
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sm0.set_pin_dirs(Direction::Out, &[&rs, &rw, &e, &db4, &db5, &db6, &db7]);
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let mut cfg = Config::default();
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cfg.use_program(&common.load_program(&prg.program), &[&e]);
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cfg.clock_divider = 125u8.into();
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cfg.set_out_pins(&[&db4, &db5, &db6, &db7]);
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cfg.shift_out = ShiftConfig {
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auto_fill: true,
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direction: ShiftDirection::Left,
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threshold: 32,
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};
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cfg.fifo_join = FifoJoin::TxOnly;
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sm0.set_config(&cfg);
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sm0.set_enable(true);
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// init to 8 bit thrice
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sm0.tx().push((50000 << 8) | 0x30);
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sm0.tx().push((5000 << 8) | 0x30);
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sm0.tx().push((200 << 8) | 0x30);
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// init 4 bit
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sm0.tx().push((200 << 8) | 0x20);
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// set font and lines
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sm0.tx().push((50 << 8) | 0x20);
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sm0.tx().push(0b1100_0000);
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irq0.wait().await;
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sm0.set_enable(false);
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// takes command sequences (<rs:1> <count:7>, data...)
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// many side sets are only there to free up a delay bit!
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let prg = pio_proc::pio_asm!(
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r#"
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.origin 27
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.side_set 1
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.wrap_target
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pull side 0
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out x 1 side 0 ; !rs
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out y 7 side 0 ; #data - 1
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; rs/rw to e: >= 60ns
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; e high time: >= 500ns
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; e low time: >= 500ns
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; read data valid after e falling: ~5ns
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; write data hold after e falling: ~10ns
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loop:
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pull side 0
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jmp !x data side 0
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command:
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set pins 0b00 side 0
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jmp shift side 0
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data:
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set pins 0b01 side 0
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shift:
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out pins 4 side 1 [9]
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nop side 0 [9]
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out pins 4 side 1 [9]
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mov osr null side 0 [7]
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out pindirs 4 side 0
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set pins 0b10 side 0
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busy:
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nop side 1 [9]
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jmp pin more side 0 [9]
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mov osr ~osr side 1 [9]
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nop side 0 [4]
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out pindirs 4 side 0
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jmp y-- loop side 0
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.wrap
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more:
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nop side 1 [9]
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jmp busy side 0 [9]
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"#
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);
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let mut cfg = Config::default();
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cfg.use_program(&common.load_program(&prg.program), &[&e]);
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cfg.clock_divider = 8u8.into(); // ~64ns/insn
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cfg.set_jmp_pin(&db7);
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cfg.set_set_pins(&[&rs, &rw]);
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cfg.set_out_pins(&[&db4, &db5, &db6, &db7]);
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cfg.shift_out.direction = ShiftDirection::Left;
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cfg.fifo_join = FifoJoin::TxOnly;
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sm0.set_config(&cfg);
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sm0.set_enable(true);
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// display on and cursor on and blinking, reset display
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sm0.tx().dma_push(dma.reborrow(), &[0x81u8, 0x0f, 1]).await;
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Self {
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dma: dma.map_into(),
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sm: sm0,
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buf: [0x20; 40],
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}
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}
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pub async fn add_line(&mut self, s: &[u8]) {
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// move cursor to 0:0, prepare 16 characters
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self.buf[..3].copy_from_slice(&[0x80, 0x80, 15]);
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// move line 2 up
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self.buf.copy_within(22..38, 3);
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// move cursor to 1:0, prepare 16 characters
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self.buf[19..22].copy_from_slice(&[0x80, 0xc0, 15]);
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// file line 2 with spaces
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self.buf[22..38].fill(0x20);
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// copy input line
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let len = s.len().min(16);
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self.buf[22..22 + len].copy_from_slice(&s[0..len]);
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// set cursor to 1:15
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self.buf[38..].copy_from_slice(&[0x80, 0xcf]);
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self.sm.tx().dma_push(self.dma.reborrow(), &self.buf).await;
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}
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}
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