498 lines
14 KiB
Rust
498 lines
14 KiB
Rust
#![allow(dead_code)]
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#![allow(unused_imports)]
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#![allow(non_snake_case)]
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pub fn GPIO(n: usize) -> gpio::Gpio {
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gpio::Gpio((0x48000000 + 0x400 * n) as _)
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}
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impl_gpio_pin!(PA0, 0, 0, EXTI0);
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impl_gpio_pin!(PA1, 0, 1, EXTI1);
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impl_gpio_pin!(PA2, 0, 2, EXTI2);
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impl_gpio_pin!(PA3, 0, 3, EXTI3);
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impl_gpio_pin!(PA4, 0, 4, EXTI4);
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impl_gpio_pin!(PA5, 0, 5, EXTI5);
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impl_gpio_pin!(PA6, 0, 6, EXTI6);
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impl_gpio_pin!(PA7, 0, 7, EXTI7);
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impl_gpio_pin!(PA8, 0, 8, EXTI8);
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impl_gpio_pin!(PA9, 0, 9, EXTI9);
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impl_gpio_pin!(PA10, 0, 10, EXTI10);
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impl_gpio_pin!(PA11, 0, 11, EXTI11);
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impl_gpio_pin!(PA12, 0, 12, EXTI12);
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impl_gpio_pin!(PA13, 0, 13, EXTI13);
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impl_gpio_pin!(PA14, 0, 14, EXTI14);
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impl_gpio_pin!(PA15, 0, 15, EXTI15);
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impl_gpio_pin!(PB0, 1, 0, EXTI0);
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impl_gpio_pin!(PB1, 1, 1, EXTI1);
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impl_gpio_pin!(PB2, 1, 2, EXTI2);
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impl_gpio_pin!(PB3, 1, 3, EXTI3);
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impl_gpio_pin!(PB4, 1, 4, EXTI4);
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impl_gpio_pin!(PB5, 1, 5, EXTI5);
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impl_gpio_pin!(PB6, 1, 6, EXTI6);
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impl_gpio_pin!(PB7, 1, 7, EXTI7);
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impl_gpio_pin!(PB8, 1, 8, EXTI8);
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impl_gpio_pin!(PB9, 1, 9, EXTI9);
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impl_gpio_pin!(PB10, 1, 10, EXTI10);
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impl_gpio_pin!(PB11, 1, 11, EXTI11);
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impl_gpio_pin!(PB12, 1, 12, EXTI12);
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impl_gpio_pin!(PB13, 1, 13, EXTI13);
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impl_gpio_pin!(PB14, 1, 14, EXTI14);
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impl_gpio_pin!(PB15, 1, 15, EXTI15);
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impl_gpio_pin!(PC0, 2, 0, EXTI0);
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impl_gpio_pin!(PC1, 2, 1, EXTI1);
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impl_gpio_pin!(PC2, 2, 2, EXTI2);
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impl_gpio_pin!(PC3, 2, 3, EXTI3);
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impl_gpio_pin!(PC4, 2, 4, EXTI4);
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impl_gpio_pin!(PC5, 2, 5, EXTI5);
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impl_gpio_pin!(PC6, 2, 6, EXTI6);
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impl_gpio_pin!(PC7, 2, 7, EXTI7);
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impl_gpio_pin!(PC8, 2, 8, EXTI8);
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impl_gpio_pin!(PC9, 2, 9, EXTI9);
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impl_gpio_pin!(PC10, 2, 10, EXTI10);
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impl_gpio_pin!(PC11, 2, 11, EXTI11);
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impl_gpio_pin!(PC12, 2, 12, EXTI12);
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impl_gpio_pin!(PC13, 2, 13, EXTI13);
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impl_gpio_pin!(PC14, 2, 14, EXTI14);
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impl_gpio_pin!(PC15, 2, 15, EXTI15);
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impl_gpio_pin!(PD0, 3, 0, EXTI0);
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impl_gpio_pin!(PD1, 3, 1, EXTI1);
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impl_gpio_pin!(PD2, 3, 2, EXTI2);
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impl_gpio_pin!(PD3, 3, 3, EXTI3);
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impl_gpio_pin!(PD4, 3, 4, EXTI4);
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impl_gpio_pin!(PD5, 3, 5, EXTI5);
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impl_gpio_pin!(PD6, 3, 6, EXTI6);
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impl_gpio_pin!(PD7, 3, 7, EXTI7);
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impl_gpio_pin!(PD8, 3, 8, EXTI8);
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impl_gpio_pin!(PD9, 3, 9, EXTI9);
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impl_gpio_pin!(PD10, 3, 10, EXTI10);
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impl_gpio_pin!(PD11, 3, 11, EXTI11);
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impl_gpio_pin!(PD12, 3, 12, EXTI12);
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impl_gpio_pin!(PD13, 3, 13, EXTI13);
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impl_gpio_pin!(PD14, 3, 14, EXTI14);
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impl_gpio_pin!(PD15, 3, 15, EXTI15);
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impl_gpio_pin!(PE0, 4, 0, EXTI0);
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impl_gpio_pin!(PE1, 4, 1, EXTI1);
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impl_gpio_pin!(PE2, 4, 2, EXTI2);
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impl_gpio_pin!(PE3, 4, 3, EXTI3);
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impl_gpio_pin!(PE4, 4, 4, EXTI4);
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impl_gpio_pin!(PE5, 4, 5, EXTI5);
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impl_gpio_pin!(PE6, 4, 6, EXTI6);
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impl_gpio_pin!(PE7, 4, 7, EXTI7);
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impl_gpio_pin!(PE8, 4, 8, EXTI8);
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impl_gpio_pin!(PE9, 4, 9, EXTI9);
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impl_gpio_pin!(PE10, 4, 10, EXTI10);
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impl_gpio_pin!(PE11, 4, 11, EXTI11);
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impl_gpio_pin!(PE12, 4, 12, EXTI12);
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impl_gpio_pin!(PE13, 4, 13, EXTI13);
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impl_gpio_pin!(PE14, 4, 14, EXTI14);
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impl_gpio_pin!(PE15, 4, 15, EXTI15);
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impl_gpio_pin!(PH0, 7, 0, EXTI0);
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impl_gpio_pin!(PH1, 7, 1, EXTI1);
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impl_gpio_pin!(PH2, 7, 2, EXTI2);
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impl_gpio_pin!(PH3, 7, 3, EXTI3);
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impl_gpio_pin!(PH4, 7, 4, EXTI4);
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impl_gpio_pin!(PH5, 7, 5, EXTI5);
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impl_gpio_pin!(PH6, 7, 6, EXTI6);
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impl_gpio_pin!(PH7, 7, 7, EXTI7);
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impl_gpio_pin!(PH8, 7, 8, EXTI8);
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impl_gpio_pin!(PH9, 7, 9, EXTI9);
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impl_gpio_pin!(PH10, 7, 10, EXTI10);
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impl_gpio_pin!(PH11, 7, 11, EXTI11);
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impl_gpio_pin!(PH12, 7, 12, EXTI12);
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impl_gpio_pin!(PH13, 7, 13, EXTI13);
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impl_gpio_pin!(PH14, 7, 14, EXTI14);
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impl_gpio_pin!(PH15, 7, 15, EXTI15);
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pub const EXTI: exti::Exti = exti::Exti(0x40010400 as _);
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pub const GPIOA: gpio::Gpio = gpio::Gpio(0x48000000 as _);
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pub const GPIOB: gpio::Gpio = gpio::Gpio(0x48000400 as _);
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pub const GPIOC: gpio::Gpio = gpio::Gpio(0x48000800 as _);
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pub const GPIOD: gpio::Gpio = gpio::Gpio(0x48000c00 as _);
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pub const GPIOE: gpio::Gpio = gpio::Gpio(0x48001000 as _);
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pub const GPIOH: gpio::Gpio = gpio::Gpio(0x48001c00 as _);
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pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
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impl_rng!(RNG);
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pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40010000 as _);
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pub const USART1: usart::Usart = usart::Usart(0x40013800 as _);
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pub const USART2: usart::Usart = usart::Usart(0x40004400 as _);
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pub const USART3: usart::Usart = usart::Usart(0x40004800 as _);
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pub use regs::exti_v1 as exti;
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pub use regs::gpio_v2 as gpio;
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pub use regs::rng_v1 as rng;
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pub use regs::syscfg_l4 as syscfg;
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pub use regs::usart_v2 as usart;
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mod regs;
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use embassy_extras::peripherals;
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pub use regs::generic;
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peripherals!(
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EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
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EXTI13, EXTI14, EXTI15, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12,
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PA13, PA14, PA15, PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13,
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PB14, PB15, PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14,
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PC15, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15,
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PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PH0, PH1,
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PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, EXTI, RNG, SYSCFG,
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USART1, USART2, USART3
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);
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pub mod interrupt {
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pub use cortex_m::interrupt::{CriticalSection, Mutex};
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pub use embassy::interrupt::{declare, take, Interrupt};
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pub use embassy_extras::interrupt::Priority4 as Priority;
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#[derive(Copy, Clone, Debug, PartialEq, Eq)]
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#[allow(non_camel_case_types)]
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enum InterruptEnum {
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ADC1 = 18,
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CAN1_RX0 = 20,
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CAN1_RX1 = 21,
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CAN1_SCE = 22,
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CAN1_TX = 19,
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COMP = 64,
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CRS = 82,
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DFSDM1_FLT0 = 61,
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DFSDM1_FLT1 = 62,
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DMA1_Channel1 = 11,
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DMA1_Channel2 = 12,
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DMA1_Channel3 = 13,
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DMA1_Channel4 = 14,
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DMA1_Channel5 = 15,
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DMA1_Channel6 = 16,
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DMA1_Channel7 = 17,
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DMA2_Channel1 = 56,
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DMA2_Channel2 = 57,
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DMA2_Channel3 = 58,
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DMA2_Channel4 = 59,
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DMA2_Channel5 = 60,
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DMA2_Channel6 = 68,
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DMA2_Channel7 = 69,
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EXTI0 = 6,
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EXTI1 = 7,
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EXTI15_10 = 40,
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EXTI2 = 8,
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EXTI3 = 9,
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EXTI4 = 10,
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EXTI9_5 = 23,
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FLASH = 4,
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FPU = 81,
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I2C1_ER = 32,
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I2C1_EV = 31,
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I2C2_ER = 34,
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I2C2_EV = 33,
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I2C3_ER = 73,
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I2C3_EV = 72,
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I2C4_ER = 84,
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I2C4_EV = 83,
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LPTIM1 = 65,
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LPTIM2 = 66,
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LPUART1 = 70,
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PVD_PVM = 1,
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QUADSPI = 71,
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RCC = 5,
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RNG = 80,
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RTC_Alarm = 41,
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RTC_WKUP = 3,
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SAI1 = 74,
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SDMMC1 = 49,
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SPI1 = 35,
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SPI2 = 36,
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SPI3 = 51,
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TAMP_STAMP = 2,
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TIM1_BRK_TIM15 = 24,
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TIM1_CC = 27,
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TIM1_TRG_COM = 26,
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TIM1_UP_TIM16 = 25,
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TIM2 = 28,
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TIM3 = 29,
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TIM6_DAC = 54,
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TSC = 77,
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UART4 = 52,
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USART1 = 37,
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USART2 = 38,
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USART3 = 39,
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WWDG = 0,
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}
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unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
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#[inline(always)]
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fn number(self) -> u16 {
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self as u16
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}
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}
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declare!(ADC1);
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declare!(CAN1_RX0);
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declare!(CAN1_RX1);
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declare!(CAN1_SCE);
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declare!(CAN1_TX);
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declare!(COMP);
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declare!(CRS);
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declare!(DFSDM1_FLT0);
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declare!(DFSDM1_FLT1);
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declare!(DMA1_Channel1);
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declare!(DMA1_Channel2);
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declare!(DMA1_Channel3);
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declare!(DMA1_Channel4);
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declare!(DMA1_Channel5);
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declare!(DMA1_Channel6);
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declare!(DMA1_Channel7);
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declare!(DMA2_Channel1);
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declare!(DMA2_Channel2);
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declare!(DMA2_Channel3);
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declare!(DMA2_Channel4);
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declare!(DMA2_Channel5);
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declare!(DMA2_Channel6);
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declare!(DMA2_Channel7);
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declare!(EXTI0);
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declare!(EXTI1);
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declare!(EXTI15_10);
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declare!(EXTI2);
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declare!(EXTI3);
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declare!(EXTI4);
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declare!(EXTI9_5);
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declare!(FLASH);
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declare!(FPU);
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declare!(I2C1_ER);
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declare!(I2C1_EV);
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declare!(I2C2_ER);
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declare!(I2C2_EV);
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declare!(I2C3_ER);
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declare!(I2C3_EV);
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declare!(I2C4_ER);
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declare!(I2C4_EV);
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declare!(LPTIM1);
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declare!(LPTIM2);
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declare!(LPUART1);
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declare!(PVD_PVM);
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declare!(QUADSPI);
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declare!(RCC);
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declare!(RNG);
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declare!(RTC_Alarm);
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declare!(RTC_WKUP);
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declare!(SAI1);
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declare!(SDMMC1);
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declare!(SPI1);
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declare!(SPI2);
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declare!(SPI3);
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declare!(TAMP_STAMP);
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declare!(TIM1_BRK_TIM15);
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declare!(TIM1_CC);
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declare!(TIM1_TRG_COM);
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declare!(TIM1_UP_TIM16);
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declare!(TIM2);
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declare!(TIM3);
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declare!(TIM6_DAC);
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declare!(TSC);
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declare!(UART4);
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declare!(USART1);
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declare!(USART2);
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declare!(USART3);
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declare!(WWDG);
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}
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mod interrupt_vector {
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extern "C" {
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fn ADC1();
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fn CAN1_RX0();
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fn CAN1_RX1();
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fn CAN1_SCE();
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fn CAN1_TX();
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fn COMP();
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fn CRS();
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fn DFSDM1_FLT0();
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fn DFSDM1_FLT1();
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fn DMA1_Channel1();
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fn DMA1_Channel2();
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fn DMA1_Channel3();
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fn DMA1_Channel4();
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fn DMA1_Channel5();
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fn DMA1_Channel6();
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fn DMA1_Channel7();
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fn DMA2_Channel1();
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fn DMA2_Channel2();
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fn DMA2_Channel3();
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fn DMA2_Channel4();
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fn DMA2_Channel5();
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fn DMA2_Channel6();
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fn DMA2_Channel7();
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fn EXTI0();
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fn EXTI1();
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fn EXTI15_10();
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fn EXTI2();
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fn EXTI3();
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fn EXTI4();
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fn EXTI9_5();
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fn FLASH();
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fn FPU();
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fn I2C1_ER();
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fn I2C1_EV();
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fn I2C2_ER();
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fn I2C2_EV();
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fn I2C3_ER();
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fn I2C3_EV();
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fn I2C4_ER();
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fn I2C4_EV();
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fn LPTIM1();
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fn LPTIM2();
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fn LPUART1();
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fn PVD_PVM();
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fn QUADSPI();
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fn RCC();
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fn RNG();
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fn RTC_Alarm();
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fn RTC_WKUP();
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fn SAI1();
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fn SDMMC1();
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fn SPI1();
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fn SPI2();
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fn SPI3();
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fn TAMP_STAMP();
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fn TIM1_BRK_TIM15();
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fn TIM1_CC();
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fn TIM1_TRG_COM();
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fn TIM1_UP_TIM16();
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fn TIM2();
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fn TIM3();
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fn TIM6_DAC();
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fn TSC();
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fn UART4();
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fn USART1();
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fn USART2();
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fn USART3();
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fn WWDG();
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}
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pub union Vector {
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_handler: unsafe extern "C" fn(),
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_reserved: u32,
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}
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#[link_section = ".vector_table.interrupts"]
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#[no_mangle]
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pub static __INTERRUPTS: [Vector; 85] = [
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Vector { _handler: WWDG },
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Vector { _handler: PVD_PVM },
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Vector {
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_handler: TAMP_STAMP,
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},
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Vector { _handler: RTC_WKUP },
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Vector { _handler: FLASH },
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Vector { _handler: RCC },
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Vector { _handler: EXTI0 },
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Vector { _handler: EXTI1 },
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Vector { _handler: EXTI2 },
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Vector { _handler: EXTI3 },
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Vector { _handler: EXTI4 },
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Vector {
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_handler: DMA1_Channel1,
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},
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Vector {
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_handler: DMA1_Channel2,
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},
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Vector {
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_handler: DMA1_Channel3,
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},
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Vector {
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_handler: DMA1_Channel4,
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},
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Vector {
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_handler: DMA1_Channel5,
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},
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Vector {
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_handler: DMA1_Channel6,
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},
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Vector {
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_handler: DMA1_Channel7,
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},
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Vector { _handler: ADC1 },
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Vector { _handler: CAN1_TX },
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Vector { _handler: CAN1_RX0 },
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Vector { _handler: CAN1_RX1 },
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Vector { _handler: CAN1_SCE },
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Vector { _handler: EXTI9_5 },
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Vector {
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_handler: TIM1_BRK_TIM15,
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},
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Vector {
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_handler: TIM1_UP_TIM16,
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},
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Vector {
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_handler: TIM1_TRG_COM,
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},
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Vector { _handler: TIM1_CC },
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Vector { _handler: TIM2 },
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Vector { _handler: TIM3 },
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Vector { _reserved: 0 },
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Vector { _handler: I2C1_EV },
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Vector { _handler: I2C1_ER },
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Vector { _handler: I2C2_EV },
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Vector { _handler: I2C2_ER },
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Vector { _handler: SPI1 },
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Vector { _handler: SPI2 },
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Vector { _handler: USART1 },
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Vector { _handler: USART2 },
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Vector { _handler: USART3 },
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Vector {
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_handler: EXTI15_10,
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},
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Vector {
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_handler: RTC_Alarm,
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},
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Vector { _reserved: 0 },
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Vector { _reserved: 0 },
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Vector { _reserved: 0 },
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Vector { _reserved: 0 },
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Vector { _reserved: 0 },
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Vector { _reserved: 0 },
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Vector { _reserved: 0 },
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Vector { _handler: SDMMC1 },
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Vector { _reserved: 0 },
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Vector { _handler: SPI3 },
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Vector { _handler: UART4 },
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Vector { _reserved: 0 },
|
|
Vector { _handler: TIM6_DAC },
|
|
Vector { _reserved: 0 },
|
|
Vector {
|
|
_handler: DMA2_Channel1,
|
|
},
|
|
Vector {
|
|
_handler: DMA2_Channel2,
|
|
},
|
|
Vector {
|
|
_handler: DMA2_Channel3,
|
|
},
|
|
Vector {
|
|
_handler: DMA2_Channel4,
|
|
},
|
|
Vector {
|
|
_handler: DMA2_Channel5,
|
|
},
|
|
Vector {
|
|
_handler: DFSDM1_FLT0,
|
|
},
|
|
Vector {
|
|
_handler: DFSDM1_FLT1,
|
|
},
|
|
Vector { _reserved: 0 },
|
|
Vector { _handler: COMP },
|
|
Vector { _handler: LPTIM1 },
|
|
Vector { _handler: LPTIM2 },
|
|
Vector { _reserved: 0 },
|
|
Vector {
|
|
_handler: DMA2_Channel6,
|
|
},
|
|
Vector {
|
|
_handler: DMA2_Channel7,
|
|
},
|
|
Vector { _handler: LPUART1 },
|
|
Vector { _handler: QUADSPI },
|
|
Vector { _handler: I2C3_EV },
|
|
Vector { _handler: I2C3_ER },
|
|
Vector { _handler: SAI1 },
|
|
Vector { _reserved: 0 },
|
|
Vector { _reserved: 0 },
|
|
Vector { _handler: TSC },
|
|
Vector { _reserved: 0 },
|
|
Vector { _reserved: 0 },
|
|
Vector { _handler: RNG },
|
|
Vector { _handler: FPU },
|
|
Vector { _handler: CRS },
|
|
Vector { _handler: I2C4_EV },
|
|
Vector { _handler: I2C4_ER },
|
|
];
|
|
}
|