231 lines
6.5 KiB
Rust
231 lines
6.5 KiB
Rust
#![macro_use]
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use core::cell::UnsafeCell;
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use core::marker::PhantomData;
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use core::sync::atomic::{compiler_fence, Ordering};
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use embassy::util::Unborrow;
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use embassy_hal_common::unborrow;
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use crate::gpio::sealed::Pin as _;
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use crate::gpio::OptionalPin as GpioOptionalPin;
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use crate::interrupt::Interrupt;
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use crate::pac;
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#[derive(Debug, Eq, PartialEq, Clone, Copy)]
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pub enum Prescaler {
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Div1,
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Div2,
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Div4,
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Div8,
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Div16,
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Div32,
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Div64,
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Div128,
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}
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/// Interface to the UARTE peripheral
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pub struct Pwm<'d, T: Instance> {
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phantom: PhantomData<&'d mut T>,
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}
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impl<'d, T: Instance> Pwm<'d, T> {
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/// Creates the interface to a UARTE instance.
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/// Sets the baud rate, parity and assigns the pins to the UARTE peripheral.
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///
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/// # Safety
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///
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/// The returned API is safe unless you use `mem::forget` (or similar safe mechanisms)
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/// on stack allocated buffers which which have been passed to [`send()`](Pwm::send)
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/// or [`receive`](Pwm::receive).
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#[allow(unused_unsafe)]
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pub fn new(
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_pwm: impl Unborrow<Target = T> + 'd,
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ch0: impl Unborrow<Target = impl GpioOptionalPin> + 'd,
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ch1: impl Unborrow<Target = impl GpioOptionalPin> + 'd,
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ch2: impl Unborrow<Target = impl GpioOptionalPin> + 'd,
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ch3: impl Unborrow<Target = impl GpioOptionalPin> + 'd,
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) -> Self {
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unborrow!(ch0, ch1, ch2, ch3);
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let r = T::regs();
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let s = T::state();
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if let Some(pin) = ch0.pin_mut() {
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pin.set_low();
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pin.conf().write(|w| w.dir().output());
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}
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if let Some(pin) = ch1.pin_mut() {
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pin.set_low();
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pin.conf().write(|w| w.dir().output());
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}
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if let Some(pin) = ch2.pin_mut() {
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pin.set_low();
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pin.conf().write(|w| w.dir().output());
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}
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if let Some(pin) = ch3.pin_mut() {
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pin.set_low();
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pin.conf().write(|w| w.dir().output());
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}
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r.psel.out[0].write(|w| unsafe { w.bits(ch0.psel_bits()) });
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r.psel.out[1].write(|w| unsafe { w.bits(ch1.psel_bits()) });
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r.psel.out[2].write(|w| unsafe { w.bits(ch2.psel_bits()) });
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r.psel.out[3].write(|w| unsafe { w.bits(ch3.psel_bits()) });
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// Disable all interrupts
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r.intenclr.write(|w| unsafe { w.bits(0xFFFF_FFFF) });
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// Enable
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r.enable.write(|w| w.enable().enabled());
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r.seq0
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.ptr
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.write(|w| unsafe { w.bits(&s.duty as *const _ as u32) });
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r.seq0.cnt.write(|w| unsafe { w.bits(4) });
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r.seq0.refresh.write(|w| unsafe { w.bits(32) });
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r.seq0.enddelay.write(|w| unsafe { w.bits(0) });
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r.decoder.write(|w| {
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w.load().individual();
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w.mode().refresh_count()
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});
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r.mode.write(|w| w.updown().up());
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r.prescaler.write(|w| w.prescaler().div_1());
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r.countertop
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.write(|w| unsafe { w.countertop().bits(32767) });
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r.loop_.write(|w| w.cnt().disabled());
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Self {
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phantom: PhantomData,
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}
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}
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/// Enables the PWM generator.
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#[inline(always)]
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pub fn enable(&self) {
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let r = T::regs();
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r.enable.write(|w| w.enable().enabled());
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}
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/// Disables the PWM generator.
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#[inline(always)]
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pub fn disable(&self) {
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let r = T::regs();
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r.enable.write(|w| w.enable().disabled());
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}
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/// Sets duty cycle (15 bit) for a PWM channel.
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pub fn set_duty(&self, channel: usize, duty: u16) {
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let s = T::state();
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unsafe { (*s.duty.get())[channel] = duty & 0x7FFF };
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compiler_fence(Ordering::SeqCst);
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T::regs().tasks_seqstart[0].write(|w| unsafe { w.bits(1) });
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}
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/// Sets the PWM clock prescaler.
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#[inline(always)]
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pub fn set_prescaler(&self, div: Prescaler) {
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T::regs().prescaler.write(|w| w.prescaler().bits(div as u8));
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}
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/// Sets the PWM clock prescaler.
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#[inline(always)]
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pub fn prescaler(&self) -> Prescaler {
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match T::regs().prescaler.read().prescaler().bits() {
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0 => Prescaler::Div1,
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1 => Prescaler::Div2,
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2 => Prescaler::Div4,
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3 => Prescaler::Div8,
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4 => Prescaler::Div16,
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5 => Prescaler::Div32,
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6 => Prescaler::Div64,
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7 => Prescaler::Div128,
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_ => unreachable!(),
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}
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}
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/// Sets the maximum duty cycle value.
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#[inline(always)]
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pub fn set_max_duty(&self, duty: u16) {
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T::regs()
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.countertop
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.write(|w| unsafe { w.countertop().bits(duty.min(32767u16)) });
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}
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/// Returns the maximum duty cycle value.
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#[inline(always)]
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pub fn max_duty(&self) -> u16 {
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T::regs().countertop.read().countertop().bits()
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}
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/// Sets the PWM output frequency.
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#[inline(always)]
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pub fn set_period(&self, freq: u32) {
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let clk = 16_000_000u32 >> (self.prescaler() as u8);
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let duty = clk / freq;
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self.set_max_duty(duty.min(32767) as u16);
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}
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/// Returns the PWM output frequency.
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#[inline(always)]
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pub fn period(&self) -> u32 {
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let clk = 16_000_000u32 >> (self.prescaler() as u8);
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let max_duty = self.max_duty() as u32;
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clk / max_duty
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}
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}
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impl<'a, T: Instance> Drop for Pwm<'a, T> {
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fn drop(&mut self) {
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let r = T::regs();
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r.enable.write(|w| w.enable().disabled());
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info!("pwm drop: done");
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// TODO: disable pins
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}
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}
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pub(crate) mod sealed {
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use super::*;
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pub struct State {
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pub duty: UnsafeCell<[u16; 4]>,
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}
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unsafe impl Sync for State {}
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impl State {
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pub const fn new() -> Self {
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Self {
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duty: UnsafeCell::new([0; 4]),
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}
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}
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}
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pub trait Instance {
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fn regs() -> &'static pac::pwm0::RegisterBlock;
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fn state() -> &'static State;
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}
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}
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pub trait Instance: Unborrow<Target = Self> + sealed::Instance + 'static {
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type Interrupt: Interrupt;
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}
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macro_rules! impl_pwm {
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($type:ident, $pac_type:ident, $irq:ident) => {
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impl crate::pwm::sealed::Instance for peripherals::$type {
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fn regs() -> &'static pac::pwm0::RegisterBlock {
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unsafe { &*pac::$pac_type::ptr() }
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}
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fn state() -> &'static crate::pwm::sealed::State {
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static STATE: crate::pwm::sealed::State = crate::pwm::sealed::State::new();
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&STATE
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}
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}
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impl crate::pwm::Instance for peripherals::$type {
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type Interrupt = crate::interrupt::$irq;
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}
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};
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}
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