embassy/examples/stm32f7/src/bin/sdmmc.rs

64 lines
1.6 KiB
Rust
Raw Permalink Normal View History

2022-03-16 22:44:02 +01:00
#![no_std]
#![no_main]
#![feature(type_alias_impl_trait)]
use defmt::*;
use embassy_executor::Spawner;
2022-03-16 22:44:02 +01:00
use embassy_stm32::sdmmc::Sdmmc;
2023-10-18 03:16:36 +02:00
use embassy_stm32::time::{mhz, Hertz};
use embassy_stm32::{bind_interrupts, peripherals, sdmmc, Config};
2022-06-12 22:15:44 +02:00
use {defmt_rtt as _, panic_probe as _};
2022-03-16 22:44:02 +01:00
bind_interrupts!(struct Irqs {
SDMMC1 => sdmmc::InterruptHandler<peripherals::SDMMC1>;
});
#[embassy_executor::main]
2023-03-08 03:08:59 +01:00
async fn main(_spawner: Spawner) {
2022-03-16 22:44:02 +01:00
let mut config = Config::default();
2023-10-18 03:16:36 +02:00
{
use embassy_stm32::rcc::*;
config.rcc.hse = Some(Hse {
freq: Hertz(8_000_000),
mode: HseMode::Bypass,
});
config.rcc.pll_src = PllSource::HSE;
config.rcc.pll = Some(Pll {
prediv: PllPreDiv::DIV4,
mul: PllMul::MUL216,
divp: Some(PllPDiv::DIV2), // 8mhz / 4 * 216 / 2 = 216Mhz
divq: Some(PllQDiv::DIV9), // 8mhz / 4 * 216 / 9 = 48Mhz
2023-10-18 03:16:36 +02:00
divr: None,
});
config.rcc.ahb_pre = AHBPrescaler::DIV1;
config.rcc.apb1_pre = APBPrescaler::DIV4;
config.rcc.apb2_pre = APBPrescaler::DIV2;
config.rcc.sys = Sysclk::PLL1_P;
}
let p = embassy_stm32::init(config);
2022-03-16 22:44:02 +01:00
info!("Hello World!");
2022-07-23 01:29:35 +02:00
let mut sdmmc = Sdmmc::new_4bit(
2022-03-16 22:44:02 +01:00
p.SDMMC1,
Irqs,
2022-03-16 23:03:24 +01:00
p.DMA2_CH3,
2022-07-23 01:29:35 +02:00
p.PC12,
p.PD2,
p.PC8,
p.PC9,
p.PC10,
p.PC11,
Default::default(),
2022-03-16 22:44:02 +01:00
);
2022-03-16 22:55:07 +01:00
// Should print 400kHz for initialization
info!("Configured clock: {}", sdmmc.clock().0);
2022-03-16 22:44:02 +01:00
unwrap!(sdmmc.init_card(mhz(25)).await);
2022-03-16 22:44:02 +01:00
let card = unwrap!(sdmmc.card());
info!("Card: {:#?}", Debug2Format(card));
}