2023-04-17 00:04:54 +02:00
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#![macro_use]
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use core::future::Future;
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use core::pin::Pin;
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2022-04-26 23:57:26 +02:00
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use core::sync::atomic::{fence, Ordering};
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2023-04-17 00:04:54 +02:00
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use core::task::{Context, Poll};
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2022-04-26 23:57:26 +02:00
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2023-07-28 13:23:22 +02:00
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use embassy_hal_internal::{into_ref, Peripheral, PeripheralRef};
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2022-08-22 21:46:09 +02:00
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use embassy_sync::waitqueue::AtomicWaker;
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2022-04-26 23:57:26 +02:00
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2023-04-18 20:56:23 +02:00
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use super::word::{Word, WordSize};
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use super::Dir;
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2022-04-26 23:57:26 +02:00
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use crate::_generated::GPDMA_CHANNEL_COUNT;
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2023-06-08 18:07:44 +02:00
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use crate::interrupt::typelevel::Interrupt;
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2023-06-09 16:14:13 +02:00
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use crate::interrupt::Priority;
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2023-04-17 00:04:54 +02:00
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use crate::pac;
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use crate::pac::gpdma::vals;
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#[derive(Debug, Copy, Clone, PartialEq, Eq)]
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#[cfg_attr(feature = "defmt", derive(defmt::Format))]
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#[non_exhaustive]
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pub struct TransferOptions {}
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impl Default for TransferOptions {
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fn default() -> Self {
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Self {}
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}
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}
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2022-04-26 23:57:26 +02:00
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impl From<WordSize> for vals::ChTr1Dw {
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fn from(raw: WordSize) -> Self {
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match raw {
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WordSize::OneByte => Self::BYTE,
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WordSize::TwoBytes => Self::HALFWORD,
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WordSize::FourBytes => Self::WORD,
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}
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}
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}
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struct State {
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2023-04-17 00:04:54 +02:00
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ch_wakers: [AtomicWaker; GPDMA_CHANNEL_COUNT],
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2022-04-26 23:57:26 +02:00
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}
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impl State {
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const fn new() -> Self {
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2023-04-17 00:04:54 +02:00
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const AW: AtomicWaker = AtomicWaker::new();
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2022-04-26 23:57:26 +02:00
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Self {
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2023-04-17 00:04:54 +02:00
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ch_wakers: [AW; GPDMA_CHANNEL_COUNT],
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2022-04-26 23:57:26 +02:00
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}
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}
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}
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static STATE: State = State::new();
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/// safety: must be called only once
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2023-04-17 00:04:54 +02:00
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pub(crate) unsafe fn init(irq_priority: Priority) {
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2022-04-26 23:57:26 +02:00
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foreach_interrupt! {
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($peri:ident, gpdma, $block:ident, $signal_name:ident, $irq:ident) => {
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2023-06-08 16:08:40 +02:00
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crate::interrupt::typelevel::$irq::set_priority(irq_priority);
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crate::interrupt::typelevel::$irq::enable();
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2022-04-26 23:57:26 +02:00
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};
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}
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crate::_generated::init_gpdma();
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}
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foreach_dma_channel! {
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($channel_peri:ident, $dma_peri:ident, gpdma, $channel_num:expr, $index:expr, $dmamux:tt) => {
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2023-04-17 00:04:54 +02:00
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impl sealed::Channel for crate::peripherals::$channel_peri {
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fn regs(&self) -> pac::gpdma::Gpdma {
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pac::$dma_peri
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2022-04-26 23:57:26 +02:00
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}
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2023-04-17 00:04:54 +02:00
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fn num(&self) -> usize {
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$channel_num
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2022-04-26 23:57:26 +02:00
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}
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2023-04-17 00:04:54 +02:00
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fn index(&self) -> usize {
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$index
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}
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2023-04-17 00:04:54 +02:00
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fn on_irq() {
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unsafe { on_irq_inner(pac::$dma_peri, $channel_num, $index) }
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2022-04-26 23:57:26 +02:00
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}
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2023-04-17 00:04:54 +02:00
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}
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2022-04-26 23:57:26 +02:00
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2023-04-17 00:04:54 +02:00
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impl Channel for crate::peripherals::$channel_peri {}
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};
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}
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2022-04-26 23:57:26 +02:00
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2023-04-17 00:04:54 +02:00
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/// Safety: Must be called with a matching set of parameters for a valid dma channel
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pub(crate) unsafe fn on_irq_inner(dma: pac::gpdma::Gpdma, channel_num: usize, index: usize) {
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let ch = dma.ch(channel_num);
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let sr = ch.sr().read();
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2022-04-26 23:57:26 +02:00
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2023-04-17 00:04:54 +02:00
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if sr.dtef() {
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panic!(
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"DMA: data transfer error on DMA@{:08x} channel {}",
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2023-06-19 03:07:26 +02:00
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dma.as_ptr() as u32,
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channel_num
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2023-04-17 00:04:54 +02:00
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);
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}
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if sr.usef() {
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panic!(
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"DMA: user settings error on DMA@{:08x} channel {}",
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2023-06-19 03:07:26 +02:00
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dma.as_ptr() as u32,
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channel_num
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2023-04-17 00:04:54 +02:00
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);
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}
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2022-04-26 23:57:26 +02:00
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2023-04-17 00:04:54 +02:00
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if sr.suspf() || sr.tcf() {
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// disable all xxIEs to prevent the irq from firing again.
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ch.cr().write(|_| {});
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2022-04-26 23:57:26 +02:00
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2023-04-17 00:04:54 +02:00
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// Wake the future. It'll look at tcf and see it's set.
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STATE.ch_wakers[index].wake();
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}
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}
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2022-04-26 23:57:26 +02:00
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2023-04-17 00:04:54 +02:00
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pub type Request = u8;
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2022-04-26 23:57:26 +02:00
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2023-04-17 00:04:54 +02:00
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#[cfg(dmamux)]
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pub trait Channel: sealed::Channel + Peripheral<P = Self> + 'static + super::dmamux::MuxChannel {}
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#[cfg(not(dmamux))]
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pub trait Channel: sealed::Channel + Peripheral<P = Self> + 'static {}
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2022-04-26 23:57:26 +02:00
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2023-04-17 00:04:54 +02:00
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pub(crate) mod sealed {
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use super::*;
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pub trait Channel {
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fn regs(&self) -> pac::gpdma::Gpdma;
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fn num(&self) -> usize;
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fn index(&self) -> usize;
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fn on_irq();
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}
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2022-04-26 23:57:26 +02:00
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}
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2023-04-17 00:04:54 +02:00
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#[must_use = "futures do nothing unless you `.await` or poll them"]
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pub struct Transfer<'a, C: Channel> {
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channel: PeripheralRef<'a, C>,
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}
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2022-04-26 23:57:26 +02:00
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2023-04-17 00:04:54 +02:00
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impl<'a, C: Channel> Transfer<'a, C> {
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pub unsafe fn new_read<W: Word>(
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channel: impl Peripheral<P = C> + 'a,
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request: Request,
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peri_addr: *mut W,
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buf: &'a mut [W],
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options: TransferOptions,
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) -> Self {
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Self::new_read_raw(channel, request, peri_addr, buf, options)
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2022-04-26 23:57:26 +02:00
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}
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2023-04-17 00:04:54 +02:00
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pub unsafe fn new_read_raw<W: Word>(
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channel: impl Peripheral<P = C> + 'a,
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request: Request,
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peri_addr: *mut W,
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buf: *mut [W],
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options: TransferOptions,
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) -> Self {
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into_ref!(channel);
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let (ptr, len) = super::slice_ptr_parts_mut(buf);
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assert!(len > 0 && len <= 0xFFFF);
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Self::new_inner(
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channel,
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request,
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Dir::PeripheralToMemory,
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peri_addr as *const u32,
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ptr as *mut u32,
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len,
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true,
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2023-04-18 20:56:23 +02:00
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W::size(),
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2023-04-17 00:04:54 +02:00
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options,
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)
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}
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pub unsafe fn new_write<W: Word>(
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channel: impl Peripheral<P = C> + 'a,
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request: Request,
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buf: &'a [W],
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peri_addr: *mut W,
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options: TransferOptions,
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) -> Self {
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Self::new_write_raw(channel, request, buf, peri_addr, options)
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}
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pub unsafe fn new_write_raw<W: Word>(
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channel: impl Peripheral<P = C> + 'a,
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request: Request,
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buf: *const [W],
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peri_addr: *mut W,
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options: TransferOptions,
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) -> Self {
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into_ref!(channel);
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let (ptr, len) = super::slice_ptr_parts(buf);
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assert!(len > 0 && len <= 0xFFFF);
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Self::new_inner(
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channel,
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request,
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Dir::MemoryToPeripheral,
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peri_addr as *const u32,
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ptr as *mut u32,
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len,
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true,
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2023-04-18 20:56:23 +02:00
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W::size(),
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2023-04-17 00:04:54 +02:00
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options,
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)
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}
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pub unsafe fn new_write_repeated<W: Word>(
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channel: impl Peripheral<P = C> + 'a,
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request: Request,
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repeated: &'a W,
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count: usize,
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peri_addr: *mut W,
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options: TransferOptions,
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) -> Self {
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into_ref!(channel);
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Self::new_inner(
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channel,
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request,
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Dir::MemoryToPeripheral,
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peri_addr as *const u32,
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repeated as *const W as *mut u32,
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count,
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false,
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2023-04-18 20:56:23 +02:00
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W::size(),
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2023-04-17 00:04:54 +02:00
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options,
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)
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}
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unsafe fn new_inner(
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channel: PeripheralRef<'a, C>,
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2022-04-26 23:57:26 +02:00
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request: Request,
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dir: Dir,
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peri_addr: *const u32,
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mem_addr: *mut u32,
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mem_len: usize,
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incr_mem: bool,
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data_size: WordSize,
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2023-04-17 00:04:54 +02:00
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_options: TransferOptions,
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) -> Self {
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let ch = channel.regs().ch(channel.num());
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2023-02-18 00:35:35 +01:00
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2022-04-26 23:57:26 +02:00
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// "Preceding reads and writes cannot be moved past subsequent writes."
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fence(Ordering::SeqCst);
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2023-04-17 00:04:54 +02:00
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let this = Self { channel };
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2023-04-10 15:11:07 +02:00
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2023-04-17 00:04:54 +02:00
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#[cfg(dmamux)]
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super::dmamux::configure_dmamux(&mut *this.channel, request);
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2023-04-10 15:11:07 +02:00
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2023-04-17 00:04:54 +02:00
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ch.cr().write(|w| w.set_reset(true));
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2023-06-19 22:39:08 +02:00
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ch.fcr().write(|w| w.0 = 0xFFFF_FFFF); // clear all irqs
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2022-04-26 23:57:26 +02:00
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ch.llr().write(|_| {}); // no linked list
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ch.tr1().write(|w| {
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w.set_sdw(data_size.into());
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w.set_ddw(data_size.into());
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w.set_sinc(dir == Dir::MemoryToPeripheral && incr_mem);
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w.set_dinc(dir == Dir::PeripheralToMemory && incr_mem);
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});
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ch.tr2().write(|w| {
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w.set_dreq(match dir {
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Dir::MemoryToPeripheral => vals::ChTr2Dreq::DESTINATIONPERIPHERAL,
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Dir::PeripheralToMemory => vals::ChTr2Dreq::SOURCEPERIPHERAL,
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});
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w.set_reqsel(request);
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});
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ch.br1().write(|w| {
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// BNDT is specified as bytes, not as number of transfers.
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w.set_bndt((mem_len * data_size.bytes()) as u16)
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});
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match dir {
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Dir::MemoryToPeripheral => {
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ch.sar().write_value(mem_addr as _);
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ch.dar().write_value(peri_addr as _);
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}
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Dir::PeripheralToMemory => {
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ch.sar().write_value(peri_addr as _);
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ch.dar().write_value(mem_addr as _);
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}
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}
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ch.cr().write(|w| {
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// Enable interrupts
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w.set_tcie(true);
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w.set_useie(true);
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w.set_dteie(true);
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w.set_suspie(true);
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// Start it
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w.set_en(true);
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});
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2023-04-17 00:04:54 +02:00
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this
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2022-04-26 23:57:26 +02:00
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}
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2023-04-17 00:04:54 +02:00
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pub fn request_stop(&mut self) {
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let ch = self.channel.regs().ch(self.channel.num());
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2022-04-26 23:57:26 +02:00
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// Disable the channel. Keep the IEs enabled so the irqs still fire.
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2023-06-19 03:07:26 +02:00
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ch.cr().write(|w| {
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w.set_tcie(true);
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w.set_useie(true);
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w.set_dteie(true);
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w.set_suspie(true);
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})
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2022-04-26 23:57:26 +02:00
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}
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2023-04-17 00:04:54 +02:00
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pub fn is_running(&mut self) -> bool {
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let ch = self.channel.regs().ch(self.channel.num());
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2023-06-19 03:07:26 +02:00
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!ch.sr().read().tcf()
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2022-04-26 23:57:26 +02:00
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}
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/// Gets the total remaining transfers for the channel
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/// Note: this will be zero for transfers that completed without cancellation.
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2023-04-17 00:04:54 +02:00
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pub fn get_remaining_transfers(&self) -> u16 {
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let ch = self.channel.regs().ch(self.channel.num());
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2023-06-19 03:07:26 +02:00
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ch.br1().read().bndt()
|
2022-04-26 23:57:26 +02:00
|
|
|
}
|
|
|
|
|
2023-04-17 00:04:54 +02:00
|
|
|
pub fn blocking_wait(mut self) {
|
|
|
|
while self.is_running() {}
|
2022-04-26 23:57:26 +02:00
|
|
|
|
2023-04-17 00:04:54 +02:00
|
|
|
// "Subsequent reads and writes cannot be moved ahead of preceding reads."
|
|
|
|
fence(Ordering::SeqCst);
|
2022-04-26 23:57:26 +02:00
|
|
|
|
2023-04-17 00:04:54 +02:00
|
|
|
core::mem::forget(self);
|
|
|
|
}
|
|
|
|
}
|
2022-04-26 23:57:26 +02:00
|
|
|
|
2023-04-17 00:04:54 +02:00
|
|
|
impl<'a, C: Channel> Drop for Transfer<'a, C> {
|
|
|
|
fn drop(&mut self) {
|
|
|
|
self.request_stop();
|
|
|
|
while self.is_running() {}
|
|
|
|
|
|
|
|
// "Subsequent reads and writes cannot be moved ahead of preceding reads."
|
|
|
|
fence(Ordering::SeqCst);
|
|
|
|
}
|
|
|
|
}
|
2022-04-26 23:57:26 +02:00
|
|
|
|
2023-04-17 00:04:54 +02:00
|
|
|
impl<'a, C: Channel> Unpin for Transfer<'a, C> {}
|
|
|
|
impl<'a, C: Channel> Future for Transfer<'a, C> {
|
|
|
|
type Output = ();
|
|
|
|
fn poll(mut self: Pin<&mut Self>, cx: &mut Context<'_>) -> Poll<Self::Output> {
|
|
|
|
STATE.ch_wakers[self.channel.index()].register(cx.waker());
|
2023-04-10 15:11:07 +02:00
|
|
|
|
2023-04-17 00:04:54 +02:00
|
|
|
if self.is_running() {
|
|
|
|
Poll::Pending
|
|
|
|
} else {
|
|
|
|
Poll::Ready(())
|
2022-04-26 23:57:26 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|