2022-09-26 05:32:45 +02:00
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use core::future::{poll_fn, Future};
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2022-09-21 06:00:35 +02:00
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use core::task::{Poll, Waker};
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2022-08-26 09:05:12 +02:00
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use atomic_polyfill::{compiler_fence, Ordering};
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use embassy_cortex_m::peripheral::{PeripheralMutex, PeripheralState, StateStorage};
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use embassy_hal_common::ring_buffer::RingBuffer;
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use embassy_sync::waitqueue::WakerRegistration;
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use super::*;
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2022-09-09 10:36:27 +02:00
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pub struct State<'d, T: Instance>(StateStorage<FullStateInner<'d, T>>);
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2022-08-26 09:05:12 +02:00
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impl<'d, T: Instance> State<'d, T> {
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2022-09-09 10:36:27 +02:00
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pub const fn new() -> Self {
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2022-08-26 09:05:12 +02:00
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Self(StateStorage::new())
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}
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}
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2022-09-09 10:36:27 +02:00
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pub struct RxState<'d, T: Instance>(StateStorage<RxStateInner<'d, T>>);
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impl<'d, T: Instance> RxState<'d, T> {
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pub const fn new() -> Self {
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Self(StateStorage::new())
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}
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}
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pub struct TxState<'d, T: Instance>(StateStorage<TxStateInner<'d, T>>);
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impl<'d, T: Instance> TxState<'d, T> {
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pub const fn new() -> Self {
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Self(StateStorage::new())
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}
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}
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struct RxStateInner<'d, T: Instance> {
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phantom: PhantomData<&'d mut T>,
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waker: WakerRegistration,
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buf: RingBuffer<'d>,
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}
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struct TxStateInner<'d, T: Instance> {
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2022-08-26 09:05:12 +02:00
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phantom: PhantomData<&'d mut T>,
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2022-09-09 10:36:27 +02:00
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waker: WakerRegistration,
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buf: RingBuffer<'d>,
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}
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2022-08-26 09:05:12 +02:00
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2022-09-09 10:36:27 +02:00
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struct FullStateInner<'d, T: Instance> {
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rx: RxStateInner<'d, T>,
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tx: TxStateInner<'d, T>,
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2022-08-26 09:05:12 +02:00
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}
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2022-09-09 10:36:27 +02:00
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unsafe impl<'d, T: Instance> Send for RxStateInner<'d, T> {}
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unsafe impl<'d, T: Instance> Sync for RxStateInner<'d, T> {}
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unsafe impl<'d, T: Instance> Send for TxStateInner<'d, T> {}
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unsafe impl<'d, T: Instance> Sync for TxStateInner<'d, T> {}
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unsafe impl<'d, T: Instance> Send for FullStateInner<'d, T> {}
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unsafe impl<'d, T: Instance> Sync for FullStateInner<'d, T> {}
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2022-08-26 09:05:12 +02:00
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pub struct BufferedUart<'d, T: Instance> {
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2022-09-09 10:36:27 +02:00
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inner: PeripheralMutex<'d, FullStateInner<'d, T>>,
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}
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2022-09-27 05:51:31 +02:00
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pub struct BufferedUartRx<'d, T: Instance> {
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2022-09-09 10:36:27 +02:00
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inner: PeripheralMutex<'d, RxStateInner<'d, T>>,
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}
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2022-09-27 05:51:31 +02:00
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pub struct BufferedUartTx<'d, T: Instance> {
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2022-09-09 10:36:27 +02:00
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inner: PeripheralMutex<'d, TxStateInner<'d, T>>,
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2022-08-26 09:05:12 +02:00
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}
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impl<'d, T: Instance> Unpin for BufferedUart<'d, T> {}
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2022-09-27 05:51:31 +02:00
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impl<'d, T: Instance> Unpin for BufferedUartRx<'d, T> {}
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impl<'d, T: Instance> Unpin for BufferedUartTx<'d, T> {}
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2022-08-26 09:05:12 +02:00
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impl<'d, T: Instance> BufferedUart<'d, T> {
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pub fn new<M: Mode>(
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state: &'d mut State<'d, T>,
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_uart: Uart<'d, T, M>,
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irq: impl Peripheral<P = T::Interrupt> + 'd,
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tx_buffer: &'d mut [u8],
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rx_buffer: &'d mut [u8],
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) -> BufferedUart<'d, T> {
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into_ref!(irq);
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let r = T::regs();
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unsafe {
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r.uartimsc().modify(|w| {
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w.set_rxim(true);
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w.set_rtim(true);
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2022-09-21 06:00:35 +02:00
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w.set_txim(true);
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2022-08-26 09:05:12 +02:00
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});
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}
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Self {
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2022-09-09 10:36:27 +02:00
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inner: PeripheralMutex::new(irq, &mut state.0, move || FullStateInner {
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tx: TxStateInner {
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phantom: PhantomData,
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waker: WakerRegistration::new(),
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buf: RingBuffer::new(tx_buffer),
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},
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rx: RxStateInner {
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phantom: PhantomData,
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waker: WakerRegistration::new(),
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buf: RingBuffer::new(rx_buffer),
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},
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}),
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}
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}
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}
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2022-09-27 05:51:31 +02:00
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impl<'d, T: Instance> BufferedUartRx<'d, T> {
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2022-09-09 10:36:27 +02:00
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pub fn new<M: Mode>(
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state: &'d mut RxState<'d, T>,
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_uart: UartRx<'d, T, M>,
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irq: impl Peripheral<P = T::Interrupt> + 'd,
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rx_buffer: &'d mut [u8],
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2022-09-27 05:51:31 +02:00
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) -> BufferedUartRx<'d, T> {
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2022-09-09 10:36:27 +02:00
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into_ref!(irq);
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let r = T::regs();
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unsafe {
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r.uartimsc().modify(|w| {
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w.set_rxim(true);
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w.set_rtim(true);
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});
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}
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Self {
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inner: PeripheralMutex::new(irq, &mut state.0, move || RxStateInner {
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phantom: PhantomData,
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buf: RingBuffer::new(rx_buffer),
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waker: WakerRegistration::new(),
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}),
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}
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}
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}
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2022-09-27 05:51:31 +02:00
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impl<'d, T: Instance> BufferedUartTx<'d, T> {
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2022-09-09 10:36:27 +02:00
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pub fn new<M: Mode>(
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state: &'d mut TxState<'d, T>,
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_uart: UartTx<'d, T, M>,
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irq: impl Peripheral<P = T::Interrupt> + 'd,
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tx_buffer: &'d mut [u8],
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2022-09-27 05:51:31 +02:00
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) -> BufferedUartTx<'d, T> {
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2022-09-09 10:36:27 +02:00
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into_ref!(irq);
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let r = T::regs();
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unsafe {
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r.uartimsc().modify(|w| {
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2022-09-21 06:00:35 +02:00
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w.set_txim(true);
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2022-09-09 10:36:27 +02:00
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});
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}
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Self {
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inner: PeripheralMutex::new(irq, &mut state.0, move || TxStateInner {
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2022-08-26 09:05:12 +02:00
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phantom: PhantomData,
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2022-09-09 10:36:27 +02:00
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buf: RingBuffer::new(tx_buffer),
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waker: WakerRegistration::new(),
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2022-08-26 09:05:12 +02:00
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}),
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}
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}
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}
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2022-09-09 10:36:27 +02:00
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impl<'d, T: Instance> PeripheralState for FullStateInner<'d, T>
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2022-08-26 09:05:12 +02:00
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where
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Self: 'd,
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{
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2022-09-09 10:36:27 +02:00
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type Interrupt = T::Interrupt;
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fn on_interrupt(&mut self) {
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self.rx.on_interrupt();
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self.tx.on_interrupt();
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}
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}
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2022-09-21 06:00:35 +02:00
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impl<'d, T: Instance> RxStateInner<'d, T>
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where
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Self: 'd,
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{
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fn read(&mut self, buf: &mut [u8], waker: &Waker) -> (Poll<Result<usize, Error>>, bool) {
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// We have data ready in buffer? Return it.
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let mut do_pend = false;
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let data = self.buf.pop_buf();
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if !data.is_empty() {
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let len = data.len().min(buf.len());
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buf[..len].copy_from_slice(&data[..len]);
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if self.buf.is_full() {
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do_pend = true;
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}
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self.buf.pop(len);
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return (Poll::Ready(Ok(len)), do_pend);
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}
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self.waker.register(waker);
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(Poll::Pending, do_pend)
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}
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fn fill_buf<'a>(&mut self, waker: &Waker) -> Poll<Result<&'a [u8], Error>> {
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// We have data ready in buffer? Return it.
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let buf = self.buf.pop_buf();
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if !buf.is_empty() {
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let buf: &[u8] = buf;
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// Safety: buffer lives as long as uart
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let buf: &[u8] = unsafe { core::mem::transmute(buf) };
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return Poll::Ready(Ok(buf));
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}
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self.waker.register(waker);
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Poll::Pending
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}
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fn consume(&mut self, amt: usize) -> bool {
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let full = self.buf.is_full();
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self.buf.pop(amt);
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full
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}
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}
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2022-09-09 10:36:27 +02:00
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impl<'d, T: Instance> PeripheralState for RxStateInner<'d, T>
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where
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Self: 'd,
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{
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type Interrupt = T::Interrupt;
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fn on_interrupt(&mut self) {
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2022-08-26 09:05:12 +02:00
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let r = T::regs();
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unsafe {
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2022-09-27 07:45:10 +02:00
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let ris = r.uartris().read();
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2022-08-26 09:05:12 +02:00
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// Clear interrupt flags
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2022-09-09 10:36:27 +02:00
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r.uarticr().modify(|w| {
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2022-08-26 09:05:12 +02:00
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w.set_rxic(true);
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w.set_rtic(true);
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});
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2022-09-27 07:45:10 +02:00
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if ris.peris() {
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warn!("Parity error");
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r.uarticr().modify(|w| {
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w.set_peic(true);
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});
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}
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if ris.feris() {
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warn!("Framing error");
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r.uarticr().modify(|w| {
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w.set_feic(true);
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});
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}
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if ris.beris() {
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warn!("Break error");
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r.uarticr().modify(|w| {
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w.set_beic(true);
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});
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}
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if ris.oeris() {
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warn!("Overrun error");
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r.uarticr().modify(|w| {
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w.set_oeic(true);
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});
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}
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2022-08-26 09:05:12 +02:00
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2022-09-27 07:45:10 +02:00
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if !r.uartfr().read().rxfe() {
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2022-09-09 10:36:27 +02:00
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let buf = self.buf.push_buf();
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2022-08-26 09:05:12 +02:00
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if !buf.is_empty() {
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buf[0] = r.uartdr().read().data();
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2022-09-09 10:36:27 +02:00
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self.buf.push(1);
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2022-08-26 09:05:12 +02:00
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} else {
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warn!("RX buffer full, discard received byte");
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}
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2022-09-09 10:36:27 +02:00
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if self.buf.is_full() {
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self.waker.wake();
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2022-08-26 09:05:12 +02:00
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}
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}
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2022-09-27 07:45:10 +02:00
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if ris.rtris() {
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2022-09-09 10:36:27 +02:00
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self.waker.wake();
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2022-08-26 09:05:12 +02:00
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};
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}
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}
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2022-09-09 10:36:27 +02:00
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}
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2022-08-26 09:05:12 +02:00
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2022-09-21 06:00:35 +02:00
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impl<'d, T: Instance> TxStateInner<'d, T>
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where
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Self: 'd,
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{
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fn write(&mut self, buf: &[u8], waker: &Waker) -> (Poll<Result<usize, Error>>, bool) {
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let empty = self.buf.is_empty();
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let tx_buf = self.buf.push_buf();
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if tx_buf.is_empty() {
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self.waker.register(waker);
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return (Poll::Pending, empty);
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}
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let n = core::cmp::min(tx_buf.len(), buf.len());
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tx_buf[..n].copy_from_slice(&buf[..n]);
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self.buf.push(n);
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(Poll::Ready(Ok(n)), empty)
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}
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fn flush(&mut self, waker: &Waker) -> Poll<Result<(), Error>> {
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if !self.buf.is_empty() {
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self.waker.register(waker);
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return Poll::Pending;
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}
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Poll::Ready(Ok(()))
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}
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}
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2022-09-09 10:36:27 +02:00
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impl<'d, T: Instance> PeripheralState for TxStateInner<'d, T>
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where
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Self: 'd,
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{
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type Interrupt = T::Interrupt;
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fn on_interrupt(&mut self) {
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2022-08-26 09:05:12 +02:00
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let r = T::regs();
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unsafe {
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2022-09-27 07:45:10 +02:00
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let buf = self.buf.pop_buf();
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if !buf.is_empty() {
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r.uartimsc().modify(|w| {
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w.set_txim(true);
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});
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r.uartdr().write(|w| w.set_data(buf[0].into()));
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self.buf.pop(1);
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self.waker.wake();
|
|
|
|
} else {
|
|
|
|
// Disable interrupt until we have something to transmit again
|
|
|
|
r.uartimsc().modify(|w| {
|
|
|
|
w.set_txim(false);
|
|
|
|
});
|
2022-08-26 09:05:12 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
impl embedded_io::Error for Error {
|
|
|
|
fn kind(&self) -> embedded_io::ErrorKind {
|
|
|
|
embedded_io::ErrorKind::Other
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
impl<'d, T: Instance> embedded_io::Io for BufferedUart<'d, T> {
|
|
|
|
type Error = Error;
|
|
|
|
}
|
|
|
|
|
2022-09-27 05:51:31 +02:00
|
|
|
impl<'d, T: Instance> embedded_io::Io for BufferedUartRx<'d, T> {
|
2022-09-09 10:36:27 +02:00
|
|
|
type Error = Error;
|
|
|
|
}
|
|
|
|
|
2022-09-27 05:51:31 +02:00
|
|
|
impl<'d, T: Instance> embedded_io::Io for BufferedUartTx<'d, T> {
|
2022-09-09 10:36:27 +02:00
|
|
|
type Error = Error;
|
|
|
|
}
|
|
|
|
|
2022-08-26 09:05:12 +02:00
|
|
|
impl<'d, T: Instance + 'd> embedded_io::asynch::Read for BufferedUart<'d, T> {
|
2022-09-09 10:36:27 +02:00
|
|
|
type ReadFuture<'a> = impl Future<Output = Result<usize, Self::Error>>
|
|
|
|
where
|
|
|
|
Self: 'a;
|
|
|
|
|
|
|
|
fn read<'a>(&'a mut self, buf: &'a mut [u8]) -> Self::ReadFuture<'a> {
|
|
|
|
poll_fn(move |cx| {
|
2022-09-21 06:00:35 +02:00
|
|
|
let (res, do_pend) = self.inner.with(|state| {
|
2022-09-09 10:36:27 +02:00
|
|
|
compiler_fence(Ordering::SeqCst);
|
2022-09-21 06:00:35 +02:00
|
|
|
state.rx.read(buf, cx.waker())
|
2022-09-09 10:36:27 +02:00
|
|
|
});
|
|
|
|
|
|
|
|
if do_pend {
|
|
|
|
self.inner.pend();
|
|
|
|
}
|
|
|
|
|
|
|
|
res
|
|
|
|
})
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2022-09-27 05:51:31 +02:00
|
|
|
impl<'d, T: Instance + 'd> embedded_io::asynch::Read for BufferedUartRx<'d, T> {
|
2022-09-09 10:36:27 +02:00
|
|
|
type ReadFuture<'a> = impl Future<Output = Result<usize, Self::Error>>
|
2022-08-26 09:05:12 +02:00
|
|
|
where
|
|
|
|
Self: 'a;
|
|
|
|
|
|
|
|
fn read<'a>(&'a mut self, buf: &'a mut [u8]) -> Self::ReadFuture<'a> {
|
|
|
|
poll_fn(move |cx| {
|
2022-09-21 06:00:35 +02:00
|
|
|
let (res, do_pend) = self.inner.with(|state| {
|
2022-08-26 09:05:12 +02:00
|
|
|
compiler_fence(Ordering::SeqCst);
|
2022-09-21 06:00:35 +02:00
|
|
|
state.read(buf, cx.waker())
|
2022-08-26 09:05:12 +02:00
|
|
|
});
|
|
|
|
|
|
|
|
if do_pend {
|
|
|
|
self.inner.pend();
|
|
|
|
}
|
|
|
|
|
|
|
|
res
|
|
|
|
})
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
impl<'d, T: Instance + 'd> embedded_io::asynch::BufRead for BufferedUart<'d, T> {
|
|
|
|
type FillBufFuture<'a> = impl Future<Output = Result<&'a [u8], Self::Error>>
|
|
|
|
where
|
|
|
|
Self: 'a;
|
|
|
|
|
|
|
|
fn fill_buf<'a>(&'a mut self) -> Self::FillBufFuture<'a> {
|
|
|
|
poll_fn(move |cx| {
|
|
|
|
self.inner.with(|state| {
|
|
|
|
compiler_fence(Ordering::SeqCst);
|
2022-09-21 06:00:35 +02:00
|
|
|
state.rx.fill_buf(cx.waker())
|
2022-09-09 10:36:27 +02:00
|
|
|
})
|
|
|
|
})
|
|
|
|
}
|
|
|
|
|
|
|
|
fn consume(&mut self, amt: usize) {
|
2022-09-21 06:00:35 +02:00
|
|
|
let signal = self.inner.with(|state| state.rx.consume(amt));
|
2022-09-09 10:36:27 +02:00
|
|
|
if signal {
|
|
|
|
self.inner.pend();
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2022-09-27 05:51:31 +02:00
|
|
|
impl<'d, T: Instance + 'd> embedded_io::asynch::BufRead for BufferedUartRx<'d, T> {
|
2022-09-09 10:36:27 +02:00
|
|
|
type FillBufFuture<'a> = impl Future<Output = Result<&'a [u8], Self::Error>>
|
|
|
|
where
|
|
|
|
Self: 'a;
|
|
|
|
|
|
|
|
fn fill_buf<'a>(&'a mut self) -> Self::FillBufFuture<'a> {
|
|
|
|
poll_fn(move |cx| {
|
|
|
|
self.inner.with(|state| {
|
|
|
|
compiler_fence(Ordering::SeqCst);
|
2022-09-21 06:00:35 +02:00
|
|
|
state.fill_buf(cx.waker())
|
2022-08-26 09:05:12 +02:00
|
|
|
})
|
|
|
|
})
|
|
|
|
}
|
|
|
|
|
|
|
|
fn consume(&mut self, amt: usize) {
|
2022-09-21 06:00:35 +02:00
|
|
|
let signal = self.inner.with(|state| state.consume(amt));
|
2022-08-26 09:05:12 +02:00
|
|
|
if signal {
|
|
|
|
self.inner.pend();
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
impl<'d, T: Instance + 'd> embedded_io::asynch::Write for BufferedUart<'d, T> {
|
|
|
|
type WriteFuture<'a> = impl Future<Output = Result<usize, Self::Error>>
|
|
|
|
where
|
|
|
|
Self: 'a;
|
|
|
|
|
|
|
|
fn write<'a>(&'a mut self, buf: &'a [u8]) -> Self::WriteFuture<'a> {
|
|
|
|
poll_fn(move |cx| {
|
2022-09-21 06:00:35 +02:00
|
|
|
let (poll, empty) = self.inner.with(|state| state.tx.write(buf, cx.waker()));
|
2022-09-09 10:36:27 +02:00
|
|
|
if empty {
|
|
|
|
self.inner.pend();
|
|
|
|
}
|
|
|
|
poll
|
|
|
|
})
|
|
|
|
}
|
|
|
|
|
|
|
|
type FlushFuture<'a> = impl Future<Output = Result<(), Self::Error>>
|
|
|
|
where
|
|
|
|
Self: 'a;
|
|
|
|
|
|
|
|
fn flush<'a>(&'a mut self) -> Self::FlushFuture<'a> {
|
2022-09-21 06:00:35 +02:00
|
|
|
poll_fn(move |cx| self.inner.with(|state| state.tx.flush(cx.waker())))
|
2022-09-09 10:36:27 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2022-09-27 05:51:31 +02:00
|
|
|
impl<'d, T: Instance + 'd> embedded_io::asynch::Write for BufferedUartTx<'d, T> {
|
2022-09-09 10:36:27 +02:00
|
|
|
type WriteFuture<'a> = impl Future<Output = Result<usize, Self::Error>>
|
|
|
|
where
|
|
|
|
Self: 'a;
|
|
|
|
|
|
|
|
fn write<'a>(&'a mut self, buf: &'a [u8]) -> Self::WriteFuture<'a> {
|
|
|
|
poll_fn(move |cx| {
|
2022-09-21 06:00:35 +02:00
|
|
|
let (poll, empty) = self.inner.with(|state| state.write(buf, cx.waker()));
|
2022-08-26 09:05:12 +02:00
|
|
|
if empty {
|
|
|
|
self.inner.pend();
|
|
|
|
}
|
|
|
|
poll
|
|
|
|
})
|
|
|
|
}
|
|
|
|
|
|
|
|
type FlushFuture<'a> = impl Future<Output = Result<(), Self::Error>>
|
|
|
|
where
|
|
|
|
Self: 'a;
|
|
|
|
|
|
|
|
fn flush<'a>(&'a mut self) -> Self::FlushFuture<'a> {
|
2022-09-21 06:00:35 +02:00
|
|
|
poll_fn(move |cx| self.inner.with(|state| state.flush(cx.waker())))
|
2022-08-26 09:05:12 +02:00
|
|
|
}
|
|
|
|
}
|