2022-11-07 00:27:21 +01:00
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use core::future::{poll_fn, Future};
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use core::slice;
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use core::task::Poll;
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2022-08-26 09:05:12 +02:00
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2022-11-07 00:27:21 +01:00
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use embassy_cortex_m::interrupt::{Interrupt, InterruptExt};
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use embassy_hal_common::atomic_ring_buffer::RingBuffer;
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use embassy_sync::waitqueue::AtomicWaker;
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2022-08-26 09:05:12 +02:00
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use super::*;
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2022-11-07 00:27:21 +01:00
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pub struct State {
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tx_waker: AtomicWaker,
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tx_buf: RingBuffer,
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rx_waker: AtomicWaker,
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rx_buf: RingBuffer,
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2022-09-09 10:36:27 +02:00
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}
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2022-11-07 00:27:21 +01:00
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impl State {
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2022-09-09 10:36:27 +02:00
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pub const fn new() -> Self {
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2022-11-07 00:27:21 +01:00
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Self {
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rx_buf: RingBuffer::new(),
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tx_buf: RingBuffer::new(),
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rx_waker: AtomicWaker::new(),
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tx_waker: AtomicWaker::new(),
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}
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2022-09-09 10:36:27 +02:00
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}
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}
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2022-08-26 09:05:12 +02:00
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pub struct BufferedUart<'d, T: Instance> {
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2022-11-07 00:27:21 +01:00
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phantom: PhantomData<&'d mut T>,
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2022-09-09 10:36:27 +02:00
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}
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2022-09-27 05:51:31 +02:00
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pub struct BufferedUartRx<'d, T: Instance> {
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2022-11-07 00:27:21 +01:00
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phantom: PhantomData<&'d mut T>,
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2022-09-09 10:36:27 +02:00
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}
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2022-09-27 05:51:31 +02:00
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pub struct BufferedUartTx<'d, T: Instance> {
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2022-11-07 00:27:21 +01:00
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phantom: PhantomData<&'d mut T>,
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2022-08-26 09:05:12 +02:00
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}
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impl<'d, T: Instance> BufferedUart<'d, T> {
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2022-11-07 00:27:21 +01:00
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pub fn new(
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_uart: impl Peripheral<P = T> + 'd,
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irq: impl Peripheral<P = T::Interrupt> + 'd,
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tx: impl Peripheral<P = impl TxPin<T>> + 'd,
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rx: impl Peripheral<P = impl RxPin<T>> + 'd,
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tx_buffer: &'d mut [u8],
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rx_buffer: &'d mut [u8],
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config: Config,
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) -> Self {
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into_ref!(tx, rx);
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Self::new_inner(
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irq,
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tx.map_into(),
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rx.map_into(),
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None,
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None,
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tx_buffer,
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rx_buffer,
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config,
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)
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}
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pub fn new_with_rtscts(
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_uart: impl Peripheral<P = T> + 'd,
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2022-08-26 09:05:12 +02:00
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irq: impl Peripheral<P = T::Interrupt> + 'd,
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2022-11-07 00:27:21 +01:00
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tx: impl Peripheral<P = impl TxPin<T>> + 'd,
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rx: impl Peripheral<P = impl RxPin<T>> + 'd,
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rts: impl Peripheral<P = impl RtsPin<T>> + 'd,
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cts: impl Peripheral<P = impl CtsPin<T>> + 'd,
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2022-08-26 09:05:12 +02:00
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tx_buffer: &'d mut [u8],
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rx_buffer: &'d mut [u8],
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2022-11-07 00:27:21 +01:00
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config: Config,
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) -> Self {
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into_ref!(tx, rx, cts, rts);
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Self::new_inner(
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irq,
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tx.map_into(),
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rx.map_into(),
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Some(rts.map_into()),
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Some(cts.map_into()),
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tx_buffer,
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rx_buffer,
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config,
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)
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}
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fn new_inner(
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irq: impl Peripheral<P = T::Interrupt> + 'd,
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mut tx: PeripheralRef<'d, AnyPin>,
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mut rx: PeripheralRef<'d, AnyPin>,
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mut rts: Option<PeripheralRef<'d, AnyPin>>,
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mut cts: Option<PeripheralRef<'d, AnyPin>>,
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tx_buffer: &'d mut [u8],
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rx_buffer: &'d mut [u8],
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config: Config,
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) -> Self {
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2022-08-26 09:05:12 +02:00
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into_ref!(irq);
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2022-11-07 00:27:21 +01:00
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super::Uart::<'d, T, Async>::init(
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Some(tx.reborrow()),
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Some(rx.reborrow()),
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rts.as_mut().map(|x| x.reborrow()),
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cts.as_mut().map(|x| x.reborrow()),
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config,
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);
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let state = T::state();
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let regs = T::regs();
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let len = tx_buffer.len();
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unsafe { state.tx_buf.init(tx_buffer.as_mut_ptr(), len) };
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let len = rx_buffer.len();
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unsafe { state.rx_buf.init(rx_buffer.as_mut_ptr(), len) };
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2022-08-26 09:05:12 +02:00
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unsafe {
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2022-11-07 00:27:21 +01:00
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regs.uartimsc().modify(|w| {
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2022-08-26 09:05:12 +02:00
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w.set_rxim(true);
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w.set_rtim(true);
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2022-09-21 06:00:35 +02:00
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w.set_txim(true);
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2022-08-26 09:05:12 +02:00
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});
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}
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2022-11-07 00:27:21 +01:00
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irq.set_handler(on_interrupt::<T>);
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irq.unpend();
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irq.enable();
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Self { phantom: PhantomData }
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2022-09-09 10:36:27 +02:00
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}
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2022-12-22 23:03:05 +01:00
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pub fn split(&mut self) -> (BufferedUartRx<'d, T>, BufferedUartTx<'d, T>) {
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(
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BufferedUartRx { phantom: PhantomData },
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BufferedUartTx { phantom: PhantomData },
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)
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}
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2022-09-09 10:36:27 +02:00
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}
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2022-09-27 05:51:31 +02:00
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impl<'d, T: Instance> BufferedUartRx<'d, T> {
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2022-11-07 00:27:21 +01:00
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pub fn new(
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_uart: impl Peripheral<P = T> + 'd,
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2022-09-09 10:36:27 +02:00
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irq: impl Peripheral<P = T::Interrupt> + 'd,
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2022-11-07 00:27:21 +01:00
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rx: impl Peripheral<P = impl RxPin<T>> + 'd,
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2022-09-09 10:36:27 +02:00
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rx_buffer: &'d mut [u8],
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2022-11-07 00:27:21 +01:00
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config: Config,
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) -> Self {
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into_ref!(rx);
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Self::new_inner(irq, rx.map_into(), None, rx_buffer, config)
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}
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pub fn new_with_rts(
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_uart: impl Peripheral<P = T> + 'd,
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irq: impl Peripheral<P = T::Interrupt> + 'd,
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rx: impl Peripheral<P = impl RxPin<T>> + 'd,
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rts: impl Peripheral<P = impl RtsPin<T>> + 'd,
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rx_buffer: &'d mut [u8],
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config: Config,
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) -> Self {
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into_ref!(rx, rts);
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Self::new_inner(irq, rx.map_into(), Some(rts.map_into()), rx_buffer, config)
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}
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fn new_inner(
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irq: impl Peripheral<P = T::Interrupt> + 'd,
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mut rx: PeripheralRef<'d, AnyPin>,
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mut rts: Option<PeripheralRef<'d, AnyPin>>,
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rx_buffer: &'d mut [u8],
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config: Config,
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) -> Self {
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2022-09-09 10:36:27 +02:00
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into_ref!(irq);
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2022-11-07 00:27:21 +01:00
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super::Uart::<'d, T, Async>::init(
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None,
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Some(rx.reborrow()),
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rts.as_mut().map(|x| x.reborrow()),
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None,
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config,
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);
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let state = T::state();
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let regs = T::regs();
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let len = rx_buffer.len();
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unsafe { state.rx_buf.init(rx_buffer.as_mut_ptr(), len) };
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2022-09-09 10:36:27 +02:00
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unsafe {
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2022-11-07 00:27:21 +01:00
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regs.uartimsc().modify(|w| {
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2022-09-09 10:36:27 +02:00
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w.set_rxim(true);
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w.set_rtim(true);
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});
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}
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2022-11-07 00:27:21 +01:00
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irq.set_handler(on_interrupt::<T>);
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irq.unpend();
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irq.enable();
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2022-09-09 10:36:27 +02:00
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2022-11-07 00:27:21 +01:00
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Self { phantom: PhantomData }
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}
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fn read<'a>(buf: &'a mut [u8]) -> impl Future<Output = Result<usize, Error>> + 'a {
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poll_fn(move |cx| {
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let state = T::state();
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let mut rx_reader = unsafe { state.rx_buf.reader() };
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let n = rx_reader.pop(|data| {
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let n = data.len().min(buf.len());
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buf[..n].copy_from_slice(&data[..n]);
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n
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});
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if n == 0 {
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state.rx_waker.register(cx.waker());
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return Poll::Pending;
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}
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Poll::Ready(Ok(n))
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})
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}
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fn fill_buf<'a>() -> impl Future<Output = Result<&'a [u8], Error>> {
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poll_fn(move |cx| {
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let state = T::state();
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let mut rx_reader = unsafe { state.rx_buf.reader() };
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let (p, n) = rx_reader.pop_buf();
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if n == 0 {
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state.rx_waker.register(cx.waker());
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return Poll::Pending;
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}
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let buf = unsafe { slice::from_raw_parts(p, n) };
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Poll::Ready(Ok(buf))
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})
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}
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fn consume(amt: usize) {
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let state = T::state();
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let mut rx_reader = unsafe { state.rx_buf.reader() };
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rx_reader.pop_done(amt)
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2022-09-09 10:36:27 +02:00
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}
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}
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2022-09-27 05:51:31 +02:00
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impl<'d, T: Instance> BufferedUartTx<'d, T> {
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2022-11-07 00:27:21 +01:00
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pub fn new(
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_uart: impl Peripheral<P = T> + 'd,
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2022-09-09 10:36:27 +02:00
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irq: impl Peripheral<P = T::Interrupt> + 'd,
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2022-11-07 00:27:21 +01:00
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tx: impl Peripheral<P = impl TxPin<T>> + 'd,
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2022-09-09 10:36:27 +02:00
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tx_buffer: &'d mut [u8],
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2022-11-07 00:27:21 +01:00
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config: Config,
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) -> Self {
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into_ref!(tx);
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Self::new_inner(irq, tx.map_into(), None, tx_buffer, config)
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}
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pub fn new_with_cts(
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_uart: impl Peripheral<P = T> + 'd,
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irq: impl Peripheral<P = T::Interrupt> + 'd,
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tx: impl Peripheral<P = impl TxPin<T>> + 'd,
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cts: impl Peripheral<P = impl CtsPin<T>> + 'd,
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tx_buffer: &'d mut [u8],
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config: Config,
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) -> Self {
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into_ref!(tx, cts);
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Self::new_inner(irq, tx.map_into(), Some(cts.map_into()), tx_buffer, config)
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}
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fn new_inner(
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irq: impl Peripheral<P = T::Interrupt> + 'd,
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mut tx: PeripheralRef<'d, AnyPin>,
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mut cts: Option<PeripheralRef<'d, AnyPin>>,
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tx_buffer: &'d mut [u8],
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config: Config,
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) -> Self {
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2022-09-09 10:36:27 +02:00
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into_ref!(irq);
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2022-11-07 00:27:21 +01:00
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super::Uart::<'d, T, Async>::init(
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Some(tx.reborrow()),
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None,
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None,
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cts.as_mut().map(|x| x.reborrow()),
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config,
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);
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let state = T::state();
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let regs = T::regs();
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let len = tx_buffer.len();
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unsafe { state.tx_buf.init(tx_buffer.as_mut_ptr(), len) };
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2022-09-09 10:36:27 +02:00
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unsafe {
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2022-11-07 00:27:21 +01:00
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regs.uartimsc().modify(|w| {
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2022-09-21 06:00:35 +02:00
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w.set_txim(true);
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2022-09-09 10:36:27 +02:00
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});
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}
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2022-11-07 00:27:21 +01:00
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irq.set_handler(on_interrupt::<T>);
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irq.unpend();
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irq.enable();
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2022-08-26 09:05:12 +02:00
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2022-11-07 00:27:21 +01:00
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Self { phantom: PhantomData }
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2022-08-26 09:05:12 +02:00
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}
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2022-11-07 00:27:21 +01:00
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fn write<'a>(buf: &'a [u8]) -> impl Future<Output = Result<usize, Error>> + 'a {
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poll_fn(move |cx| {
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let state = T::state();
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let mut tx_writer = unsafe { state.tx_buf.writer() };
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let n = tx_writer.push(|data| {
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let n = data.len().min(buf.len());
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data[..n].copy_from_slice(&buf[..n]);
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n
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});
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if n == 0 {
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state.tx_waker.register(cx.waker());
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return Poll::Pending;
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} else {
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unsafe { T::Interrupt::steal() }.pend();
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}
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Poll::Ready(Ok(n))
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})
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2022-09-09 10:36:27 +02:00
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}
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2022-11-07 00:27:21 +01:00
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fn flush() -> impl Future<Output = Result<(), Error>> {
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poll_fn(move |cx| {
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let state = T::state();
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if !state.tx_buf.is_empty() {
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state.tx_waker.register(cx.waker());
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return Poll::Pending;
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2022-09-21 06:00:35 +02:00
|
|
|
}
|
|
|
|
|
2022-11-07 00:27:21 +01:00
|
|
|
Poll::Ready(Ok(()))
|
|
|
|
})
|
2022-09-21 06:00:35 +02:00
|
|
|
}
|
2022-11-07 00:27:21 +01:00
|
|
|
}
|
2022-09-21 06:00:35 +02:00
|
|
|
|
2022-11-07 00:27:21 +01:00
|
|
|
impl<'d, T: Instance> Drop for BufferedUart<'d, T> {
|
|
|
|
fn drop(&mut self) {
|
|
|
|
unsafe {
|
|
|
|
T::Interrupt::steal().disable();
|
|
|
|
let state = T::state();
|
|
|
|
state.tx_buf.deinit();
|
|
|
|
state.rx_buf.deinit();
|
2022-09-21 06:00:35 +02:00
|
|
|
}
|
|
|
|
}
|
2022-11-07 00:27:21 +01:00
|
|
|
}
|
2022-09-21 06:00:35 +02:00
|
|
|
|
2022-11-07 00:27:21 +01:00
|
|
|
impl<'d, T: Instance> Drop for BufferedUartRx<'d, T> {
|
|
|
|
fn drop(&mut self) {
|
|
|
|
unsafe {
|
|
|
|
T::Interrupt::steal().disable();
|
|
|
|
let state = T::state();
|
|
|
|
state.tx_buf.deinit();
|
|
|
|
state.rx_buf.deinit();
|
|
|
|
}
|
2022-09-21 06:00:35 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2022-11-07 00:27:21 +01:00
|
|
|
impl<'d, T: Instance> Drop for BufferedUartTx<'d, T> {
|
|
|
|
fn drop(&mut self) {
|
2022-08-26 09:05:12 +02:00
|
|
|
unsafe {
|
2022-11-07 00:27:21 +01:00
|
|
|
T::Interrupt::steal().disable();
|
|
|
|
let state = T::state();
|
|
|
|
state.tx_buf.deinit();
|
|
|
|
state.rx_buf.deinit();
|
2022-08-26 09:05:12 +02:00
|
|
|
}
|
|
|
|
}
|
2022-09-09 10:36:27 +02:00
|
|
|
}
|
2022-08-26 09:05:12 +02:00
|
|
|
|
2022-11-07 00:27:21 +01:00
|
|
|
pub(crate) unsafe fn on_interrupt<T: Instance>(_: *mut ()) {
|
|
|
|
trace!("on_interrupt");
|
2022-09-21 06:00:35 +02:00
|
|
|
|
2022-11-07 00:27:21 +01:00
|
|
|
let r = T::regs();
|
|
|
|
let s = T::state();
|
2022-09-21 06:00:35 +02:00
|
|
|
|
2022-11-07 00:27:21 +01:00
|
|
|
unsafe {
|
|
|
|
// RX
|
2022-09-21 06:00:35 +02:00
|
|
|
|
2022-11-07 00:27:21 +01:00
|
|
|
let ris = r.uartris().read();
|
|
|
|
// Clear interrupt flags
|
|
|
|
r.uarticr().write(|w| {
|
|
|
|
w.set_rxic(true);
|
|
|
|
w.set_rtic(true);
|
|
|
|
});
|
2022-09-21 06:00:35 +02:00
|
|
|
|
2022-11-07 00:27:21 +01:00
|
|
|
if ris.peris() {
|
|
|
|
warn!("Parity error");
|
|
|
|
r.uarticr().write(|w| {
|
|
|
|
w.set_peic(true);
|
|
|
|
});
|
|
|
|
}
|
|
|
|
if ris.feris() {
|
|
|
|
warn!("Framing error");
|
|
|
|
r.uarticr().write(|w| {
|
|
|
|
w.set_feic(true);
|
|
|
|
});
|
|
|
|
}
|
|
|
|
if ris.beris() {
|
|
|
|
warn!("Break error");
|
|
|
|
r.uarticr().write(|w| {
|
|
|
|
w.set_beic(true);
|
|
|
|
});
|
|
|
|
}
|
|
|
|
if ris.oeris() {
|
|
|
|
warn!("Overrun error");
|
|
|
|
r.uarticr().write(|w| {
|
|
|
|
w.set_oeic(true);
|
|
|
|
});
|
|
|
|
}
|
2022-09-21 06:00:35 +02:00
|
|
|
|
2022-11-07 00:27:21 +01:00
|
|
|
let mut rx_writer = s.rx_buf.writer();
|
|
|
|
if !r.uartfr().read().rxfe() {
|
|
|
|
let val = r.uartdr().read().data();
|
|
|
|
if !rx_writer.push_one(val) {
|
|
|
|
warn!("RX buffer full, discard received byte");
|
2022-08-26 09:05:12 +02:00
|
|
|
}
|
2022-11-07 00:27:21 +01:00
|
|
|
s.rx_waker.wake();
|
|
|
|
}
|
|
|
|
|
|
|
|
// TX
|
|
|
|
let mut tx_reader = s.tx_buf.reader();
|
|
|
|
if let Some(val) = tx_reader.pop_one() {
|
|
|
|
r.uartimsc().modify(|w| {
|
|
|
|
w.set_txim(true);
|
|
|
|
});
|
|
|
|
r.uartdr().write(|w| w.set_data(val));
|
|
|
|
s.tx_waker.wake();
|
|
|
|
} else {
|
|
|
|
// Disable interrupt until we have something to transmit again
|
|
|
|
r.uartimsc().modify(|w| {
|
|
|
|
w.set_txim(false);
|
|
|
|
});
|
2022-08-26 09:05:12 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
impl embedded_io::Error for Error {
|
|
|
|
fn kind(&self) -> embedded_io::ErrorKind {
|
|
|
|
embedded_io::ErrorKind::Other
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
impl<'d, T: Instance> embedded_io::Io for BufferedUart<'d, T> {
|
|
|
|
type Error = Error;
|
|
|
|
}
|
|
|
|
|
2022-09-27 05:51:31 +02:00
|
|
|
impl<'d, T: Instance> embedded_io::Io for BufferedUartRx<'d, T> {
|
2022-09-09 10:36:27 +02:00
|
|
|
type Error = Error;
|
|
|
|
}
|
|
|
|
|
2022-09-27 05:51:31 +02:00
|
|
|
impl<'d, T: Instance> embedded_io::Io for BufferedUartTx<'d, T> {
|
2022-09-09 10:36:27 +02:00
|
|
|
type Error = Error;
|
|
|
|
}
|
|
|
|
|
2022-08-26 09:05:12 +02:00
|
|
|
impl<'d, T: Instance + 'd> embedded_io::asynch::Read for BufferedUart<'d, T> {
|
2022-11-21 23:31:31 +01:00
|
|
|
async fn read(&mut self, buf: &mut [u8]) -> Result<usize, Self::Error> {
|
2022-11-07 00:27:21 +01:00
|
|
|
BufferedUartRx::<'d, T>::read(buf).await
|
2022-09-09 10:36:27 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2022-09-27 05:51:31 +02:00
|
|
|
impl<'d, T: Instance + 'd> embedded_io::asynch::Read for BufferedUartRx<'d, T> {
|
2022-11-21 23:31:31 +01:00
|
|
|
async fn read(&mut self, buf: &mut [u8]) -> Result<usize, Self::Error> {
|
2022-11-07 00:27:21 +01:00
|
|
|
Self::read(buf).await
|
2022-08-26 09:05:12 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
impl<'d, T: Instance + 'd> embedded_io::asynch::BufRead for BufferedUart<'d, T> {
|
2022-11-21 23:31:31 +01:00
|
|
|
async fn fill_buf(&mut self) -> Result<&[u8], Self::Error> {
|
2022-11-07 00:27:21 +01:00
|
|
|
BufferedUartRx::<'d, T>::fill_buf().await
|
2022-09-09 10:36:27 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
fn consume(&mut self, amt: usize) {
|
2022-11-07 00:27:21 +01:00
|
|
|
BufferedUartRx::<'d, T>::consume(amt)
|
2022-09-09 10:36:27 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2022-09-27 05:51:31 +02:00
|
|
|
impl<'d, T: Instance + 'd> embedded_io::asynch::BufRead for BufferedUartRx<'d, T> {
|
2022-11-21 23:31:31 +01:00
|
|
|
async fn fill_buf(&mut self) -> Result<&[u8], Self::Error> {
|
2022-11-07 00:27:21 +01:00
|
|
|
Self::fill_buf().await
|
2022-08-26 09:05:12 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
fn consume(&mut self, amt: usize) {
|
2022-11-07 00:27:21 +01:00
|
|
|
Self::consume(amt)
|
2022-08-26 09:05:12 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
impl<'d, T: Instance + 'd> embedded_io::asynch::Write for BufferedUart<'d, T> {
|
2022-11-21 23:31:31 +01:00
|
|
|
async fn write(&mut self, buf: &[u8]) -> Result<usize, Self::Error> {
|
2022-11-07 00:27:21 +01:00
|
|
|
BufferedUartTx::<'d, T>::write(buf).await
|
2022-09-09 10:36:27 +02:00
|
|
|
}
|
|
|
|
|
2022-11-21 23:31:31 +01:00
|
|
|
async fn flush(&mut self) -> Result<(), Self::Error> {
|
2022-11-07 00:27:21 +01:00
|
|
|
BufferedUartTx::<'d, T>::flush().await
|
2022-09-09 10:36:27 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2022-09-27 05:51:31 +02:00
|
|
|
impl<'d, T: Instance + 'd> embedded_io::asynch::Write for BufferedUartTx<'d, T> {
|
2022-11-21 23:31:31 +01:00
|
|
|
async fn write(&mut self, buf: &[u8]) -> Result<usize, Self::Error> {
|
2022-11-07 00:27:21 +01:00
|
|
|
Self::write(buf).await
|
2022-08-26 09:05:12 +02:00
|
|
|
}
|
|
|
|
|
2022-11-21 23:31:31 +01:00
|
|
|
async fn flush(&mut self) -> Result<(), Self::Error> {
|
2022-11-07 00:27:21 +01:00
|
|
|
Self::flush().await
|
2022-08-26 09:05:12 +02:00
|
|
|
}
|
|
|
|
}
|