2021-05-17 19:56:13 +02:00
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#![macro_use]
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2021-07-20 19:38:44 +02:00
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use crate::dma::NoDma;
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2021-12-06 23:33:06 +01:00
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use crate::spi::{Error, Instance, RegsExt, RxDmaChannel, TxDmaChannel, WordSize};
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2021-07-20 19:38:44 +02:00
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use core::future::Future;
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2021-05-20 20:19:43 +02:00
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use core::ptr;
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2021-07-20 19:38:44 +02:00
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use embassy_traits::spi as traits;
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2021-05-17 19:56:13 +02:00
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pub use embedded_hal::spi::{Mode, Phase, Polarity, MODE_0, MODE_1, MODE_2, MODE_3};
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2021-07-21 20:09:24 +02:00
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use futures::future::join3;
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2021-07-20 21:20:16 +02:00
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2021-12-06 21:47:50 +01:00
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use super::Spi;
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2021-05-17 19:56:13 +02:00
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2021-07-20 19:38:44 +02:00
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impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
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2021-07-20 19:48:54 +02:00
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#[allow(unused)]
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2021-07-20 21:20:16 +02:00
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async fn write_dma_u8(&mut self, write: &[u8]) -> Result<(), Error>
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where
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Tx: TxDmaChannel<T>,
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{
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2021-12-06 21:24:02 +01:00
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self.set_word_size(WordSize::EightBit);
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2021-07-21 20:09:24 +02:00
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unsafe {
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T::regs().cr1().modify(|w| {
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w.set_spe(false);
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});
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}
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2021-07-20 21:20:16 +02:00
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let request = self.txdma.request();
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2021-12-06 23:33:06 +01:00
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let dst = T::regs().tx_ptr();
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2021-07-20 21:20:16 +02:00
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let f = self.txdma.write(request, write, dst);
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2021-07-21 20:09:24 +02:00
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2021-07-20 21:20:16 +02:00
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unsafe {
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T::regs().cfg1().modify(|reg| {
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reg.set_txdmaen(true);
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});
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2021-07-21 20:09:24 +02:00
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T::regs().cr1().modify(|w| {
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w.set_spe(true);
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});
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T::regs().cr1().modify(|w| {
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w.set_cstart(true);
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});
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2021-07-20 21:20:16 +02:00
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}
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f.await;
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2021-07-21 20:09:24 +02:00
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unsafe {
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T::regs().cfg1().modify(|reg| {
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reg.set_txdmaen(false);
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});
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T::regs().cr1().modify(|w| {
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w.set_spe(false);
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});
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}
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2021-07-20 21:20:16 +02:00
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Ok(())
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2021-07-20 19:38:44 +02:00
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}
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2021-07-20 19:48:54 +02:00
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#[allow(unused)]
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2021-07-20 21:20:16 +02:00
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async fn read_dma_u8(&mut self, read: &mut [u8]) -> Result<(), Error>
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where
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Tx: TxDmaChannel<T>,
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Rx: RxDmaChannel<T>,
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{
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2021-12-06 21:24:02 +01:00
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self.set_word_size(WordSize::EightBit);
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2021-07-21 20:09:24 +02:00
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unsafe {
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T::regs().cr1().modify(|w| {
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w.set_spe(false);
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});
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T::regs().cfg1().modify(|reg| {
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reg.set_rxdmaen(true);
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});
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}
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2021-07-21 16:42:22 +02:00
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let clock_byte_count = read.len();
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let rx_request = self.rxdma.request();
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2021-12-06 23:33:06 +01:00
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let rx_src = T::regs().rx_ptr();
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2021-07-21 16:42:22 +02:00
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let rx_f = self.rxdma.read(rx_request, rx_src, read);
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let tx_request = self.txdma.request();
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2021-12-06 23:33:06 +01:00
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let tx_dst = T::regs().tx_ptr();
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2021-07-21 16:42:22 +02:00
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let clock_byte = 0x00;
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let tx_f = self
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.txdma
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.write_x(tx_request, &clock_byte, clock_byte_count, tx_dst);
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unsafe {
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T::regs().cfg1().modify(|reg| {
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reg.set_txdmaen(true);
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2021-07-21 20:09:24 +02:00
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});
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T::regs().cr1().modify(|w| {
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w.set_spe(true);
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});
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T::regs().cr1().modify(|w| {
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w.set_cstart(true);
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2021-07-21 16:42:22 +02:00
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});
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}
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2021-07-21 20:09:24 +02:00
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join3(tx_f, rx_f, Self::wait_for_idle()).await;
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unsafe {
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T::regs().cfg1().modify(|reg| {
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reg.set_rxdmaen(false);
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reg.set_txdmaen(false);
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});
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T::regs().cr1().modify(|w| {
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w.set_spe(false);
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});
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}
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2021-07-21 16:42:22 +02:00
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Ok(())
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2021-07-20 19:38:44 +02:00
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}
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2021-07-20 19:48:54 +02:00
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#[allow(unused)]
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2021-07-20 21:20:16 +02:00
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async fn read_write_dma_u8(&mut self, read: &mut [u8], write: &[u8]) -> Result<(), Error>
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where
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Tx: TxDmaChannel<T>,
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Rx: RxDmaChannel<T>,
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{
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2021-07-22 15:28:42 +02:00
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assert!(read.len() >= write.len());
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2021-12-06 21:24:02 +01:00
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self.set_word_size(WordSize::EightBit);
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2021-07-21 20:09:24 +02:00
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unsafe {
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T::regs().cr1().modify(|w| {
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w.set_spe(false);
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});
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T::regs().cfg1().modify(|reg| {
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reg.set_rxdmaen(true);
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});
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2021-12-02 11:38:43 +01:00
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// Flush the read buffer to avoid errornous data from being read
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while T::regs().sr().read().rxp() {
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let _ = T::regs().rxdr().read();
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}
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2021-07-21 20:09:24 +02:00
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}
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2021-07-20 21:33:42 +02:00
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2021-07-20 21:20:16 +02:00
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let rx_request = self.rxdma.request();
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2021-12-06 23:33:06 +01:00
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let rx_src = T::regs().rx_ptr();
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2021-07-21 20:09:24 +02:00
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let rx_f = self
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.rxdma
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.read(rx_request, rx_src, &mut read[0..write.len()]);
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2021-07-20 21:20:16 +02:00
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let tx_request = self.txdma.request();
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2021-12-06 23:33:06 +01:00
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let tx_dst = T::regs().tx_ptr();
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2021-07-21 16:42:22 +02:00
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let tx_f = self.txdma.write(tx_request, write, tx_dst);
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2021-07-20 21:20:16 +02:00
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unsafe {
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T::regs().cfg1().modify(|reg| {
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reg.set_txdmaen(true);
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2021-07-21 20:09:24 +02:00
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});
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T::regs().cr1().modify(|w| {
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w.set_spe(true);
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});
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T::regs().cr1().modify(|w| {
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w.set_cstart(true);
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2021-07-20 21:20:16 +02:00
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});
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}
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2021-07-21 20:09:24 +02:00
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join3(tx_f, rx_f, Self::wait_for_idle()).await;
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unsafe {
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T::regs().cfg1().modify(|reg| {
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reg.set_rxdmaen(false);
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reg.set_txdmaen(false);
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});
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T::regs().cr1().modify(|w| {
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w.set_spe(false);
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});
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}
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2021-07-20 21:20:16 +02:00
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Ok(())
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2021-07-20 19:38:44 +02:00
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}
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2021-07-21 20:09:24 +02:00
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async fn wait_for_idle() {
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unsafe {
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while !T::regs().sr().read().txc() {
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// spin
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}
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while T::regs().sr().read().rxplvl().0 > 0 {
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// spin
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}
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}
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}
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2021-05-17 19:56:13 +02:00
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}
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2021-12-06 21:47:50 +01:00
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impl<'d, T: Instance> embedded_hal::blocking::spi::Write<u8> for Spi<'d, T, NoDma, NoDma> {
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2021-05-17 19:56:13 +02:00
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type Error = Error;
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fn write(&mut self, words: &[u8]) -> Result<(), Self::Error> {
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2021-12-06 21:24:02 +01:00
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self.set_word_size(WordSize::EightBit);
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2021-05-17 19:56:13 +02:00
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let regs = T::regs();
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for word in words.iter() {
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while unsafe { !regs.sr().read().txp() } {
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// spin
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}
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unsafe {
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2021-12-06 23:33:06 +01:00
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ptr::write_volatile(regs.tx_ptr(), *word);
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2021-05-20 20:13:45 +02:00
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regs.cr1().modify(|reg| reg.set_cstart(true));
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2021-05-17 19:56:13 +02:00
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}
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loop {
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let sr = unsafe { regs.sr().read() };
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if sr.tifre() {
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return Err(Error::Framing);
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}
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if sr.ovr() {
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return Err(Error::Overrun);
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}
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if sr.crce() {
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return Err(Error::Crc);
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}
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if !sr.txp() {
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// loop waiting for TXE
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2021-08-24 20:44:31 +02:00
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continue;
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2021-05-17 19:56:13 +02:00
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}
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2021-08-24 20:44:31 +02:00
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break;
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}
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unsafe {
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// discard read to prevent pverrun.
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2021-12-06 23:33:06 +01:00
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let _: u8 = ptr::read_volatile(T::regs().rx_ptr());
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2021-05-17 19:56:13 +02:00
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}
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}
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2021-08-24 20:44:31 +02:00
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while unsafe { !regs.sr().read().txc() } {
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// spin
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}
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2021-05-17 19:56:13 +02:00
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Ok(())
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}
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}
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2021-12-06 21:47:50 +01:00
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impl<'d, T: Instance> embedded_hal::blocking::spi::Transfer<u8> for Spi<'d, T, NoDma, NoDma> {
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2021-05-17 19:56:13 +02:00
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type Error = Error;
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fn transfer<'w>(&mut self, words: &'w mut [u8]) -> Result<&'w [u8], Self::Error> {
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2021-12-06 21:24:02 +01:00
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self.set_word_size(WordSize::EightBit);
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2021-05-17 19:56:13 +02:00
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let regs = T::regs();
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2021-06-05 10:15:35 +02:00
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for word in words.iter_mut() {
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2021-05-20 20:13:45 +02:00
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unsafe {
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regs.cr1().modify(|reg| {
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reg.set_ssi(false);
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});
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}
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2021-05-17 19:56:13 +02:00
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while unsafe { !regs.sr().read().txp() } {
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// spin
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}
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unsafe {
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2021-12-06 23:33:06 +01:00
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ptr::write_volatile(T::regs().tx_ptr(), *word);
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2021-05-20 20:13:45 +02:00
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regs.cr1().modify(|reg| reg.set_cstart(true));
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2021-05-17 19:56:13 +02:00
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}
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2021-05-20 20:13:45 +02:00
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loop {
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let sr = unsafe { regs.sr().read() };
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if sr.rxp() {
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break;
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}
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if sr.tifre() {
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return Err(Error::Framing);
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}
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if sr.ovr() {
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return Err(Error::Overrun);
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}
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if sr.crce() {
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return Err(Error::Crc);
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}
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}
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unsafe {
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2021-12-06 23:33:06 +01:00
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*word = ptr::read_volatile(T::regs().rx_ptr());
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2021-05-17 19:56:13 +02:00
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}
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let sr = unsafe { regs.sr().read() };
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if sr.tifre() {
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return Err(Error::Framing);
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}
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if sr.ovr() {
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return Err(Error::Overrun);
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}
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if sr.crce() {
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return Err(Error::Crc);
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}
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}
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Ok(words)
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}
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}
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2021-12-06 21:47:50 +01:00
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impl<'d, T: Instance> embedded_hal::blocking::spi::Write<u16> for Spi<'d, T, NoDma, NoDma> {
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2021-05-17 19:56:13 +02:00
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type Error = Error;
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fn write(&mut self, words: &[u16]) -> Result<(), Self::Error> {
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2021-12-06 21:24:02 +01:00
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self.set_word_size(WordSize::SixteenBit);
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2021-05-17 19:56:13 +02:00
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let regs = T::regs();
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for word in words.iter() {
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while unsafe { !regs.sr().read().txp() } {
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// spin
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}
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unsafe {
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2021-05-20 20:13:45 +02:00
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let txdr = regs.txdr().ptr() as *mut u16;
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2021-05-20 20:19:43 +02:00
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ptr::write_volatile(txdr, *word);
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2021-05-20 20:13:45 +02:00
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regs.cr1().modify(|reg| reg.set_cstart(true));
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2021-05-17 19:56:13 +02:00
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}
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loop {
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let sr = unsafe { regs.sr().read() };
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if sr.tifre() {
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return Err(Error::Framing);
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}
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if sr.ovr() {
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return Err(Error::Overrun);
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}
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if sr.crce() {
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return Err(Error::Crc);
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}
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if !sr.txp() {
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// loop waiting for TXE
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2021-08-24 20:44:31 +02:00
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continue;
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2021-05-17 19:56:13 +02:00
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}
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2021-08-24 20:44:31 +02:00
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break;
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2021-05-17 19:56:13 +02:00
|
|
|
}
|
2021-08-24 20:44:31 +02:00
|
|
|
|
|
|
|
unsafe {
|
|
|
|
let rxdr = regs.rxdr().ptr() as *const u8;
|
|
|
|
// discard read to prevent pverrun.
|
|
|
|
let _ = ptr::read_volatile(rxdr);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
while unsafe { !regs.sr().read().txc() } {
|
|
|
|
// spin
|
2021-05-17 19:56:13 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
Ok(())
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2021-12-06 21:47:50 +01:00
|
|
|
impl<'d, T: Instance> embedded_hal::blocking::spi::Transfer<u16> for Spi<'d, T, NoDma, NoDma> {
|
2021-05-17 19:56:13 +02:00
|
|
|
type Error = Error;
|
|
|
|
|
|
|
|
fn transfer<'w>(&mut self, words: &'w mut [u16]) -> Result<&'w [u16], Self::Error> {
|
2021-12-06 21:24:02 +01:00
|
|
|
self.set_word_size(WordSize::SixteenBit);
|
2021-05-17 19:56:13 +02:00
|
|
|
let regs = T::regs();
|
|
|
|
|
|
|
|
for word in words.iter_mut() {
|
|
|
|
while unsafe { !regs.sr().read().txp() } {
|
|
|
|
// spin
|
|
|
|
}
|
|
|
|
unsafe {
|
2021-05-20 20:13:45 +02:00
|
|
|
let txdr = regs.txdr().ptr() as *mut u16;
|
2021-05-20 20:19:43 +02:00
|
|
|
ptr::write_volatile(txdr, *word);
|
2021-05-20 20:13:45 +02:00
|
|
|
regs.cr1().modify(|reg| reg.set_cstart(true));
|
|
|
|
}
|
|
|
|
|
|
|
|
loop {
|
|
|
|
let sr = unsafe { regs.sr().read() };
|
|
|
|
|
|
|
|
if sr.rxp() {
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
if sr.tifre() {
|
|
|
|
return Err(Error::Framing);
|
|
|
|
}
|
|
|
|
if sr.ovr() {
|
|
|
|
return Err(Error::Overrun);
|
|
|
|
}
|
|
|
|
if sr.crce() {
|
|
|
|
return Err(Error::Crc);
|
|
|
|
}
|
2021-05-17 19:56:13 +02:00
|
|
|
}
|
2021-05-20 20:13:45 +02:00
|
|
|
|
|
|
|
unsafe {
|
|
|
|
let rxdr = regs.rxdr().ptr() as *const u16;
|
2021-05-20 20:19:43 +02:00
|
|
|
*word = ptr::read_volatile(rxdr);
|
2021-05-17 19:56:13 +02:00
|
|
|
}
|
|
|
|
let sr = unsafe { regs.sr().read() };
|
|
|
|
if sr.tifre() {
|
|
|
|
return Err(Error::Framing);
|
|
|
|
}
|
|
|
|
if sr.ovr() {
|
|
|
|
return Err(Error::Overrun);
|
|
|
|
}
|
|
|
|
if sr.crce() {
|
|
|
|
return Err(Error::Crc);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
Ok(words)
|
|
|
|
}
|
|
|
|
}
|
2021-07-20 15:19:23 +02:00
|
|
|
|
2021-07-20 19:38:44 +02:00
|
|
|
impl<'d, T: Instance, Tx, Rx> traits::Spi<u8> for Spi<'d, T, Tx, Rx> {
|
2021-07-20 15:19:23 +02:00
|
|
|
type Error = super::Error;
|
2021-07-20 19:38:44 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
impl<'d, T: Instance, Tx: TxDmaChannel<T>, Rx> traits::Write<u8> for Spi<'d, T, Tx, Rx> {
|
|
|
|
#[rustfmt::skip]
|
2021-08-24 20:56:45 +02:00
|
|
|
type WriteFuture<'a> where Self: 'a = impl Future<Output = Result<(), Self::Error>> + 'a;
|
2021-07-20 19:38:44 +02:00
|
|
|
|
|
|
|
fn write<'a>(&'a mut self, data: &'a [u8]) -> Self::WriteFuture<'a> {
|
|
|
|
self.write_dma_u8(data)
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
impl<'d, T: Instance, Tx: TxDmaChannel<T>, Rx: RxDmaChannel<T>> traits::Read<u8>
|
|
|
|
for Spi<'d, T, Tx, Rx>
|
|
|
|
{
|
|
|
|
#[rustfmt::skip]
|
2021-08-24 20:56:45 +02:00
|
|
|
type ReadFuture<'a> where Self: 'a = impl Future<Output = Result<(), Self::Error>> + 'a;
|
2021-07-20 15:19:23 +02:00
|
|
|
|
|
|
|
fn read<'a>(&'a mut self, data: &'a mut [u8]) -> Self::ReadFuture<'a> {
|
2021-07-20 19:38:44 +02:00
|
|
|
self.read_dma_u8(data)
|
2021-07-20 15:19:23 +02:00
|
|
|
}
|
2021-07-20 19:38:44 +02:00
|
|
|
}
|
2021-07-20 15:19:23 +02:00
|
|
|
|
2021-07-20 19:38:44 +02:00
|
|
|
impl<'d, T: Instance, Tx: TxDmaChannel<T>, Rx: RxDmaChannel<T>> traits::FullDuplex<u8>
|
|
|
|
for Spi<'d, T, Tx, Rx>
|
|
|
|
{
|
|
|
|
#[rustfmt::skip]
|
2021-08-24 20:56:45 +02:00
|
|
|
type WriteReadFuture<'a> where Self: 'a = impl Future<Output = Result<(), Self::Error>> + 'a;
|
2021-07-20 15:19:23 +02:00
|
|
|
|
|
|
|
fn read_write<'a>(
|
|
|
|
&'a mut self,
|
|
|
|
read: &'a mut [u8],
|
|
|
|
write: &'a [u8],
|
|
|
|
) -> Self::WriteReadFuture<'a> {
|
2021-07-20 19:38:44 +02:00
|
|
|
self.read_write_dma_u8(read, write)
|
2021-07-20 15:19:23 +02:00
|
|
|
}
|
|
|
|
}
|