2023-03-20 15:34:30 +01:00
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//! Direct Memory Access (DMA)
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2022-09-22 16:42:49 +02:00
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use core::future::Future;
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2022-08-18 19:39:13 +02:00
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use core::pin::Pin;
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2021-03-29 04:11:32 +02:00
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use core::sync::atomic::{compiler_fence, Ordering};
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2022-08-18 21:27:37 +02:00
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use core::task::{Context, Poll};
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2021-03-29 04:11:32 +02:00
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2023-07-28 13:23:22 +02:00
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use embassy_hal_internal::{impl_peripheral, into_ref, Peripheral, PeripheralRef};
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2022-08-23 13:28:14 +02:00
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use embassy_sync::waitqueue::AtomicWaker;
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2022-08-18 21:09:50 +02:00
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use pac::dma::vals::DataSize;
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2022-08-18 10:14:37 +02:00
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2023-06-08 16:08:40 +02:00
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use crate::interrupt::InterruptExt;
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2021-05-17 03:01:30 +02:00
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use crate::pac::dma::vals;
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2022-08-19 09:48:58 +02:00
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use crate::{interrupt, pac, peripherals};
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2023-06-08 18:00:19 +02:00
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#[cfg(feature = "rt")]
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2022-08-19 09:48:58 +02:00
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#[interrupt]
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2023-06-16 01:32:18 +02:00
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fn DMA_IRQ_0() {
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2022-08-19 09:48:58 +02:00
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let ints0 = pac::DMA.ints0().read().ints0();
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2022-08-23 12:28:17 +02:00
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for channel in 0..CHANNEL_COUNT {
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2022-08-23 13:20:36 +02:00
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let ctrl_trig = pac::DMA.ch(channel).ctrl_trig().read();
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if ctrl_trig.ahb_error() {
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2022-08-23 13:46:48 +02:00
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panic!("DMA: error on DMA_0 channel {}", channel);
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2022-08-23 13:20:36 +02:00
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}
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2022-08-23 12:28:17 +02:00
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if ints0 & (1 << channel) == (1 << channel) {
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CHANNEL_WAKERS[channel].wake();
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2022-08-19 09:48:58 +02:00
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}
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2022-08-23 12:28:17 +02:00
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}
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pac::DMA.ints0().write(|w| w.set_ints0(ints0));
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}
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pub(crate) unsafe fn init() {
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2023-06-08 16:08:40 +02:00
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interrupt::DMA_IRQ_0.disable();
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interrupt::DMA_IRQ_0.set_priority(interrupt::Priority::P3);
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2022-08-23 12:28:17 +02:00
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pac::DMA.inte0().write(|w| w.set_inte0(0xFFFF));
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2023-06-08 16:08:40 +02:00
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interrupt::DMA_IRQ_0.enable();
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2022-08-19 09:48:58 +02:00
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}
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2021-03-29 04:11:32 +02:00
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2022-08-23 12:28:17 +02:00
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pub unsafe fn read<'a, C: Channel, W: Word>(
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ch: impl Peripheral<P = C> + 'a,
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from: *const W,
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2022-09-01 12:00:11 +02:00
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to: *mut [W],
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2022-08-26 12:50:12 +02:00
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dreq: u8,
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2022-08-23 12:28:17 +02:00
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) -> Transfer<'a, C> {
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2022-09-01 12:00:11 +02:00
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let (to_ptr, len) = crate::dma::slice_ptr_parts(to);
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2022-08-26 12:50:12 +02:00
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copy_inner(
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ch,
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from as *const u32,
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2022-09-01 12:00:11 +02:00
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to_ptr as *mut u32,
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2022-08-26 12:50:12 +02:00
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len,
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W::size(),
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false,
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true,
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dreq,
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)
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2022-08-18 21:09:50 +02:00
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}
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2022-08-23 12:28:17 +02:00
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pub unsafe fn write<'a, C: Channel, W: Word>(
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ch: impl Peripheral<P = C> + 'a,
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2022-09-01 12:00:11 +02:00
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from: *const [W],
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2022-08-23 12:28:17 +02:00
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to: *mut W,
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2022-08-26 12:50:12 +02:00
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dreq: u8,
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2022-08-23 12:28:17 +02:00
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) -> Transfer<'a, C> {
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2022-09-01 12:00:11 +02:00
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let (from_ptr, len) = crate::dma::slice_ptr_parts(from);
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2022-08-26 12:50:12 +02:00
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copy_inner(
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ch,
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2022-09-01 12:00:11 +02:00
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from_ptr as *const u32,
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2022-08-26 12:50:12 +02:00
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to as *mut u32,
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len,
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W::size(),
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true,
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false,
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dreq,
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)
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2022-08-19 10:11:03 +02:00
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}
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2023-08-15 22:47:03 +02:00
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// static mut so that this is allocated in RAM.
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static mut DUMMY: u32 = 0;
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2023-06-05 22:28:14 +02:00
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2022-09-18 21:02:05 +02:00
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pub unsafe fn write_repeated<'a, C: Channel, W: Word>(
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ch: impl Peripheral<P = C> + 'a,
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to: *mut W,
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len: usize,
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dreq: u8,
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) -> Transfer<'a, C> {
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copy_inner(
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ch,
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2023-08-15 22:47:03 +02:00
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&mut DUMMY as *const u32,
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2022-09-18 21:02:05 +02:00
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to as *mut u32,
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len,
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W::size(),
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false,
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false,
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dreq,
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)
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}
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2022-08-23 12:28:17 +02:00
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pub unsafe fn copy<'a, C: Channel, W: Word>(
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ch: impl Peripheral<P = C> + 'a,
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from: &[W],
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to: &mut [W],
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) -> Transfer<'a, C> {
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2022-08-19 10:11:03 +02:00
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let (from_ptr, from_len) = crate::dma::slice_ptr_parts(from);
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let (to_ptr, to_len) = crate::dma::slice_ptr_parts_mut(to);
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assert_eq!(from_len, to_len);
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copy_inner(
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ch,
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from_ptr as *const u32,
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to_ptr as *mut u32,
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from_len,
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W::size(),
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true,
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true,
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2022-08-26 12:50:12 +02:00
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vals::TreqSel::PERMANENT.0,
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2022-08-19 10:11:03 +02:00
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)
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2022-08-18 21:09:50 +02:00
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}
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2021-03-29 04:11:32 +02:00
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2022-08-19 10:11:03 +02:00
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fn copy_inner<'a, C: Channel>(
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2022-08-18 21:09:50 +02:00
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ch: impl Peripheral<P = C> + 'a,
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from: *const u32,
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to: *mut u32,
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len: usize,
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data_size: DataSize,
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2022-08-19 10:11:03 +02:00
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incr_read: bool,
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incr_write: bool,
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2022-08-26 12:50:12 +02:00
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dreq: u8,
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2022-08-18 21:09:50 +02:00
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) -> Transfer<'a, C> {
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2022-08-18 19:39:13 +02:00
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into_ref!(ch);
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2021-03-29 04:11:32 +02:00
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2023-06-16 01:32:18 +02:00
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let p = ch.regs();
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2021-03-29 04:11:32 +02:00
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2023-06-16 01:32:18 +02:00
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p.read_addr().write_value(from as u32);
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p.write_addr().write_value(to as u32);
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p.trans_count().write_value(len as u32);
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2021-03-29 04:11:32 +02:00
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2023-06-16 01:32:18 +02:00
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compiler_fence(Ordering::SeqCst);
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2021-03-29 04:11:32 +02:00
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2023-06-16 01:32:18 +02:00
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p.ctrl_trig().write(|w| {
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// TODO: Add all DREQ options to pac vals::TreqSel, and use
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// `set_treq:sel`
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w.0 = ((dreq as u32) & 0x3f) << 15usize;
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w.set_data_size(data_size);
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w.set_incr_read(incr_read);
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w.set_incr_write(incr_write);
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w.set_chain_to(ch.number());
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w.set_en(true);
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});
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2021-03-29 04:11:32 +02:00
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2023-06-16 01:32:18 +02:00
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compiler_fence(Ordering::SeqCst);
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2022-08-18 19:39:13 +02:00
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Transfer::new(ch)
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}
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2023-02-24 20:01:41 +01:00
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#[must_use = "futures do nothing unless you `.await` or poll them"]
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2022-08-19 10:11:03 +02:00
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pub struct Transfer<'a, C: Channel> {
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2022-08-18 19:39:13 +02:00
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channel: PeripheralRef<'a, C>,
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}
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impl<'a, C: Channel> Transfer<'a, C> {
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pub(crate) fn new(channel: impl Peripheral<P = C> + 'a) -> Self {
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into_ref!(channel);
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2022-08-19 09:48:58 +02:00
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2022-08-18 19:39:13 +02:00
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Self { channel }
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}
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}
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impl<'a, C: Channel> Drop for Transfer<'a, C> {
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fn drop(&mut self) {
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2022-08-18 20:30:24 +02:00
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let p = self.channel.regs();
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2023-06-16 01:32:18 +02:00
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pac::DMA
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.chan_abort()
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.modify(|m| m.set_chan_abort(1 << self.channel.number()));
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while p.ctrl_trig().read().busy() {}
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2022-08-18 19:39:13 +02:00
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}
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}
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impl<'a, C: Channel> Unpin for Transfer<'a, C> {}
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impl<'a, C: Channel> Future for Transfer<'a, C> {
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type Output = ();
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2022-08-18 21:09:50 +02:00
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fn poll(self: Pin<&mut Self>, cx: &mut Context<'_>) -> Poll<Self::Output> {
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2022-08-19 09:48:58 +02:00
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// We need to register/re-register the waker for each poll because any
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// calls to wake will deregister the waker.
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2022-08-18 21:27:37 +02:00
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CHANNEL_WAKERS[self.channel.number() as usize].register(cx.waker());
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2022-08-18 20:30:50 +02:00
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2023-06-16 01:32:18 +02:00
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if self.channel.regs().ctrl_trig().read().busy() {
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2022-08-18 20:30:50 +02:00
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Poll::Pending
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} else {
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Poll::Ready(())
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}
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}
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}
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2022-09-23 08:12:32 +02:00
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pub(crate) const CHANNEL_COUNT: usize = 12;
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2022-08-18 21:27:37 +02:00
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const NEW_AW: AtomicWaker = AtomicWaker::new();
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static CHANNEL_WAKERS: [AtomicWaker; CHANNEL_COUNT] = [NEW_AW; CHANNEL_COUNT];
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2022-08-18 20:30:50 +02:00
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2021-03-29 04:11:32 +02:00
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mod sealed {
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2022-08-18 19:39:13 +02:00
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pub trait Channel {}
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pub trait Word {}
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}
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2021-03-29 04:11:32 +02:00
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2022-08-18 19:39:13 +02:00
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pub trait Channel: Peripheral<P = Self> + sealed::Channel + Into<AnyChannel> + Sized + 'static {
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fn number(&self) -> u8;
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2021-03-29 04:11:32 +02:00
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2022-08-18 19:39:13 +02:00
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fn regs(&self) -> pac::dma::Channel {
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pac::DMA.ch(self.number() as _)
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}
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fn degrade(self) -> AnyChannel {
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2022-08-18 20:30:24 +02:00
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AnyChannel { number: self.number() }
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2021-03-29 04:11:32 +02:00
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}
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}
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2022-08-18 19:39:13 +02:00
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pub trait Word: sealed::Word {
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fn size() -> vals::DataSize;
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}
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impl sealed::Word for u8 {}
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impl Word for u8 {
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fn size() -> vals::DataSize {
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vals::DataSize::SIZE_BYTE
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}
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}
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impl sealed::Word for u16 {}
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impl Word for u16 {
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fn size() -> vals::DataSize {
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vals::DataSize::SIZE_HALFWORD
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}
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}
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impl sealed::Word for u32 {}
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impl Word for u32 {
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fn size() -> vals::DataSize {
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vals::DataSize::SIZE_WORD
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}
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}
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2021-03-29 04:11:32 +02:00
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pub struct AnyChannel {
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number: u8,
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}
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2022-08-18 19:39:13 +02:00
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impl_peripheral!(AnyChannel);
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impl sealed::Channel for AnyChannel {}
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impl Channel for AnyChannel {
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2021-03-29 04:11:32 +02:00
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fn number(&self) -> u8 {
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self.number
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}
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}
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macro_rules! channel {
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2022-08-18 19:39:13 +02:00
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($name:ident, $num:expr) => {
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impl sealed::Channel for peripherals::$name {}
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impl Channel for peripherals::$name {
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2021-03-29 04:11:32 +02:00
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fn number(&self) -> u8 {
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$num
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}
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}
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2022-08-18 19:39:13 +02:00
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impl From<peripherals::$name> for crate::dma::AnyChannel {
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fn from(val: peripherals::$name) -> Self {
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crate::dma::Channel::degrade(val)
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}
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}
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2021-03-29 04:11:32 +02:00
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};
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}
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2022-08-18 21:09:50 +02:00
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// TODO: replace transmutes with core::ptr::metadata once it's stable
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#[allow(unused)]
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pub(crate) fn slice_ptr_parts<T>(slice: *const [T]) -> (usize, usize) {
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unsafe { core::mem::transmute(slice) }
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}
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#[allow(unused)]
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pub(crate) fn slice_ptr_parts_mut<T>(slice: *mut [T]) -> (usize, usize) {
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unsafe { core::mem::transmute(slice) }
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}
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2021-03-29 04:11:32 +02:00
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channel!(DMA_CH0, 0);
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channel!(DMA_CH1, 1);
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channel!(DMA_CH2, 2);
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channel!(DMA_CH3, 3);
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channel!(DMA_CH4, 4);
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channel!(DMA_CH5, 5);
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channel!(DMA_CH6, 6);
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channel!(DMA_CH7, 7);
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channel!(DMA_CH8, 8);
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channel!(DMA_CH9, 9);
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channel!(DMA_CH10, 10);
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channel!(DMA_CH11, 11);
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