2023-05-30 00:10:36 +02:00
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#![macro_use]
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pub use defmt::*;
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#[allow(unused)]
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use embassy_stm32::time::Hertz;
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use embassy_stm32::Config;
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use {defmt_rtt as _, panic_probe as _};
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#[cfg(feature = "stm32f103c8")]
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teleprobe_meta::target!(b"bluepill-stm32f103c8");
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#[cfg(feature = "stm32g491re")]
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teleprobe_meta::target!(b"nucleo-stm32g491re");
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#[cfg(feature = "stm32g071rb")]
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teleprobe_meta::target!(b"nucleo-stm32g071rb");
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#[cfg(feature = "stm32f429zi")]
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teleprobe_meta::target!(b"nucleo-stm32f429zi");
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#[cfg(feature = "stm32wb55rg")]
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teleprobe_meta::target!(b"nucleo-stm32wb55rg");
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#[cfg(feature = "stm32h755zi")]
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teleprobe_meta::target!(b"nucleo-stm32h755zi");
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#[cfg(feature = "stm32u585ai")]
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teleprobe_meta::target!(b"iot-stm32u585ai");
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#[cfg(feature = "stm32h563zi")]
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teleprobe_meta::target!(b"nucleo-stm32h563zi");
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#[cfg(feature = "stm32c031c6")]
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teleprobe_meta::target!(b"nucleo-stm32c031c6");
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2023-09-25 22:34:18 +02:00
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macro_rules! define_peris {
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($($name:ident = $peri:ident,)* $(@irq $irq_name:ident = $irq_code:tt,)*) => {
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#[allow(unused_macros)]
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macro_rules! peri {
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$(
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($p:expr, $name) => {
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$p.$peri
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};
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)*
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}
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#[allow(unused_macros)]
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macro_rules! irqs {
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$(
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($irq_name) => {{
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embassy_stm32::bind_interrupts!(struct Irqs $irq_code);
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Irqs
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}};
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)*
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}
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#[allow(unused)]
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#[allow(non_camel_case_types)]
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pub mod peris {
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$(
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pub type $name = embassy_stm32::peripherals::$peri;
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)*
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}
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};
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}
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#[cfg(feature = "stm32f103c8")]
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define_peris!(
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UART = USART1, UART_TX = PA9, UART_RX = PA10, UART_TX_DMA = DMA1_CH4, UART_RX_DMA = DMA1_CH5,
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SPI = SPI1, SPI_SCK = PA5, SPI_MOSI = PA7, SPI_MISO = PA6, SPI_TX_DMA = DMA1_CH3, SPI_RX_DMA = DMA1_CH2,
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@irq UART = {USART1 => embassy_stm32::usart::InterruptHandler<embassy_stm32::peripherals::USART1>;},
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);
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#[cfg(feature = "stm32g491re")]
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define_peris!(
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UART = USART1, UART_TX = PC4, UART_RX = PC5, UART_TX_DMA = DMA1_CH1, UART_RX_DMA = DMA1_CH2,
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SPI = SPI1, SPI_SCK = PA5, SPI_MOSI = PA7, SPI_MISO = PA6, SPI_TX_DMA = DMA1_CH1, SPI_RX_DMA = DMA1_CH2,
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@irq UART = {USART1 => embassy_stm32::usart::InterruptHandler<embassy_stm32::peripherals::USART1>;},
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);
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#[cfg(feature = "stm32g071rb")]
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define_peris!(
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UART = USART1, UART_TX = PC4, UART_RX = PC5, UART_TX_DMA = DMA1_CH1, UART_RX_DMA = DMA1_CH2,
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SPI = SPI1, SPI_SCK = PA5, SPI_MOSI = PA7, SPI_MISO = PA6, SPI_TX_DMA = DMA1_CH1, SPI_RX_DMA = DMA1_CH2,
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@irq UART = {USART1 => embassy_stm32::usart::InterruptHandler<embassy_stm32::peripherals::USART1>;},
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);
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#[cfg(feature = "stm32f429zi")]
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define_peris!(
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UART = USART6, UART_TX = PG14, UART_RX = PG9, UART_TX_DMA = DMA2_CH6, UART_RX_DMA = DMA2_CH1,
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SPI = SPI1, SPI_SCK = PA5, SPI_MOSI = PA7, SPI_MISO = PA6, SPI_TX_DMA = DMA2_CH3, SPI_RX_DMA = DMA2_CH2,
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@irq UART = {USART6 => embassy_stm32::usart::InterruptHandler<embassy_stm32::peripherals::USART6>;},
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);
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#[cfg(feature = "stm32wb55rg")]
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define_peris!(
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UART = LPUART1, UART_TX = PA2, UART_RX = PA3, UART_TX_DMA = DMA1_CH1, UART_RX_DMA = DMA1_CH2,
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SPI = SPI1, SPI_SCK = PA5, SPI_MOSI = PA7, SPI_MISO = PA6, SPI_TX_DMA = DMA1_CH1, SPI_RX_DMA = DMA1_CH2,
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@irq UART = {LPUART1 => embassy_stm32::usart::InterruptHandler<embassy_stm32::peripherals::LPUART1>;},
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);
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#[cfg(feature = "stm32h755zi")]
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define_peris!(
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UART = USART1, UART_TX = PB6, UART_RX = PB7, UART_TX_DMA = DMA1_CH0, UART_RX_DMA = DMA1_CH1,
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SPI = SPI1, SPI_SCK = PA5, SPI_MOSI = PB5, SPI_MISO = PA6, SPI_TX_DMA = DMA1_CH0, SPI_RX_DMA = DMA1_CH1,
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@irq UART = {USART1 => embassy_stm32::usart::InterruptHandler<embassy_stm32::peripherals::USART1>;},
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);
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#[cfg(feature = "stm32u585ai")]
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define_peris!(
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UART = USART3, UART_TX = PD8, UART_RX = PD9, UART_TX_DMA = GPDMA1_CH0, UART_RX_DMA = GPDMA1_CH1,
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SPI = SPI1, SPI_SCK = PE13, SPI_MOSI = PE15, SPI_MISO = PE14, SPI_TX_DMA = GPDMA1_CH0, SPI_RX_DMA = GPDMA1_CH1,
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@irq UART = {USART3 => embassy_stm32::usart::InterruptHandler<embassy_stm32::peripherals::USART3>;},
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);
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#[cfg(feature = "stm32h563zi")]
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define_peris!(
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UART = LPUART1, UART_TX = PB6, UART_RX = PB7, UART_TX_DMA = GPDMA1_CH0, UART_RX_DMA = GPDMA1_CH1,
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SPI = SPI4, SPI_SCK = PE12, SPI_MOSI = PE14, SPI_MISO = PE13, SPI_TX_DMA = GPDMA1_CH0, SPI_RX_DMA = GPDMA1_CH1,
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@irq UART = {LPUART1 => embassy_stm32::usart::InterruptHandler<embassy_stm32::peripherals::LPUART1>;},
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);
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#[cfg(feature = "stm32c031c6")]
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define_peris!(
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UART = USART1, UART_TX = PB6, UART_RX = PB7, UART_TX_DMA = DMA1_CH1, UART_RX_DMA = DMA1_CH2,
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SPI = SPI1, SPI_SCK = PA5, SPI_MOSI = PA7, SPI_MISO = PA6, SPI_TX_DMA = DMA1_CH1, SPI_RX_DMA = DMA1_CH2,
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@irq UART = {USART1 => embassy_stm32::usart::InterruptHandler<embassy_stm32::peripherals::USART1>;},
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);
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2023-05-30 00:10:36 +02:00
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pub fn config() -> Config {
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#[allow(unused_mut)]
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let mut config = Config::default();
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#[cfg(feature = "stm32h755zi")]
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{
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2023-09-19 04:22:57 +02:00
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use embassy_stm32::rcc::*;
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config.rcc.hsi = Some(Hsi::Mhz64);
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config.rcc.csi = true;
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config.rcc.pll_src = PllSource::Hsi;
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config.rcc.pll1 = Some(Pll {
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prediv: 4,
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mul: 50,
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divp: Some(2),
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divq: Some(8), // SPI1 cksel defaults to pll1_q
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divr: None,
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});
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config.rcc.pll2 = Some(Pll {
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prediv: 4,
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mul: 50,
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divp: Some(8), // 100mhz
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divq: None,
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divr: None,
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});
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config.rcc.sys = Sysclk::Pll1P; // 400 Mhz
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config.rcc.ahb_pre = AHBPrescaler::DIV2; // 200 Mhz
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config.rcc.apb1_pre = APBPrescaler::DIV2; // 100 Mhz
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config.rcc.apb2_pre = APBPrescaler::DIV2; // 100 Mhz
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config.rcc.apb3_pre = APBPrescaler::DIV2; // 100 Mhz
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config.rcc.apb4_pre = APBPrescaler::DIV2; // 100 Mhz
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config.rcc.voltage_scale = VoltageScale::Scale1;
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config.rcc.adc_clock_source = AdcClockSource::PLL2_P;
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2023-05-30 00:10:36 +02:00
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}
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#[cfg(feature = "stm32u585ai")]
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{
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config.rcc.mux = embassy_stm32::rcc::ClockSrc::MSI(embassy_stm32::rcc::MSIRange::Range48mhz);
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}
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config
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}
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