2021-12-07 05:14:27 +01:00
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#![no_std]
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#![no_main]
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2023-05-30 00:10:36 +02:00
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#[path = "../common.rs"]
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mod common;
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2021-12-07 05:14:27 +01:00
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2023-05-30 00:10:36 +02:00
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use common::*;
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2021-12-07 05:14:27 +01:00
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use defmt::assert_eq;
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2022-08-17 23:40:16 +02:00
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use embassy_executor::Spawner;
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2021-12-07 05:14:27 +01:00
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use embassy_stm32::spi::{self, Spi};
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2023-07-31 00:02:50 +02:00
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use embassy_stm32::time::Hertz;
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2021-12-07 05:14:27 +01:00
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2022-08-17 18:49:55 +02:00
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#[embassy_executor::main]
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async fn main(_spawner: Spawner) {
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let p = embassy_stm32::init(config());
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2021-12-07 05:14:27 +01:00
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info!("Hello World!");
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2023-09-25 22:34:18 +02:00
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let spi = peri!(p, SPI);
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let sck = peri!(p, SPI_SCK);
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let mosi = peri!(p, SPI_MOSI);
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let miso = peri!(p, SPI_MISO);
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let tx_dma = peri!(p, SPI_TX_DMA);
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let rx_dma = peri!(p, SPI_RX_DMA);
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2021-12-07 05:14:27 +01:00
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2023-07-31 00:02:50 +02:00
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let mut spi_config = spi::Config::default();
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spi_config.frequency = Hertz(1_000_000);
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2021-12-07 05:14:27 +01:00
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let mut spi = Spi::new(
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2023-07-31 00:02:50 +02:00
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spi, sck, // Arduino D13
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2021-12-07 05:14:27 +01:00
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mosi, // Arduino D11
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miso, // Arduino D12
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2023-07-31 00:02:50 +02:00
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tx_dma, rx_dma, spi_config,
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2021-12-07 05:14:27 +01:00
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);
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let data: [u8; 9] = [0x00, 0xFF, 0xAA, 0x55, 0xC0, 0xFF, 0xEE, 0xC0, 0xDE];
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// Arduino pins D11 and D12 (MOSI-MISO) are connected together with a 1K resistor.
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// so we should get the data we sent back.
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let mut buf = [0; 9];
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2022-01-26 22:39:06 +01:00
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spi.transfer(&mut buf, &data).await.unwrap();
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2021-12-07 05:14:27 +01:00
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assert_eq!(buf, data);
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2022-03-15 00:31:36 +01:00
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spi.transfer_in_place(&mut buf).await.unwrap();
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assert_eq!(buf, data);
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2022-03-15 00:46:18 +01:00
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// Check read/write don't hang. We can't check they transfer the right data
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// without fancier test mechanisms.
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spi.write(&buf).await.unwrap();
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spi.read(&mut buf).await.unwrap();
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spi.write(&buf).await.unwrap();
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spi.read(&mut buf).await.unwrap();
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spi.write(&buf).await.unwrap();
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// Check transfer doesn't break after having done a write, due to garbage in the FIFO
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spi.transfer(&mut buf, &data).await.unwrap();
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assert_eq!(buf, data);
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2022-03-15 00:48:11 +01:00
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// Check zero-length operations, these should be noops.
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spi.transfer::<u8>(&mut [], &[]).await.unwrap();
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spi.transfer_in_place::<u8>(&mut []).await.unwrap();
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spi.read::<u8>(&mut []).await.unwrap();
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spi.write::<u8>(&[]).await.unwrap();
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2022-03-15 04:13:33 +01:00
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// === Check mixing blocking with async.
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spi.blocking_transfer(&mut buf, &data).unwrap();
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assert_eq!(buf, data);
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spi.transfer(&mut buf, &data).await.unwrap();
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assert_eq!(buf, data);
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spi.blocking_write(&buf).unwrap();
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spi.transfer(&mut buf, &data).await.unwrap();
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assert_eq!(buf, data);
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spi.blocking_read(&mut buf).unwrap();
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spi.blocking_write(&buf).unwrap();
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spi.write(&buf).await.unwrap();
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spi.read(&mut buf).await.unwrap();
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spi.blocking_write(&buf).unwrap();
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spi.blocking_read(&mut buf).unwrap();
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spi.write(&buf).await.unwrap();
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2021-12-07 05:14:27 +01:00
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info!("Test OK");
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cortex_m::asm::bkpt();
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}
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