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stm32/spi: more exhaustive test.

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This commit is contained in:
Dario Nieuwenhuis 2022-03-15 00:46:18 +01:00
parent 306110f56e
commit 06f35c2517
2 changed files with 27 additions and 0 deletions
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15
tests/stm32/src/bin/spi.rs
View File

@ -37,9 +37,24 @@ async fn main(_spawner: Spawner, p: Peripherals) {
// Arduino pins D11 and D12 (MOSI-MISO) are connected together with a 1K resistor.
// so we should get the data we sent back.
let mut buf = data;
spi.blocking_transfer(&mut buf, &data).unwrap();
assert_eq!(buf, data);
spi.blocking_transfer_in_place(&mut buf).unwrap();
assert_eq!(buf, data);
// Check read/write don't hang. We can't check they transfer the right data
// without fancier test mechanisms.
spi.blocking_write(&buf).unwrap();
spi.blocking_read(&mut buf).unwrap();
spi.blocking_write(&buf).unwrap();
spi.blocking_read(&mut buf).unwrap();
spi.blocking_write(&buf).unwrap();
// Check transfer doesn't break after having done a write, due to garbage in the FIFO
spi.blocking_transfer(&mut buf, &data).unwrap();
assert_eq!(buf, data);
info!("Test OK");
cortex_m::asm::bkpt();
}

12
tests/stm32/src/bin/spi_dma.rs
View File

@ -50,6 +50,18 @@ async fn main(_spawner: Spawner, p: Peripherals) {
spi.transfer_in_place(&mut buf).await.unwrap();
assert_eq!(buf, data);
// Check read/write don't hang. We can't check they transfer the right data
// without fancier test mechanisms.
spi.write(&buf).await.unwrap();
spi.read(&mut buf).await.unwrap();
spi.write(&buf).await.unwrap();
spi.read(&mut buf).await.unwrap();
spi.write(&buf).await.unwrap();
// Check transfer doesn't break after having done a write, due to garbage in the FIFO
spi.transfer(&mut buf, &data).await.unwrap();
assert_eq!(buf, data);
info!("Test OK");
cortex_m::asm::bkpt();
}