2023-10-11 03:53:27 +02:00
|
|
|
use core::sync::atomic::{compiler_fence, Ordering};
|
|
|
|
|
|
|
|
use crate::pac::common::{Reg, RW};
|
|
|
|
pub use crate::pac::rcc::vals::Rtcsel as RtcClockSource;
|
|
|
|
use crate::time::Hertz;
|
|
|
|
|
|
|
|
#[cfg(any(stm32f0, stm32f1, stm32f3))]
|
|
|
|
pub const LSI_FREQ: Hertz = Hertz(40_000);
|
|
|
|
#[cfg(not(any(stm32f0, stm32f1, stm32f3)))]
|
|
|
|
pub const LSI_FREQ: Hertz = Hertz(32_000);
|
|
|
|
|
2023-10-03 23:45:05 +02:00
|
|
|
#[allow(dead_code)]
|
|
|
|
#[derive(Clone, Copy)]
|
2023-10-11 03:53:27 +02:00
|
|
|
pub enum LseMode {
|
2023-10-03 23:45:05 +02:00
|
|
|
Oscillator(LseDrive),
|
|
|
|
Bypass,
|
|
|
|
}
|
|
|
|
|
2023-10-11 03:53:27 +02:00
|
|
|
pub struct LseConfig {
|
|
|
|
pub frequency: Hertz,
|
|
|
|
pub mode: LseMode,
|
2023-10-03 23:45:05 +02:00
|
|
|
}
|
|
|
|
|
2023-09-07 00:33:56 +02:00
|
|
|
#[allow(dead_code)]
|
2023-09-18 01:41:45 +02:00
|
|
|
#[derive(Default, Clone, Copy)]
|
2023-09-07 00:33:56 +02:00
|
|
|
pub enum LseDrive {
|
|
|
|
Low = 0,
|
|
|
|
MediumLow = 0x01,
|
|
|
|
#[default]
|
|
|
|
MediumHigh = 0x02,
|
|
|
|
High = 0x03,
|
|
|
|
}
|
|
|
|
|
2023-10-03 23:45:05 +02:00
|
|
|
// All families but these have the LSEDRV register
|
|
|
|
#[cfg(not(any(rcc_f1, rcc_f1cl, rcc_f100, rcc_f2, rcc_f4, rcc_f400, rcc_f410, rcc_l1)))]
|
2023-09-07 00:33:56 +02:00
|
|
|
impl From<LseDrive> for crate::pac::rcc::vals::Lsedrv {
|
|
|
|
fn from(value: LseDrive) -> Self {
|
|
|
|
use crate::pac::rcc::vals::Lsedrv;
|
|
|
|
|
|
|
|
match value {
|
|
|
|
LseDrive::Low => Lsedrv::LOW,
|
|
|
|
LseDrive::MediumLow => Lsedrv::MEDIUMLOW,
|
|
|
|
LseDrive::MediumHigh => Lsedrv::MEDIUMHIGH,
|
|
|
|
LseDrive::High => Lsedrv::HIGH,
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2023-08-27 22:18:34 +02:00
|
|
|
#[cfg(not(any(rtc_v2l0, rtc_v2l1, stm32c0)))]
|
2023-08-27 22:01:09 +02:00
|
|
|
type Bdcr = crate::pac::rcc::regs::Bdcr;
|
|
|
|
#[cfg(any(rtc_v2l0, rtc_v2l1))]
|
|
|
|
type Bdcr = crate::pac::rcc::regs::Csr;
|
2023-10-11 03:53:27 +02:00
|
|
|
#[cfg(any(stm32c0))]
|
|
|
|
type Bdcr = crate::pac::rcc::regs::Csr1;
|
|
|
|
|
|
|
|
#[cfg(any(stm32c0))]
|
|
|
|
fn unlock() {}
|
|
|
|
|
|
|
|
#[cfg(not(any(stm32c0)))]
|
|
|
|
fn unlock() {
|
|
|
|
#[cfg(any(stm32f0, stm32f1, stm32f2, stm32f3, stm32l0, stm32l1))]
|
|
|
|
let cr = crate::pac::PWR.cr();
|
|
|
|
#[cfg(not(any(stm32f0, stm32f1, stm32f2, stm32f3, stm32l0, stm32l1, stm32u5, stm32h5, stm32wba)))]
|
|
|
|
let cr = crate::pac::PWR.cr1();
|
|
|
|
#[cfg(any(stm32u5, stm32h5, stm32wba))]
|
|
|
|
let cr = crate::pac::PWR.dbpcr();
|
|
|
|
|
|
|
|
cr.modify(|w| w.set_dbp(true));
|
|
|
|
while !cr.read().dbp() {}
|
|
|
|
}
|
2023-08-27 22:01:09 +02:00
|
|
|
|
2023-10-11 03:53:27 +02:00
|
|
|
fn bdcr() -> Reg<Bdcr, RW> {
|
|
|
|
#[cfg(any(rtc_v2l0, rtc_v2l1))]
|
|
|
|
return crate::pac::RCC.csr();
|
|
|
|
#[cfg(not(any(rtc_v2l0, rtc_v2l1, stm32c0)))]
|
|
|
|
return crate::pac::RCC.bdcr();
|
|
|
|
#[cfg(any(stm32c0))]
|
|
|
|
return crate::pac::RCC.csr1();
|
|
|
|
}
|
2023-08-27 16:07:34 +02:00
|
|
|
|
2023-10-11 03:53:27 +02:00
|
|
|
pub struct LsConfig {
|
|
|
|
pub rtc: RtcClockSource,
|
|
|
|
pub lsi: bool,
|
|
|
|
pub lse: Option<LseConfig>,
|
|
|
|
}
|
2023-08-27 22:18:34 +02:00
|
|
|
|
2023-10-11 03:53:27 +02:00
|
|
|
impl LsConfig {
|
|
|
|
pub const fn default_lse() -> Self {
|
|
|
|
Self {
|
|
|
|
rtc: RtcClockSource::LSE,
|
|
|
|
lse: Some(LseConfig {
|
2023-10-11 13:39:04 +02:00
|
|
|
frequency: Hertz(32_768),
|
2023-10-11 03:53:27 +02:00
|
|
|
mode: LseMode::Oscillator(LseDrive::MediumHigh),
|
|
|
|
}),
|
|
|
|
lsi: false,
|
|
|
|
}
|
|
|
|
}
|
2023-08-27 22:18:34 +02:00
|
|
|
|
2023-10-11 03:53:27 +02:00
|
|
|
pub const fn default_lsi() -> Self {
|
|
|
|
Self {
|
|
|
|
rtc: RtcClockSource::LSI,
|
|
|
|
lsi: true,
|
|
|
|
lse: None,
|
|
|
|
}
|
2023-08-27 16:07:34 +02:00
|
|
|
}
|
|
|
|
|
2023-10-11 03:53:27 +02:00
|
|
|
pub const fn off() -> Self {
|
|
|
|
Self {
|
2023-10-16 02:51:35 +02:00
|
|
|
rtc: RtcClockSource::DISABLE,
|
2023-10-11 03:53:27 +02:00
|
|
|
lsi: false,
|
|
|
|
lse: None,
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
2023-08-27 16:07:34 +02:00
|
|
|
|
2023-10-11 03:53:27 +02:00
|
|
|
impl Default for LsConfig {
|
|
|
|
fn default() -> Self {
|
|
|
|
// on L5, just the fact that LSI is enabled makes things crash.
|
|
|
|
// TODO: investigate.
|
2023-08-27 16:07:34 +02:00
|
|
|
|
2023-10-11 03:53:27 +02:00
|
|
|
#[cfg(not(stm32l5))]
|
|
|
|
return Self::default_lsi();
|
|
|
|
#[cfg(stm32l5)]
|
|
|
|
return Self::off();
|
2023-08-27 16:07:34 +02:00
|
|
|
}
|
2023-10-11 03:53:27 +02:00
|
|
|
}
|
2023-08-27 16:07:34 +02:00
|
|
|
|
2023-10-11 03:53:27 +02:00
|
|
|
impl LsConfig {
|
|
|
|
pub(crate) fn init(&self) -> Option<Hertz> {
|
|
|
|
let rtc_clk = match self.rtc {
|
|
|
|
RtcClockSource::LSI => {
|
|
|
|
assert!(self.lsi);
|
|
|
|
Some(LSI_FREQ)
|
|
|
|
}
|
|
|
|
RtcClockSource::LSE => Some(self.lse.as_ref().unwrap().frequency),
|
2023-10-16 02:51:35 +02:00
|
|
|
RtcClockSource::DISABLE => None,
|
2023-10-11 03:53:27 +02:00
|
|
|
_ => todo!(),
|
2023-10-02 22:03:18 +02:00
|
|
|
};
|
2023-10-11 03:53:27 +02:00
|
|
|
|
|
|
|
let (lse_en, lse_byp, lse_drv) = match &self.lse {
|
|
|
|
Some(c) => match c.mode {
|
|
|
|
LseMode::Oscillator(lse_drv) => (true, false, Some(lse_drv)),
|
|
|
|
LseMode::Bypass => (true, true, None),
|
|
|
|
},
|
2023-10-03 23:45:05 +02:00
|
|
|
None => (false, false, None),
|
|
|
|
};
|
2023-10-11 03:53:27 +02:00
|
|
|
_ = lse_drv; // not all chips have it.
|
2023-10-02 22:03:18 +02:00
|
|
|
|
2023-10-11 03:53:27 +02:00
|
|
|
// Disable backup domain write protection
|
|
|
|
unlock();
|
2023-09-09 01:20:58 +02:00
|
|
|
|
2023-10-11 03:53:27 +02:00
|
|
|
if self.lsi {
|
|
|
|
#[cfg(any(stm32u5, stm32h5, stm32wba))]
|
|
|
|
let csr = crate::pac::RCC.bdcr();
|
|
|
|
#[cfg(not(any(stm32u5, stm32h5, stm32wba, stm32c0)))]
|
2023-09-18 01:41:45 +02:00
|
|
|
let csr = crate::pac::RCC.csr();
|
2023-10-11 03:53:27 +02:00
|
|
|
#[cfg(any(stm32c0))]
|
|
|
|
let csr = crate::pac::RCC.csr2();
|
2023-09-09 01:20:58 +02:00
|
|
|
|
2023-09-25 01:37:09 +02:00
|
|
|
#[cfg(not(any(rcc_wb, rcc_wba)))]
|
|
|
|
csr.modify(|w| w.set_lsion(true));
|
|
|
|
|
|
|
|
#[cfg(any(rcc_wb, rcc_wba))]
|
|
|
|
csr.modify(|w| w.set_lsi1on(true));
|
2023-09-18 01:41:45 +02:00
|
|
|
|
|
|
|
#[cfg(not(any(rcc_wb, rcc_wba)))]
|
|
|
|
while !csr.read().lsirdy() {}
|
|
|
|
|
|
|
|
#[cfg(any(rcc_wb, rcc_wba))]
|
|
|
|
while !csr.read().lsi1rdy() {}
|
|
|
|
}
|
|
|
|
|
2023-10-02 22:03:18 +02:00
|
|
|
// backup domain configuration (LSEON, RTCEN, RTCSEL) is kept across resets.
|
|
|
|
// once set, changing it requires a backup domain reset.
|
|
|
|
// first check if the configuration matches what we want.
|
|
|
|
|
|
|
|
// check if it's already enabled and in the source we want.
|
2023-10-11 03:53:27 +02:00
|
|
|
let reg = bdcr().read();
|
2023-10-02 22:03:18 +02:00
|
|
|
let mut ok = true;
|
2023-10-11 03:53:27 +02:00
|
|
|
ok &= reg.rtcsel() == self.rtc;
|
2023-10-02 22:03:18 +02:00
|
|
|
#[cfg(not(rcc_wba))]
|
|
|
|
{
|
2023-10-16 02:51:35 +02:00
|
|
|
ok &= reg.rtcen() == (self.rtc != RtcClockSource::DISABLE);
|
2023-10-02 22:03:18 +02:00
|
|
|
}
|
2023-10-03 23:45:05 +02:00
|
|
|
ok &= reg.lseon() == lse_en;
|
|
|
|
ok &= reg.lsebyp() == lse_byp;
|
|
|
|
#[cfg(not(any(rcc_f1, rcc_f1cl, rcc_f100, rcc_f2, rcc_f4, rcc_f400, rcc_f410, rcc_l1)))]
|
|
|
|
if let Some(lse_drv) = lse_drv {
|
|
|
|
ok &= reg.lsedrv() == lse_drv.into();
|
2023-10-02 22:03:18 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
// if configuration is OK, we're done.
|
|
|
|
if ok {
|
2023-10-11 03:53:27 +02:00
|
|
|
trace!("BDCR ok: {:08x}", bdcr().read().0);
|
|
|
|
return rtc_clk;
|
2023-10-02 22:03:18 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
// If not OK, reset backup domain and configure it.
|
2023-10-11 03:53:27 +02:00
|
|
|
#[cfg(not(any(rcc_l0, rcc_l0_v2, rcc_l1, stm32h5, stm32c0)))]
|
|
|
|
{
|
|
|
|
bdcr().modify(|w| w.set_bdrst(true));
|
|
|
|
bdcr().modify(|w| w.set_bdrst(false));
|
|
|
|
}
|
|
|
|
#[cfg(any(stm32h5))]
|
|
|
|
{
|
|
|
|
bdcr().modify(|w| w.set_vswrst(true));
|
|
|
|
bdcr().modify(|w| w.set_vswrst(false));
|
|
|
|
}
|
|
|
|
#[cfg(any(stm32c0))]
|
2023-10-02 22:03:18 +02:00
|
|
|
{
|
2023-10-11 03:53:27 +02:00
|
|
|
bdcr().modify(|w| w.set_rtcrst(true));
|
|
|
|
bdcr().modify(|w| w.set_rtcrst(false));
|
2023-10-02 22:03:18 +02:00
|
|
|
}
|
|
|
|
|
2023-10-03 23:45:05 +02:00
|
|
|
if lse_en {
|
2023-10-11 03:53:27 +02:00
|
|
|
bdcr().modify(|w| {
|
2023-10-03 23:45:05 +02:00
|
|
|
#[cfg(not(any(rcc_f1, rcc_f1cl, rcc_f100, rcc_f2, rcc_f4, rcc_f400, rcc_f410, rcc_l1)))]
|
|
|
|
if let Some(lse_drv) = lse_drv {
|
|
|
|
w.set_lsedrv(lse_drv.into());
|
|
|
|
}
|
|
|
|
w.set_lsebyp(lse_byp);
|
2023-09-18 01:41:45 +02:00
|
|
|
w.set_lseon(true);
|
|
|
|
});
|
|
|
|
|
2023-10-11 03:53:27 +02:00
|
|
|
while !bdcr().read().lserdy() {}
|
2023-09-18 01:41:45 +02:00
|
|
|
}
|
|
|
|
|
2023-10-16 02:51:35 +02:00
|
|
|
if self.rtc != RtcClockSource::DISABLE {
|
2023-10-11 03:53:27 +02:00
|
|
|
bdcr().modify(|w| {
|
2023-10-02 22:03:18 +02:00
|
|
|
#[cfg(any(rtc_v2h7, rtc_v2l4, rtc_v2wb, rtc_v3, rtc_v3u5))]
|
|
|
|
assert!(!w.lsecsson(), "RTC is not compatible with LSE CSS, yet.");
|
|
|
|
|
2023-09-16 03:44:01 +02:00
|
|
|
#[cfg(not(rcc_wba))]
|
2023-10-02 22:03:18 +02:00
|
|
|
w.set_rtcen(true);
|
2023-10-11 03:53:27 +02:00
|
|
|
w.set_rtcsel(self.rtc);
|
2023-09-16 03:44:01 +02:00
|
|
|
});
|
2023-08-27 16:07:34 +02:00
|
|
|
}
|
2023-10-02 22:03:18 +02:00
|
|
|
|
2023-10-11 03:53:27 +02:00
|
|
|
trace!("BDCR configured: {:08x}", bdcr().read().0);
|
2023-10-03 22:53:22 +02:00
|
|
|
|
|
|
|
compiler_fence(Ordering::SeqCst);
|
2023-10-11 03:53:27 +02:00
|
|
|
|
|
|
|
rtc_clk
|
2023-08-27 16:07:34 +02:00
|
|
|
}
|
|
|
|
}
|