2021-12-08 17:39:59 +01:00
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#![no_std]
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#![no_main]
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#![feature(type_alias_impl_trait)]
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2022-04-02 04:35:06 +02:00
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use defmt::*;
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2022-08-17 23:40:16 +02:00
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use embassy_executor::Spawner;
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2022-02-10 21:38:03 +01:00
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use embassy_stm32::gpio::low_level::AFType;
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use embassy_stm32::gpio::Speed;
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2023-09-19 04:22:57 +02:00
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use embassy_stm32::time::{khz, Hertz};
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2023-07-28 15:29:27 +02:00
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use embassy_stm32::timer::*;
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2022-08-17 18:49:55 +02:00
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use embassy_stm32::{into_ref, Config, Peripheral, PeripheralRef};
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2022-08-17 23:40:16 +02:00
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use embassy_time::{Duration, Timer};
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2022-06-12 22:15:44 +02:00
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use {defmt_rtt as _, panic_probe as _};
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2021-12-08 17:39:59 +01:00
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2022-08-17 22:25:58 +02:00
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#[embassy_executor::main]
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async fn main(_spawner: Spawner) {
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2021-12-08 17:39:59 +01:00
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let mut config = Config::default();
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2023-09-19 04:22:57 +02:00
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{
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use embassy_stm32::rcc::*;
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config.rcc.hsi = Some(Hsi::Mhz64);
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config.rcc.csi = true;
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config.rcc.hsi48 = true; // needed for RNG
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config.rcc.pll_src = PllSource::Hsi;
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config.rcc.pll1 = Some(Pll {
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2023-10-09 02:48:22 +02:00
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prediv: PllPreDiv::DIV4,
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mul: PllMul::MUL50,
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divp: Some(PllDiv::DIV2),
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divq: Some(PllDiv::DIV8), // 100mhz
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2023-09-19 04:22:57 +02:00
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divr: None,
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});
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config.rcc.sys = Sysclk::Pll1P; // 400 Mhz
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config.rcc.ahb_pre = AHBPrescaler::DIV2; // 200 Mhz
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config.rcc.apb1_pre = APBPrescaler::DIV2; // 100 Mhz
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config.rcc.apb2_pre = APBPrescaler::DIV2; // 100 Mhz
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config.rcc.apb3_pre = APBPrescaler::DIV2; // 100 Mhz
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config.rcc.apb4_pre = APBPrescaler::DIV2; // 100 Mhz
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config.rcc.voltage_scale = VoltageScale::Scale1;
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}
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2022-08-17 22:25:58 +02:00
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let p = embassy_stm32::init(config);
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2021-12-08 17:39:59 +01:00
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info!("Hello World!");
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2022-07-11 00:36:10 +02:00
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let mut pwm = SimplePwm32::new(p.TIM5, p.PA0, p.PA1, p.PA2, p.PA3, khz(10));
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2021-12-08 17:39:59 +01:00
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let max = pwm.get_max_duty();
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pwm.enable(Channel::Ch1);
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info!("PWM initialized");
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info!("PWM max duty {}", max);
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loop {
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pwm.set_duty(Channel::Ch1, 0);
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Timer::after(Duration::from_millis(300)).await;
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pwm.set_duty(Channel::Ch1, max / 4);
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Timer::after(Duration::from_millis(300)).await;
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pwm.set_duty(Channel::Ch1, max / 2);
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Timer::after(Duration::from_millis(300)).await;
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pwm.set_duty(Channel::Ch1, max - 1);
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Timer::after(Duration::from_millis(300)).await;
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}
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}
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2022-02-10 21:38:03 +01:00
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pub struct SimplePwm32<'d, T: CaptureCompare32bitInstance> {
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2022-07-23 14:00:19 +02:00
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inner: PeripheralRef<'d, T>,
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2021-12-08 17:39:59 +01:00
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}
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2022-02-10 21:38:03 +01:00
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impl<'d, T: CaptureCompare32bitInstance> SimplePwm32<'d, T> {
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2022-07-11 00:36:10 +02:00
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pub fn new(
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2022-07-23 14:00:19 +02:00
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tim: impl Peripheral<P = T> + 'd,
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ch1: impl Peripheral<P = impl Channel1Pin<T>> + 'd,
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ch2: impl Peripheral<P = impl Channel2Pin<T>> + 'd,
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ch3: impl Peripheral<P = impl Channel3Pin<T>> + 'd,
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ch4: impl Peripheral<P = impl Channel4Pin<T>> + 'd,
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2022-07-11 00:36:10 +02:00
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freq: Hertz,
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2021-12-08 17:39:59 +01:00
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) -> Self {
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2022-07-23 14:00:19 +02:00
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into_ref!(tim, ch1, ch2, ch3, ch4);
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2021-12-08 17:39:59 +01:00
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2023-10-11 21:38:41 +02:00
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T::enable_and_reset();
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2021-12-08 17:39:59 +01:00
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2023-06-19 03:07:26 +02:00
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ch1.set_speed(Speed::VeryHigh);
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ch1.set_as_af(ch1.af_num(), AFType::OutputPushPull);
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ch2.set_speed(Speed::VeryHigh);
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ch2.set_as_af(ch1.af_num(), AFType::OutputPushPull);
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ch3.set_speed(Speed::VeryHigh);
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ch3.set_as_af(ch1.af_num(), AFType::OutputPushPull);
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ch4.set_speed(Speed::VeryHigh);
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ch4.set_as_af(ch1.af_num(), AFType::OutputPushPull);
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2021-12-08 17:39:59 +01:00
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2022-07-23 01:29:35 +02:00
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let mut this = Self { inner: tim };
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2021-12-08 17:39:59 +01:00
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this.set_freq(freq);
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this.inner.start();
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2023-06-19 03:07:26 +02:00
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let r = T::regs_gp32();
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r.ccmr_output(0)
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.modify(|w| w.set_ocm(0, OutputCompareMode::PwmMode1.into()));
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r.ccmr_output(0)
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.modify(|w| w.set_ocm(1, OutputCompareMode::PwmMode1.into()));
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r.ccmr_output(1)
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.modify(|w| w.set_ocm(0, OutputCompareMode::PwmMode1.into()));
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r.ccmr_output(1)
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.modify(|w| w.set_ocm(1, OutputCompareMode::PwmMode1.into()));
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2021-12-08 17:39:59 +01:00
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this
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}
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pub fn enable(&mut self, channel: Channel) {
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2023-06-19 03:07:26 +02:00
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T::regs_gp32().ccer().modify(|w| w.set_cce(channel.raw(), true));
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2021-12-08 17:39:59 +01:00
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}
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pub fn disable(&mut self, channel: Channel) {
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2023-06-19 03:07:26 +02:00
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T::regs_gp32().ccer().modify(|w| w.set_cce(channel.raw(), false));
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2021-12-08 17:39:59 +01:00
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}
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2022-07-11 00:36:10 +02:00
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pub fn set_freq(&mut self, freq: Hertz) {
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2022-06-12 22:15:44 +02:00
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<T as embassy_stm32::timer::low_level::GeneralPurpose32bitInstance>::set_frequency(&mut self.inner, freq);
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2021-12-08 17:39:59 +01:00
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}
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pub fn get_max_duty(&self) -> u32 {
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2023-06-19 03:07:26 +02:00
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T::regs_gp32().arr().read().arr()
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2021-12-08 17:39:59 +01:00
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}
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pub fn set_duty(&mut self, channel: Channel, duty: u32) {
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defmt::assert!(duty < self.get_max_duty());
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2023-06-19 03:07:26 +02:00
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T::regs_gp32().ccr(channel.raw()).modify(|w| w.set_ccr(duty))
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2021-12-08 17:39:59 +01:00
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}
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}
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