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enable clock first

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This commit is contained in:
pbert 2023-10-11 21:38:41 +02:00
parent d7d79f3068
commit ecdd7c0e2f
38 changed files with 61 additions and 61 deletions
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4
embassy-stm32/build.rs
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@ -556,14 +556,14 @@ fn main() {
fn frequency() -> crate::time::Hertz {
#clock_frequency
}
fn enable() {
fn enable_and_reset() {
critical_section::with(|_cs| {
#before_enable
#rst
#[cfg(feature = "low-power")]
crate::rcc::clock_refcount_add(_cs);
crate::pac::RCC.#en_reg().modify(|w| w.#set_en_field(true));
#after_enable
#rst
})
}
fn disable() {

2
embassy-stm32/src/adc/f1.rs
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@ -51,7 +51,7 @@ impl<T: Instance> super::sealed::AdcPin<T> for Temperature {
impl<'d, T: Instance> Adc<'d, T> {
pub fn new(adc: impl Peripheral<P = T> + 'd, delay: &mut impl DelayUs<u32>) -> Self {
into_ref!(adc);
T::reset_and_enable();
T::enable_and_reset();
T::regs().cr2().modify(|reg| reg.set_adon(true));
// 11.4: Before starting a calibration, the ADC must have been in power-on state (ADON bit = ‘1’)

2
embassy-stm32/src/adc/f3.rs
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@ -64,7 +64,7 @@ impl<'d, T: Instance> Adc<'d, T> {
into_ref!(adc);
T::reset_and_enable();
T::enable_and_reset();
// Enable the adc regulator
T::regs().cr().modify(|w| w.set_advregen(vals::Advregen::INTERMEDIATE));

2
embassy-stm32/src/adc/v1.rs
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@ -61,7 +61,7 @@ impl<'d, T: Instance> Adc<'d, T> {
delay: &mut impl DelayUs<u32>,
) -> Self {
into_ref!(adc);
T::reset_and_enable();
T::enable_and_reset();
// Delay 1μs when using HSI14 as the ADC clock.
//

2
embassy-stm32/src/adc/v2.rs
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@ -95,7 +95,7 @@ where
{
pub fn new(adc: impl Peripheral<P = T> + 'd, delay: &mut impl DelayUs<u32>) -> Self {
into_ref!(adc);
T::reset_and_enable();
T::enable_and_reset();
let presc = Prescaler::from_pclk2(T::frequency());
T::common_regs().ccr().modify(|w| w.set_adcpre(presc.adcpre()));

2
embassy-stm32/src/adc/v3.rs
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@ -48,7 +48,7 @@ impl<T: Instance> super::sealed::AdcPin<T> for Vbat {
impl<'d, T: Instance> Adc<'d, T> {
pub fn new(adc: impl Peripheral<P = T> + 'd, delay: &mut impl DelayUs<u32>) -> Self {
into_ref!(adc);
T::reset_and_enable();
T::enable_and_reset();
T::regs().cr().modify(|reg| {
#[cfg(not(adc_g0))]
reg.set_deeppwd(false);

2
embassy-stm32/src/adc/v4.rs
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@ -127,7 +127,7 @@ impl Prescaler {
impl<'d, T: Instance> Adc<'d, T> {
pub fn new(adc: impl Peripheral<P = T> + 'd, delay: &mut impl DelayUs<u16>) -> Self {
embassy_hal_internal::into_ref!(adc);
T::reset_and_enable();
T::enable_and_reset();
let prescaler = Prescaler::from_ker_ck(T::frequency());

2
embassy-stm32/src/can/bxcan.rs
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@ -136,7 +136,7 @@ impl<'d, T: Instance> Can<'d, T> {
rx.set_as_af(rx.af_num(), AFType::Input);
tx.set_as_af(tx.af_num(), AFType::OutputPushPull);
T::reset_and_enable();
T::enable_and_reset();
{
use crate::pac::can::vals::{Errie, Fmpie, Tmeie};

2
embassy-stm32/src/crc/v1.rs
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@ -16,7 +16,7 @@ impl<'d> Crc<'d> {
// Note: enable and reset come from RccPeripheral.
// enable CRC clock in RCC.
CRC::reset_and_enable();
CRC::enable_and_reset();
// Peripheral the peripheral
let mut instance = Self { _peri: peripheral };
instance.reset();

2
embassy-stm32/src/crc/v2v3.rs
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@ -70,7 +70,7 @@ impl<'d> Crc<'d> {
pub fn new(peripheral: impl Peripheral<P = CRC> + 'd, config: Config) -> Self {
// Note: enable and reset come from RccPeripheral.
// reset to default values and enable CRC clock in RCC.
CRC::reset_and_enable();
CRC::enable_and_reset();
into_ref!(peripheral);
let mut instance = Self {
_peripheral: peripheral,

8
embassy-stm32/src/dac/mod.rs
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@ -255,7 +255,7 @@ impl<'d, T: Instance, Tx> DacCh1<'d, T, Tx> {
) -> Self {
pin.set_as_analog();
into_ref!(peri, dma);
T::reset_and_enable();
T::enable_and_reset();
let mut dac = Self { _peri: peri, dma };
@ -365,7 +365,7 @@ impl<'d, T: Instance, Tx> DacCh2<'d, T, Tx> {
) -> Self {
pin.set_as_analog();
into_ref!(_peri, dma);
T::reset_and_enable();
T::enable_and_reset();
let mut dac = Self {
phantom: PhantomData,
@ -481,7 +481,7 @@ impl<'d, T: Instance, TxCh1, TxCh2> Dac<'d, T, TxCh1, TxCh2> {
pin_ch1.set_as_analog();
pin_ch2.set_as_analog();
into_ref!(peri, dma_ch1, dma_ch2);
T::reset_and_enable();
T::enable_and_reset();
let mut dac_ch1 = DacCh1 {
_peri: peri,
@ -567,7 +567,7 @@ foreach_peripheral!(
critical_section::with(|_| unsafe { crate::rcc::get_freqs().apb1 })
}
fn reset_and_enable() {
fn enable_and_reset() {
critical_section::with(|_| {
crate::pac::RCC.apb1lrstr().modify(|w| w.set_dac12rst(true));
crate::pac::RCC.apb1lrstr().modify(|w| w.set_dac12rst(false));

2
embassy-stm32/src/dcmi.rs
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@ -330,7 +330,7 @@ where
use_embedded_synchronization: bool,
edm: u8,
) -> Self {
T::reset_and_enable();
T::enable_and_reset();
peri.regs().cr().modify(|r| {
r.set_cm(true); // disable continuous mode (snapshot mode)

2
embassy-stm32/src/fmc.rs
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@ -19,7 +19,7 @@ where
const REGISTERS: *const () = T::REGS.as_ptr() as *const _;
fn enable(&mut self) {
T::reset_and_enable();
T::enable_and_reset();
}
fn memory_controller_enable(&mut self) {

2
embassy-stm32/src/gpio.rs
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@ -759,7 +759,7 @@ foreach_pin!(
pub(crate) unsafe fn init() {
#[cfg(afio)]
<crate::peripherals::AFIO as crate::rcc::sealed::RccPeripheral>::reset_and_enable();
<crate::peripherals::AFIO as crate::rcc::sealed::RccPeripheral>::enable_and_reset();
crate::_generated::init_gpio();
}

2
embassy-stm32/src/hrtim/mod.rs
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@ -157,7 +157,7 @@ impl<'d, T: Instance> AdvancedPwm<'d, T> {
fn new_inner(tim: impl Peripheral<P = T> + 'd) -> Self {
into_ref!(tim);
T::reset_and_enable();
T::enable_and_reset();
#[cfg(stm32f334)]
if unsafe { get_freqs() }.hrtim.is_some() {

2
embassy-stm32/src/i2c/v1.rs
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@ -56,7 +56,7 @@ impl<'d, T: Instance, TXDMA, RXDMA> I2c<'d, T, TXDMA, RXDMA> {
) -> Self {
into_ref!(scl, sda, tx_dma, rx_dma);
T::reset_and_enable();
T::enable_and_reset();
scl.set_as_af_pull(
scl.af_num(),

2
embassy-stm32/src/i2c/v2.rs
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@ -86,7 +86,7 @@ impl<'d, T: Instance, TXDMA, RXDMA> I2c<'d, T, TXDMA, RXDMA> {
) -> Self {
into_ref!(peri, scl, sda, tx_dma, rx_dma);
T::reset_and_enable();
T::enable_and_reset();
scl.set_as_af_pull(
scl.af_num(),

2
embassy-stm32/src/ipcc.rs
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@ -93,7 +93,7 @@ pub struct Ipcc;
impl Ipcc {
pub fn enable(_config: Config) {
IPCC::reset_and_enable();
IPCC::enable_and_reset();
IPCC::set_cpu2(true);
_configure_pwr();

6
embassy-stm32/src/lib.rs
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@ -186,11 +186,11 @@ pub fn init(config: Config) -> Peripherals {
}
#[cfg(not(any(stm32f1, stm32wb, stm32wl)))]
peripherals::SYSCFG::reset_and_enable();
peripherals::SYSCFG::enable_and_reset();
#[cfg(not(any(stm32h5, stm32h7, stm32wb, stm32wl)))]
peripherals::PWR::reset_and_enable();
peripherals::PWR::enable_and_reset();
#[cfg(not(any(stm32f2, stm32f4, stm32f7, stm32l0, stm32h5, stm32h7)))]
peripherals::FLASH::reset_and_enable();
peripherals::FLASH::enable_and_reset();
unsafe {
#[cfg(feature = "_split-pins-enabled")]

2
embassy-stm32/src/qspi/mod.rs
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@ -177,7 +177,7 @@ impl<'d, T: Instance, Dma> Qspi<'d, T, Dma> {
) -> Self {
into_ref!(peri, dma);
T::reset_and_enable();
T::enable_and_reset();
while T::REGS.sr().read().busy() {}

2
embassy-stm32/src/rcc/g4.rs
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@ -296,7 +296,7 @@ pub(crate) unsafe fn init(config: Config) {
// Enable and setup CRS if needed
if let Some(crs_config) = crs_config {
crate::peripherals::CRS::reset_and_enable();
crate::peripherals::CRS::enable_and_reset();
let sync_src = match crs_config.sync_src {
CrsSyncSource::Gpio => crate::pac::crs::vals::Syncsrc::GPIO,

2
embassy-stm32/src/rcc/mod.rs
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@ -231,7 +231,7 @@ pub mod low_level {
pub(crate) mod sealed {
pub trait RccPeripheral {
fn frequency() -> crate::time::Hertz;
fn reset_and_enable();
fn enable_and_reset();
fn disable();
}
}

2
embassy-stm32/src/rng.rs
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@ -43,7 +43,7 @@ impl<'d, T: Instance> Rng<'d, T> {
inner: impl Peripheral<P = T> + 'd,
_irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
) -> Self {
T::reset_and_enable();
T::enable_and_reset();
into_ref!(inner);
let mut random = Self { _inner: inner };
random.reset();

2
embassy-stm32/src/rtc/mod.rs
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@ -184,7 +184,7 @@ impl Default for RtcCalibrationCyclePeriod {
impl Rtc {
pub fn new(_rtc: impl Peripheral<P = RTC>, rtc_config: RtcConfig) -> Self {
#[cfg(not(any(stm32l0, stm32f3, stm32l1, stm32f0, stm32f2)))]
<RTC as crate::rcc::sealed::RccPeripheral>::reset_and_enable();
<RTC as crate::rcc::sealed::RccPeripheral>::enable_and_reset();
let mut this = Self {
#[cfg(feature = "low-power")]

4
embassy-stm32/src/sai/mod.rs
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@ -580,7 +580,7 @@ fn get_ring_buffer<'d, T: Instance, C: Channel, W: word::Word>(
impl<'d, T: Instance> Sai<'d, T> {
pub fn new(peri: impl Peripheral<P = T> + 'd) -> Self {
T::reset_and_enable();
T::enable_and_reset();
Self {
_peri: unsafe { peri.clone_unchecked().into_ref() },
@ -960,7 +960,7 @@ impl<'d, T: Instance, C: Channel, W: word::Word> SubBlock<'d, T, C, W> {
}
pub fn reset() {
T::reset_and_enable();
T::enable_and_reset();
}
pub fn flush(&mut self) {

2
embassy-stm32/src/sdmmc/mod.rs
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@ -452,7 +452,7 @@ impl<'d, T: Instance, Dma: SdmmcDma<T> + 'd> Sdmmc<'d, T, Dma> {
) -> Self {
into_ref!(sdmmc, dma);
T::reset_and_enable();
T::enable_and_reset();
T::Interrupt::unpend();
unsafe { T::Interrupt::enable() };

2
embassy-stm32/src/spi/mod.rs
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@ -230,7 +230,7 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
let lsbfirst = config.raw_byte_order();
T::reset_and_enable();
T::enable_and_reset();
#[cfg(any(spi_v1, spi_f1))]
{

2
embassy-stm32/src/time_driver.rs
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@ -155,7 +155,7 @@ impl RtcDriver {
fn init(&'static self) {
let r = T::regs_gp16();
<T as RccPeripheral>::reset_and_enable();
<T as RccPeripheral>::enable_and_reset();
let timer_freq = T::frequency();

2
embassy-stm32/src/timer/complementary_pwm.rs
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@ -64,7 +64,7 @@ impl<'d, T: ComplementaryCaptureCompare16bitInstance> ComplementaryPwm<'d, T> {
fn new_inner(tim: impl Peripheral<P = T> + 'd, freq: Hertz) -> Self {
into_ref!(tim);
T::reset_and_enable();
T::enable_and_reset();
let mut this = Self { inner: tim };

2
embassy-stm32/src/timer/qei.rs
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@ -55,7 +55,7 @@ impl<'d, T: CaptureCompare16bitInstance> Qei<'d, T> {
fn new_inner(tim: impl Peripheral<P = T> + 'd) -> Self {
into_ref!(tim);
T::reset_and_enable();
T::enable_and_reset();
// Configure TxC1 and TxC2 as captures
T::regs_gp16().ccmr_input(0).modify(|w| {

2
embassy-stm32/src/timer/simple_pwm.rs
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@ -63,7 +63,7 @@ impl<'d, T: CaptureCompare16bitInstance> SimplePwm<'d, T> {
fn new_inner(tim: impl Peripheral<P = T> + 'd, freq: Hertz) -> Self {
into_ref!(tim);
T::reset_and_enable();
T::enable_and_reset();
let mut this = Self { inner: tim };

12
embassy-stm32/src/usart/buffered.rs
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@ -152,8 +152,8 @@ impl<'d, T: BasicInstance> BufferedUart<'d, T> {
config: Config,
) -> Result<Self, ConfigError> {
// UartRx and UartTx have one refcount ea.
T::reset_and_enable();
T::reset_and_enable();
T::enable_and_reset();
T::enable_and_reset();
Self::new_inner(peri, rx, tx, tx_buffer, rx_buffer, config)
}
@ -172,8 +172,8 @@ impl<'d, T: BasicInstance> BufferedUart<'d, T> {
into_ref!(cts, rts);
// UartRx and UartTx have one refcount ea.
T::reset_and_enable();
T::reset_and_enable();
T::enable_and_reset();
T::enable_and_reset();
rts.set_as_af(rts.af_num(), AFType::OutputPushPull);
cts.set_as_af(cts.af_num(), AFType::Input);
@ -199,8 +199,8 @@ impl<'d, T: BasicInstance> BufferedUart<'d, T> {
into_ref!(de);
// UartRx and UartTx have one refcount ea.
T::reset_and_enable();
T::reset_and_enable();
T::enable_and_reset();
T::enable_and_reset();
de.set_as_af(de.af_num(), AFType::OutputPushPull);
T::regs().cr3().write(|w| {

20
embassy-stm32/src/usart/mod.rs
View File

@ -228,7 +228,7 @@ impl<'d, T: BasicInstance, TxDma> UartTx<'d, T, TxDma> {
tx_dma: impl Peripheral<P = TxDma> + 'd,
config: Config,
) -> Result<Self, ConfigError> {
T::reset_and_enable();
T::enable_and_reset();
Self::new_inner(peri, tx, tx_dma, config)
}
@ -242,7 +242,7 @@ impl<'d, T: BasicInstance, TxDma> UartTx<'d, T, TxDma> {
) -> Result<Self, ConfigError> {
into_ref!(cts);
T::reset_and_enable();
T::enable_and_reset();
cts.set_as_af(cts.af_num(), AFType::Input);
T::regs().cr3().write(|w| {
@ -319,7 +319,7 @@ impl<'d, T: BasicInstance, RxDma> UartRx<'d, T, RxDma> {
rx_dma: impl Peripheral<P = RxDma> + 'd,
config: Config,
) -> Result<Self, ConfigError> {
T::reset_and_enable();
T::enable_and_reset();
Self::new_inner(peri, rx, rx_dma, config)
}
@ -334,7 +334,7 @@ impl<'d, T: BasicInstance, RxDma> UartRx<'d, T, RxDma> {
) -> Result<Self, ConfigError> {
into_ref!(rts);
T::reset_and_enable();
T::enable_and_reset();
rts.set_as_af(rts.af_num(), AFType::OutputPushPull);
T::regs().cr3().write(|w| {
@ -691,8 +691,8 @@ impl<'d, T: BasicInstance, TxDma, RxDma> Uart<'d, T, TxDma, RxDma> {
config: Config,
) -> Result<Self, ConfigError> {
// UartRx and UartTx have one refcount ea.
T::reset_and_enable();
T::reset_and_enable();
T::enable_and_reset();
T::enable_and_reset();
Self::new_inner(peri, rx, tx, tx_dma, rx_dma, config)
}
@ -711,8 +711,8 @@ impl<'d, T: BasicInstance, TxDma, RxDma> Uart<'d, T, TxDma, RxDma> {
into_ref!(cts, rts);
// UartRx and UartTx have one refcount ea.
T::reset_and_enable();
T::reset_and_enable();
T::enable_and_reset();
T::enable_and_reset();
rts.set_as_af(rts.af_num(), AFType::OutputPushPull);
cts.set_as_af(cts.af_num(), AFType::Input);
@ -737,8 +737,8 @@ impl<'d, T: BasicInstance, TxDma, RxDma> Uart<'d, T, TxDma, RxDma> {
into_ref!(de);
// UartRx and UartTx have one refcount ea.
T::reset_and_enable();
T::reset_and_enable();
T::enable_and_reset();
T::enable_and_reset();
de.set_as_af(de.af_num(), AFType::OutputPushPull);
T::regs().cr3().write(|w| {

2
embassy-stm32/src/usb/usb.rs
View File

@ -269,7 +269,7 @@ impl<'d, T: Instance> Driver<'d, T> {
#[cfg(pwr_h5)]
crate::pac::PWR.usbscr().modify(|w| w.set_usb33sv(true));
<T as RccPeripheral>::reset_and_enable();
<T as RccPeripheral>::enable_and_reset();
regs.cntr().write(|w| {
w.set_pdwn(false);

2
embassy-stm32/src/usb_otg/usb.rs
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@ -632,7 +632,7 @@ impl<'d, T: Instance> Bus<'d, T> {
});
}
<T as RccPeripheral>::reset_and_enable();
<T as RccPeripheral>::enable_and_reset();
T::Interrupt::unpend();
unsafe { T::Interrupt::enable() };

4
examples/stm32h7/src/bin/dac_dma.rs
View File

@ -79,7 +79,7 @@ async fn dac_task1(mut dac: Dac1Type) {
dac.select_trigger(embassy_stm32::dac::Ch1Trigger::Tim6).unwrap();
dac.enable_channel().unwrap();
TIM6::reset_and_enable();
TIM6::enable_and_reset();
TIM6::regs().arr().modify(|w| w.set_arr(reload as u16 - 1));
TIM6::regs().cr2().modify(|w| w.set_mms(Mms::UPDATE));
TIM6::regs().cr1().modify(|w| {
@ -118,7 +118,7 @@ async fn dac_task2(mut dac: Dac2Type) {
error!("Reload value {} below threshold!", reload);
}
TIM7::reset_and_enable();
TIM7::enable_and_reset();
TIM7::regs().arr().modify(|w| w.set_arr(reload as u16 - 1));
TIM7::regs().cr2().modify(|w| w.set_mms(Mms::UPDATE));
TIM7::regs().cr1().modify(|w| {

2
examples/stm32h7/src/bin/low_level_timer_api.rs
View File

@ -73,7 +73,7 @@ impl<'d, T: CaptureCompare32bitInstance> SimplePwm32<'d, T> {
) -> Self {
into_ref!(tim, ch1, ch2, ch3, ch4);
T::reset_and_enable();
T::enable_and_reset();
ch1.set_speed(Speed::VeryHigh);
ch1.set_as_af(ch1.af_num(), AFType::OutputPushPull);

4
examples/stm32l4/src/bin/dac_dma.rs
View File

@ -51,7 +51,7 @@ async fn dac_task1(mut dac: Dac1Type) {
dac.select_trigger(embassy_stm32::dac::Ch1Trigger::Tim6).unwrap();
dac.enable_channel().unwrap();
TIM6::reset_and_enable();
TIM6::enable_and_reset();
TIM6::regs().arr().modify(|w| w.set_arr(reload as u16 - 1));
TIM6::regs().cr2().modify(|w| w.set_mms(Mms::UPDATE));
TIM6::regs().cr1().modify(|w| {
@ -90,7 +90,7 @@ async fn dac_task2(mut dac: Dac2Type) {
error!("Reload value {} below threshold!", reload);
}
TIM7::reset_and_enable();
TIM7::enable_and_reset();
TIM7::regs().arr().modify(|w| w.set_arr(reload as u16 - 1));
TIM7::regs().cr2().modify(|w| w.set_mms(Mms::UPDATE));
TIM7::regs().cr1().modify(|w| {