2023-02-01 00:48:33 +01:00
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//! Timer driver.
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//!
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//! Important note! This driver is very low level. For most time-related use cases, like
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//! "sleep for X seconds", "do something every X seconds", or measuring time, you should
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//! use [`embassy-time`](https://crates.io/crates/embassy-time) instead!
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2021-05-11 03:04:59 +02:00
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#![macro_use]
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2022-07-23 15:13:47 +02:00
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use embassy_hal_common::{into_ref, PeripheralRef};
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2021-03-28 22:40:41 +02:00
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2023-03-05 20:27:33 +01:00
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use crate::interrupt::Interrupt;
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2021-10-19 10:13:08 +02:00
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use crate::ppi::{Event, Task};
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2022-07-23 14:00:19 +02:00
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use crate::{pac, Peripheral};
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2021-03-28 22:40:41 +02:00
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2021-05-11 03:04:59 +02:00
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pub(crate) mod sealed {
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2021-06-26 09:58:36 +02:00
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2021-03-28 22:40:41 +02:00
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use super::*;
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pub trait Instance {
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2021-06-26 09:58:36 +02:00
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/// The number of CC registers this instance has.
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const CCS: usize;
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fn regs() -> &'static pac::timer0::RegisterBlock;
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2021-03-28 22:40:41 +02:00
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}
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pub trait ExtendedInstance {}
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2021-09-01 16:16:56 +02:00
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pub trait TimerType {}
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2021-03-28 22:40:41 +02:00
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}
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2023-02-01 00:48:33 +01:00
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/// Basic Timer instance.
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2022-07-23 14:00:19 +02:00
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pub trait Instance: Peripheral<P = Self> + sealed::Instance + 'static + Send {
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2023-02-01 00:48:33 +01:00
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/// Interrupt for this peripheral.
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2021-03-28 22:40:41 +02:00
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type Interrupt: Interrupt;
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}
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2023-02-01 00:48:33 +01:00
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/// Extended timer instance.
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2021-03-28 22:40:41 +02:00
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pub trait ExtendedInstance: Instance + sealed::ExtendedInstance {}
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2021-05-11 03:04:59 +02:00
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macro_rules! impl_timer {
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2021-06-26 09:58:36 +02:00
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($type:ident, $pac_type:ident, $irq:ident, $ccs:literal) => {
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2021-05-11 03:04:59 +02:00
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impl crate::timer::sealed::Instance for peripherals::$type {
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2021-06-26 09:58:36 +02:00
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const CCS: usize = $ccs;
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fn regs() -> &'static pac::timer0::RegisterBlock {
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2021-05-11 03:04:59 +02:00
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unsafe { &*(pac::$pac_type::ptr() as *const pac::timer0::RegisterBlock) }
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2021-03-28 22:40:41 +02:00
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}
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}
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2021-05-11 03:04:59 +02:00
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impl crate::timer::Instance for peripherals::$type {
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type Interrupt = crate::interrupt::$irq;
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2021-03-28 22:40:41 +02:00
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}
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};
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2021-06-26 09:58:36 +02:00
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($type:ident, $pac_type:ident, $irq:ident) => {
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impl_timer!($type, $pac_type, $irq, 4);
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};
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2021-05-11 03:04:59 +02:00
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($type:ident, $pac_type:ident, $irq:ident, extended) => {
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2021-06-26 09:58:36 +02:00
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impl_timer!($type, $pac_type, $irq, 6);
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2021-05-11 03:04:59 +02:00
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impl crate::timer::sealed::ExtendedInstance for peripherals::$type {}
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impl crate::timer::ExtendedInstance for peripherals::$type {}
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2021-03-28 22:40:41 +02:00
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};
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}
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2021-06-26 09:58:36 +02:00
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2023-02-01 00:48:33 +01:00
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/// Timer frequency
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2021-06-26 09:58:36 +02:00
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#[repr(u8)]
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pub enum Frequency {
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2023-02-01 00:48:33 +01:00
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/// 16MHz
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2021-06-26 09:58:36 +02:00
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F16MHz = 0,
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2023-02-01 00:48:33 +01:00
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/// 8MHz
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2021-06-26 09:58:36 +02:00
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F8MHz = 1,
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2023-02-01 00:48:33 +01:00
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/// 4MHz
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2021-06-26 09:58:36 +02:00
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F4MHz = 2,
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2023-02-01 00:48:33 +01:00
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/// 2MHz
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2021-06-26 09:58:36 +02:00
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F2MHz = 3,
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2023-02-01 00:48:33 +01:00
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/// 1MHz
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F1MHz = 4,
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2023-02-01 00:48:33 +01:00
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/// 500kHz
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2021-06-26 09:58:36 +02:00
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F500kHz = 5,
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2023-02-01 00:48:33 +01:00
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/// 250kHz
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F250kHz = 6,
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2023-02-01 00:48:33 +01:00
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/// 125kHz
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2021-06-26 09:58:36 +02:00
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F125kHz = 7,
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2023-02-01 00:48:33 +01:00
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/// 62500Hz
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2021-06-26 09:58:36 +02:00
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F62500Hz = 8,
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2023-02-01 00:48:33 +01:00
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/// 31250Hz
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2021-06-26 09:58:36 +02:00
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F31250Hz = 9,
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}
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/// nRF Timer driver.
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///
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/// The timer has an internal counter, which is incremented for every tick of the timer.
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2023-03-05 20:27:33 +01:00
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/// The counter is 32-bit, so it wraps back to 0 when it reaches 2^32.
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2021-06-26 09:58:36 +02:00
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///
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/// It has either 4 or 6 Capture/Compare registers, which can be used to capture the current state of the counter
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/// or trigger an event when the counter reaches a certain value.
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2021-09-01 16:16:56 +02:00
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2023-02-01 00:48:33 +01:00
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/// Timer driver.
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2023-03-05 20:27:33 +01:00
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pub struct Timer<'d, T: Instance> {
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2022-07-23 15:13:47 +02:00
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_p: PeripheralRef<'d, T>,
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2021-09-01 16:16:56 +02:00
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}
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2023-02-01 00:48:33 +01:00
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2023-03-05 20:27:33 +01:00
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impl<'d, T: Instance> Timer<'d, T> {
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/// Create a new `Timer` driver.
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2021-09-02 12:02:31 +02:00
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///
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/// This can be useful for triggering tasks via PPI
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/// `Uarte` uses this internally.
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2022-07-23 14:00:19 +02:00
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pub fn new(timer: impl Peripheral<P = T> + 'd) -> Self {
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2023-03-04 05:25:57 +01:00
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Self::new_inner(timer, false)
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}
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2023-03-05 20:27:33 +01:00
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/// Create a new `Timer` driver in counter mode.
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2023-03-04 05:25:57 +01:00
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///
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/// This can be useful for triggering tasks via PPI
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/// `Uarte` uses this internally.
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pub fn new_counter(timer: impl Peripheral<P = T> + 'd) -> Self {
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Self::new_inner(timer, true)
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}
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2021-06-26 09:58:36 +02:00
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2023-03-04 05:25:57 +01:00
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fn new_inner(timer: impl Peripheral<P = T> + 'd, is_counter: bool) -> Self {
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2022-07-23 15:13:47 +02:00
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into_ref!(timer);
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2021-06-26 09:58:36 +02:00
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let regs = T::regs();
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2023-04-11 23:00:14 +02:00
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let this = Self { _p: timer };
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2021-06-29 03:29:32 +02:00
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// Stop the timer before doing anything else,
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// since changing BITMODE while running can cause 'unpredictable behaviour' according to the specification.
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this.stop();
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2023-03-04 05:25:57 +01:00
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if is_counter {
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regs.mode.write(|w| w.mode().counter());
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} else {
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regs.mode.write(|w| w.mode().timer());
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}
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2021-06-26 09:58:36 +02:00
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// Make the counter's max value as high as possible.
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// TODO: is there a reason someone would want to set this lower?
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regs.bitmode.write(|w| w.bitmode()._32bit());
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// Initialize the counter at 0.
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this.clear();
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2021-06-29 03:29:32 +02:00
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// Default to the max frequency of the lower power clock
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this.set_frequency(Frequency::F1MHz);
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2021-06-26 09:58:36 +02:00
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for n in 0..T::CCS {
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2021-06-29 02:33:41 +02:00
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let cc = this.cc(n);
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// Initialize all the shorts as disabled.
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2021-06-26 09:58:36 +02:00
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cc.unshort_compare_clear();
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cc.unshort_compare_stop();
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2021-06-29 02:33:41 +02:00
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// Initialize the CC registers as 0.
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cc.write(0);
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}
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this
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}
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/// Starts the timer.
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pub fn start(&self) {
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T::regs().tasks_start.write(|w| unsafe { w.bits(1) })
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}
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/// Stops the timer.
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pub fn stop(&self) {
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T::regs().tasks_stop.write(|w| unsafe { w.bits(1) })
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}
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/// Reset the timer's counter to 0.
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pub fn clear(&self) {
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T::regs().tasks_clear.write(|w| unsafe { w.bits(1) })
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}
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/// Returns the START task, for use with PPI.
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///
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/// When triggered, this task starts the timer.
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pub fn task_start(&self) -> Task {
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2021-10-18 16:23:39 +02:00
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Task::from_reg(&T::regs().tasks_start)
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}
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/// Returns the STOP task, for use with PPI.
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///
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/// When triggered, this task stops the timer.
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pub fn task_stop(&self) -> Task {
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2021-10-18 16:23:39 +02:00
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Task::from_reg(&T::regs().tasks_stop)
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}
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/// Returns the CLEAR task, for use with PPI.
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///
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/// When triggered, this task resets the timer's counter to 0.
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pub fn task_clear(&self) -> Task {
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2021-10-18 16:23:39 +02:00
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Task::from_reg(&T::regs().tasks_clear)
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2021-06-26 09:58:36 +02:00
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}
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2023-03-04 05:25:57 +01:00
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/// Returns the COUNT task, for use with PPI.
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///
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/// When triggered, this task increments the timer's counter by 1.
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/// Only works in counter mode.
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pub fn task_count(&self) -> Task {
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Task::from_reg(&T::regs().tasks_count)
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}
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2021-06-26 09:58:36 +02:00
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/// Change the timer's frequency.
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///
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/// This will stop the timer if it isn't already stopped,
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/// because the timer may exhibit 'unpredictable behaviour' if it's frequency is changed while it's running.
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pub fn set_frequency(&self, frequency: Frequency) {
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self.stop();
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T::regs()
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.prescaler
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// SAFETY: `frequency` is a variant of `Frequency`,
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// whose values are all in the range of 0-9 (the valid range of `prescaler`).
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.write(|w| unsafe { w.prescaler().bits(frequency as u8) })
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}
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2021-06-29 02:33:41 +02:00
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/// Returns this timer's `n`th CC register.
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///
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/// # Panics
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/// Panics if `n` >= the number of CC registers this timer has (4 for a normal timer, 6 for an extended timer).
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2023-03-05 20:27:33 +01:00
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pub fn cc(&mut self, n: usize) -> Cc<T> {
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2021-06-29 02:33:41 +02:00
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if n >= T::CCS {
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2022-06-12 22:15:44 +02:00
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panic!("Cannot get CC register {} of timer with {} CC registers.", n, T::CCS);
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2021-06-26 09:58:36 +02:00
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}
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Cc {
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2021-06-29 02:33:41 +02:00
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n,
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_p: self._p.reborrow(),
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}
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}
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}
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/// A representation of a timer's Capture/Compare (CC) register.
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///
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/// A CC register holds a 32-bit value.
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/// This is used either to store a capture of the timer's current count, or to specify the value for the timer to compare against.
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///
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/// The timer will fire the register's COMPARE event when its counter reaches the value stored in the register.
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/// When the register's CAPTURE task is triggered, the timer will store the current value of its counter in the register
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2023-03-05 20:27:33 +01:00
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pub struct Cc<'d, T: Instance> {
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n: usize,
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_p: PeripheralRef<'d, T>,
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2021-09-01 16:20:32 +02:00
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}
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2021-09-01 16:16:56 +02:00
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2023-03-05 20:27:33 +01:00
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impl<'d, T: Instance> Cc<'d, T> {
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2021-06-26 09:58:36 +02:00
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/// Get the current value stored in the register.
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2021-06-29 02:33:41 +02:00
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pub fn read(&self) -> u32 {
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2021-06-26 09:58:36 +02:00
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T::regs().cc[self.n].read().cc().bits()
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}
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/// Set the value stored in the register.
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///
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/// `event_compare` will fire when the timer's counter reaches this value.
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2021-06-29 02:33:41 +02:00
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pub fn write(&self, value: u32) {
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2021-06-26 09:58:36 +02:00
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// SAFETY: there are no invalid values for the CC register.
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T::regs().cc[self.n].write(|w| unsafe { w.cc().bits(value) })
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}
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/// Capture the current value of the timer's counter in this register, and return it.
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pub fn capture(&self) -> u32 {
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2021-06-29 05:04:05 +02:00
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T::regs().tasks_capture[self.n].write(|w| unsafe { w.bits(1) });
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2021-06-29 02:33:41 +02:00
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self.read()
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2021-06-26 09:58:36 +02:00
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}
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/// Returns this CC register's CAPTURE task, for use with PPI.
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///
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/// When triggered, this task will capture the current value of the timer's counter in this register.
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pub fn task_capture(&self) -> Task {
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2021-10-18 16:23:39 +02:00
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Task::from_reg(&T::regs().tasks_capture)
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2021-06-26 09:58:36 +02:00
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}
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/// Returns this CC register's COMPARE event, for use with PPI.
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///
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/// This event will fire when the timer's counter reaches the value in this CC register.
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pub fn event_compare(&self) -> Event {
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2021-10-18 16:23:39 +02:00
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Event::from_reg(&T::regs().events_compare[self.n])
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2021-06-26 09:58:36 +02:00
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}
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/// Enable the shortcut between this CC register's COMPARE event and the timer's CLEAR task.
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///
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/// This means that when the COMPARE event is fired, the CLEAR task will be triggered.
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///
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/// So, when the timer's counter reaches the value stored in this register, the timer's counter will be reset to 0.
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pub fn short_compare_clear(&self) {
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2021-06-29 06:37:37 +02:00
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T::regs()
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.shorts
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.modify(|r, w| unsafe { w.bits(r.bits() | (1 << self.n)) })
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2021-06-26 09:58:36 +02:00
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}
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/// Disable the shortcut between this CC register's COMPARE event and the timer's CLEAR task.
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pub fn unshort_compare_clear(&self) {
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2021-06-29 06:37:37 +02:00
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T::regs()
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.shorts
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2021-06-29 07:12:42 +02:00
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.modify(|r, w| unsafe { w.bits(r.bits() & !(1 << self.n)) })
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2021-06-26 09:58:36 +02:00
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}
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/// Enable the shortcut between this CC register's COMPARE event and the timer's STOP task.
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///
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/// This means that when the COMPARE event is fired, the STOP task will be triggered.
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///
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/// So, when the timer's counter reaches the value stored in this register, the timer will stop counting up.
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pub fn short_compare_stop(&self) {
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2021-06-29 06:37:37 +02:00
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T::regs()
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.shorts
|
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|
.modify(|r, w| unsafe { w.bits(r.bits() | (1 << (8 + self.n))) })
|
2021-06-26 09:58:36 +02:00
|
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}
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/// Disable the shortcut between this CC register's COMPARE event and the timer's STOP task.
|
|
|
|
pub fn unshort_compare_stop(&self) {
|
2021-06-29 06:37:37 +02:00
|
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T::regs()
|
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|
|
.shorts
|
2021-06-29 07:12:42 +02:00
|
|
|
.modify(|r, w| unsafe { w.bits(r.bits() & !(1 << (8 + self.n))) })
|
2021-06-26 09:58:36 +02:00
|
|
|
}
|
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|
}
|