2021-05-13 20:28:53 +02:00
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#![macro_use]
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2021-12-06 21:47:50 +01:00
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use crate::dma;
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2021-12-07 05:45:40 +01:00
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use crate::dma::NoDma;
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2021-12-06 22:19:24 +01:00
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use crate::gpio::sealed::{AFType, Pin};
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2021-12-06 21:47:50 +01:00
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use crate::gpio::{AnyPin, NoPin, OptionalPin};
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2021-12-07 02:12:34 +01:00
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use crate::pac::spi::{regs, vals};
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2021-12-06 21:47:50 +01:00
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use crate::peripherals;
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use crate::rcc::RccPeripheral;
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2021-12-06 22:19:24 +01:00
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use crate::time::Hertz;
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2021-12-07 05:06:58 +01:00
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use core::future::Future;
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2021-12-06 21:47:50 +01:00
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use core::marker::PhantomData;
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2021-12-07 05:45:40 +01:00
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use core::ptr;
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2021-12-06 22:19:24 +01:00
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use embassy::util::Unborrow;
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use embassy_hal_common::unborrow;
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2021-12-07 05:06:58 +01:00
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use embassy_traits::spi as traits;
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2021-12-06 21:47:50 +01:00
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2021-07-21 20:12:50 +02:00
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#[cfg_attr(spi_v1, path = "v1.rs")]
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2021-10-06 21:02:15 +02:00
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#[cfg_attr(spi_f1, path = "v1.rs")]
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2021-07-21 22:50:38 +02:00
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#[cfg_attr(spi_v2, path = "v2.rs")]
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#[cfg_attr(spi_v3, path = "v3.rs")]
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2021-05-17 02:04:51 +02:00
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mod _version;
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pub use _version::*;
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2021-05-13 20:28:53 +02:00
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2021-08-31 14:32:48 +02:00
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#[derive(Debug)]
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2021-05-20 10:54:10 +02:00
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#[cfg_attr(feature = "defmt", derive(defmt::Format))]
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2021-05-14 16:11:43 +02:00
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pub enum Error {
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Framing,
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Crc,
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2021-05-27 23:05:42 +02:00
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ModeFault,
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2021-05-14 16:11:43 +02:00
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Overrun,
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}
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2021-05-13 20:28:53 +02:00
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// TODO move upwards in the tree
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pub enum ByteOrder {
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LsbFirst,
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MsbFirst,
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}
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#[derive(Copy, Clone, PartialOrd, PartialEq)]
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enum WordSize {
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EightBit,
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SixteenBit,
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}
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2021-12-06 21:13:25 +01:00
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impl WordSize {
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#[cfg(any(spi_v1, spi_f1))]
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fn dff(&self) -> vals::Dff {
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match self {
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WordSize::EightBit => vals::Dff::EIGHTBIT,
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WordSize::SixteenBit => vals::Dff::SIXTEENBIT,
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}
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}
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#[cfg(spi_v2)]
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fn ds(&self) -> vals::Ds {
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match self {
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WordSize::EightBit => vals::Ds::EIGHTBIT,
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WordSize::SixteenBit => vals::Ds::SIXTEENBIT,
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}
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}
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#[cfg(spi_v2)]
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fn frxth(&self) -> vals::Frxth {
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match self {
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WordSize::EightBit => vals::Frxth::QUARTER,
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WordSize::SixteenBit => vals::Frxth::HALF,
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}
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}
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#[cfg(spi_v3)]
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fn dsize(&self) -> u8 {
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match self {
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WordSize::EightBit => 0b0111,
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WordSize::SixteenBit => 0b1111,
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}
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}
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#[cfg(spi_v3)]
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fn _frxth(&self) -> vals::Fthlv {
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match self {
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WordSize::EightBit => vals::Fthlv::ONEFRAME,
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WordSize::SixteenBit => vals::Fthlv::ONEFRAME,
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}
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}
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}
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2021-05-13 20:28:53 +02:00
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#[non_exhaustive]
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pub struct Config {
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pub mode: Mode,
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pub byte_order: ByteOrder,
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}
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impl Default for Config {
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fn default() -> Self {
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Self {
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mode: MODE_0,
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byte_order: ByteOrder::MsbFirst,
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}
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}
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}
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2021-05-14 16:11:43 +02:00
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2021-12-06 21:47:50 +01:00
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pub struct Spi<'d, T: Instance, Tx, Rx> {
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sck: Option<AnyPin>,
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mosi: Option<AnyPin>,
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miso: Option<AnyPin>,
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txdma: Tx,
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rxdma: Rx,
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current_word_size: WordSize,
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phantom: PhantomData<&'d mut T>,
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}
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2021-12-06 22:19:24 +01:00
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impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
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pub fn new<F>(
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_peri: impl Unborrow<Target = T> + 'd,
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sck: impl Unborrow<Target = impl SckPin<T>>,
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mosi: impl Unborrow<Target = impl MosiPin<T>>,
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miso: impl Unborrow<Target = impl MisoPin<T>>,
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txdma: impl Unborrow<Target = Tx>,
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rxdma: impl Unborrow<Target = Rx>,
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freq: F,
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config: Config,
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) -> Self
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where
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F: Into<Hertz>,
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{
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unborrow!(sck, mosi, miso, txdma, rxdma);
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let sck_af = sck.af_num();
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let mosi_af = mosi.af_num();
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let miso_af = miso.af_num();
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let sck = sck.degrade_optional();
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let mosi = mosi.degrade_optional();
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let miso = miso.degrade_optional();
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unsafe {
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sck.as_ref().map(|x| {
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x.set_as_af(sck_af, AFType::OutputPushPull);
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#[cfg(any(spi_v2, spi_v3))]
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x.set_speed(crate::gpio::Speed::VeryHigh);
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});
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mosi.as_ref().map(|x| {
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x.set_as_af(mosi_af, AFType::OutputPushPull);
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#[cfg(any(spi_v2, spi_v3))]
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x.set_speed(crate::gpio::Speed::VeryHigh);
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});
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miso.as_ref().map(|x| {
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x.set_as_af(miso_af, AFType::Input);
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#[cfg(any(spi_v2, spi_v3))]
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x.set_speed(crate::gpio::Speed::VeryHigh);
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});
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}
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let pclk = T::frequency();
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let br = Self::compute_baud_rate(pclk, freq.into());
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#[cfg(any(spi_v1, spi_f1))]
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unsafe {
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T::enable();
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T::reset();
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T::regs().cr2().modify(|w| {
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w.set_ssoe(false);
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});
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T::regs().cr1().modify(|w| {
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w.set_cpha(
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match config.mode.phase == Phase::CaptureOnSecondTransition {
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true => vals::Cpha::SECONDEDGE,
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false => vals::Cpha::FIRSTEDGE,
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},
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);
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w.set_cpol(match config.mode.polarity == Polarity::IdleHigh {
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true => vals::Cpol::IDLEHIGH,
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false => vals::Cpol::IDLELOW,
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});
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w.set_mstr(vals::Mstr::MASTER);
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w.set_br(vals::Br(br));
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w.set_spe(true);
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w.set_lsbfirst(match config.byte_order {
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ByteOrder::LsbFirst => vals::Lsbfirst::LSBFIRST,
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ByteOrder::MsbFirst => vals::Lsbfirst::MSBFIRST,
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});
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w.set_ssi(true);
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w.set_ssm(true);
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w.set_crcen(false);
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w.set_bidimode(vals::Bidimode::UNIDIRECTIONAL);
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if mosi.is_none() {
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w.set_rxonly(vals::Rxonly::OUTPUTDISABLED);
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}
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w.set_dff(WordSize::EightBit.dff())
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});
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}
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#[cfg(spi_v2)]
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unsafe {
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T::enable();
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T::reset();
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T::regs().cr2().modify(|w| {
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2021-12-07 05:36:53 +01:00
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w.set_frxth(WordSize::EightBit.frxth());
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w.set_ds(WordSize::EightBit.ds());
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2021-12-06 22:19:24 +01:00
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w.set_ssoe(false);
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});
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T::regs().cr1().modify(|w| {
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w.set_cpha(
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match config.mode.phase == Phase::CaptureOnSecondTransition {
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true => vals::Cpha::SECONDEDGE,
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false => vals::Cpha::FIRSTEDGE,
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},
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);
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w.set_cpol(match config.mode.polarity == Polarity::IdleHigh {
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true => vals::Cpol::IDLEHIGH,
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false => vals::Cpol::IDLELOW,
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});
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w.set_mstr(vals::Mstr::MASTER);
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w.set_br(vals::Br(br));
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w.set_lsbfirst(match config.byte_order {
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ByteOrder::LsbFirst => vals::Lsbfirst::LSBFIRST,
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ByteOrder::MsbFirst => vals::Lsbfirst::MSBFIRST,
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});
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w.set_ssi(true);
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w.set_ssm(true);
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w.set_crcen(false);
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w.set_bidimode(vals::Bidimode::UNIDIRECTIONAL);
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w.set_spe(true);
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});
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}
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#[cfg(spi_v3)]
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unsafe {
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T::enable();
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T::reset();
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T::regs().ifcr().write(|w| w.0 = 0xffff_ffff);
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T::regs().cfg2().modify(|w| {
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//w.set_ssoe(true);
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w.set_ssoe(false);
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w.set_cpha(
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match config.mode.phase == Phase::CaptureOnSecondTransition {
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true => vals::Cpha::SECONDEDGE,
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false => vals::Cpha::FIRSTEDGE,
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},
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);
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w.set_cpol(match config.mode.polarity == Polarity::IdleHigh {
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true => vals::Cpol::IDLEHIGH,
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false => vals::Cpol::IDLELOW,
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});
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w.set_lsbfrst(match config.byte_order {
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ByteOrder::LsbFirst => vals::Lsbfrst::LSBFIRST,
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ByteOrder::MsbFirst => vals::Lsbfrst::MSBFIRST,
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});
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w.set_ssm(true);
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w.set_master(vals::Master::MASTER);
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w.set_comm(vals::Comm::FULLDUPLEX);
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w.set_ssom(vals::Ssom::ASSERTED);
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w.set_midi(0);
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w.set_mssi(0);
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w.set_afcntr(vals::Afcntr::CONTROLLED);
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w.set_ssiop(vals::Ssiop::ACTIVEHIGH);
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});
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T::regs().cfg1().modify(|w| {
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w.set_crcen(false);
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w.set_mbr(vals::Mbr(br));
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w.set_dsize(WordSize::EightBit.dsize());
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});
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T::regs().cr2().modify(|w| {
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w.set_tsize(0);
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w.set_tser(0);
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});
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T::regs().cr1().modify(|w| {
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w.set_ssi(false);
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w.set_spe(true);
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});
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}
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Self {
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sck,
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mosi,
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miso,
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txdma,
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rxdma,
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current_word_size: WordSize::EightBit,
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phantom: PhantomData,
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}
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}
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fn compute_baud_rate(clocks: Hertz, freq: Hertz) -> u8 {
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match clocks.0 / freq.0 {
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0 => unreachable!(),
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1..=2 => 0b000,
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3..=5 => 0b001,
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6..=11 => 0b010,
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12..=23 => 0b011,
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24..=39 => 0b100,
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40..=95 => 0b101,
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96..=191 => 0b110,
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_ => 0b111,
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}
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}
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2021-12-06 23:47:08 +01:00
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fn set_word_size(&mut self, word_size: WordSize) {
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if self.current_word_size == word_size {
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return;
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}
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#[cfg(any(spi_v1, spi_f1))]
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unsafe {
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T::regs().cr1().modify(|reg| {
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reg.set_spe(false);
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reg.set_dff(word_size.dff())
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});
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T::regs().cr1().modify(|reg| {
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reg.set_spe(true);
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});
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}
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#[cfg(spi_v2)]
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unsafe {
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T::regs().cr1().modify(|w| {
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w.set_spe(false);
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});
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T::regs().cr2().modify(|w| {
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w.set_frxth(word_size.frxth());
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w.set_ds(word_size.ds());
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});
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T::regs().cr1().modify(|w| {
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w.set_spe(true);
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});
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}
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#[cfg(spi_v3)]
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unsafe {
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T::regs().cr1().modify(|w| {
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w.set_csusp(true);
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});
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while T::regs().sr().read().eot() {}
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T::regs().cr1().modify(|w| {
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w.set_spe(false);
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});
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T::regs().cfg1().modify(|w| {
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w.set_dsize(word_size.dsize());
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});
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T::regs().cr1().modify(|w| {
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w.set_csusp(false);
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w.set_spe(true);
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});
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}
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self.current_word_size = word_size;
|
|
|
|
}
|
2021-12-06 22:19:24 +01:00
|
|
|
}
|
|
|
|
|
2021-12-06 23:51:10 +01:00
|
|
|
impl<'d, T: Instance, Tx, Rx> Drop for Spi<'d, T, Tx, Rx> {
|
|
|
|
fn drop(&mut self) {
|
|
|
|
unsafe {
|
|
|
|
self.sck.as_ref().map(|x| x.set_as_analog());
|
|
|
|
self.mosi.as_ref().map(|x| x.set_as_analog());
|
|
|
|
self.miso.as_ref().map(|x| x.set_as_analog());
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2021-12-06 23:33:06 +01:00
|
|
|
trait RegsExt {
|
|
|
|
fn tx_ptr<W>(&self) -> *mut W;
|
|
|
|
fn rx_ptr<W>(&self) -> *mut W;
|
|
|
|
}
|
|
|
|
|
|
|
|
impl RegsExt for crate::pac::spi::Spi {
|
|
|
|
fn tx_ptr<W>(&self) -> *mut W {
|
|
|
|
#[cfg(not(spi_v3))]
|
|
|
|
let dr = self.dr();
|
|
|
|
#[cfg(spi_v3)]
|
|
|
|
let dr = self.txdr();
|
|
|
|
dr.ptr() as *mut W
|
|
|
|
}
|
|
|
|
|
|
|
|
fn rx_ptr<W>(&self) -> *mut W {
|
|
|
|
#[cfg(not(spi_v3))]
|
|
|
|
let dr = self.dr();
|
|
|
|
#[cfg(spi_v3)]
|
|
|
|
let dr = self.rxdr();
|
|
|
|
dr.ptr() as *mut W
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2021-12-07 02:12:34 +01:00
|
|
|
fn check_error_flags(sr: regs::Sr) -> Result<(), Error> {
|
|
|
|
if sr.ovr() {
|
|
|
|
return Err(Error::Overrun);
|
|
|
|
}
|
|
|
|
#[cfg(not(any(spi_f1, spi_v3)))]
|
|
|
|
if sr.fre() {
|
|
|
|
return Err(Error::Framing);
|
|
|
|
}
|
|
|
|
#[cfg(spi_v3)]
|
|
|
|
if sr.tifre() {
|
|
|
|
return Err(Error::Framing);
|
|
|
|
}
|
|
|
|
if sr.modf() {
|
|
|
|
return Err(Error::ModeFault);
|
|
|
|
}
|
|
|
|
#[cfg(not(spi_v3))]
|
|
|
|
if sr.crcerr() {
|
|
|
|
return Err(Error::Crc);
|
|
|
|
}
|
|
|
|
#[cfg(spi_v3)]
|
|
|
|
if sr.crce() {
|
|
|
|
return Err(Error::Crc);
|
|
|
|
}
|
|
|
|
|
|
|
|
Ok(())
|
|
|
|
}
|
|
|
|
|
2021-12-07 05:45:40 +01:00
|
|
|
fn spin_until_tx_ready(regs: &'static crate::pac::spi::Spi) -> Result<(), Error> {
|
|
|
|
loop {
|
|
|
|
let sr = unsafe { regs.sr().read() };
|
|
|
|
|
|
|
|
check_error_flags(sr)?;
|
|
|
|
|
|
|
|
#[cfg(not(spi_v3))]
|
|
|
|
if sr.txe() {
|
|
|
|
return Ok(());
|
|
|
|
}
|
|
|
|
#[cfg(spi_v3)]
|
|
|
|
if sr.txp() {
|
|
|
|
return Ok(());
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
fn spin_until_rx_ready(regs: &'static crate::pac::spi::Spi) -> Result<(), Error> {
|
|
|
|
loop {
|
|
|
|
let sr = unsafe { regs.sr().read() };
|
|
|
|
|
|
|
|
check_error_flags(sr)?;
|
|
|
|
|
|
|
|
#[cfg(not(spi_v3))]
|
|
|
|
if sr.rxne() {
|
|
|
|
return Ok(());
|
|
|
|
}
|
|
|
|
#[cfg(spi_v3)]
|
|
|
|
if sr.rxp() {
|
|
|
|
return Ok(());
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2021-12-07 01:16:15 +01:00
|
|
|
trait Word {}
|
|
|
|
|
|
|
|
impl Word for u8 {}
|
|
|
|
impl Word for u16 {}
|
|
|
|
|
2021-12-07 05:45:40 +01:00
|
|
|
fn transfer_word<W: Word>(regs: &'static crate::pac::spi::Spi, tx_word: W) -> Result<W, Error> {
|
|
|
|
spin_until_tx_ready(regs)?;
|
|
|
|
|
|
|
|
unsafe {
|
|
|
|
ptr::write_volatile(regs.tx_ptr(), tx_word);
|
|
|
|
|
|
|
|
#[cfg(spi_v3)]
|
|
|
|
regs.cr1().modify(|reg| reg.set_cstart(true));
|
|
|
|
}
|
|
|
|
|
|
|
|
spin_until_rx_ready(regs)?;
|
|
|
|
|
|
|
|
let rx_word = unsafe { ptr::read_volatile(regs.rx_ptr()) };
|
|
|
|
return Ok(rx_word);
|
|
|
|
}
|
|
|
|
|
|
|
|
impl<'d, T: Instance> embedded_hal::blocking::spi::Write<u8> for Spi<'d, T, NoDma, NoDma> {
|
|
|
|
type Error = Error;
|
|
|
|
|
|
|
|
fn write(&mut self, words: &[u8]) -> Result<(), Self::Error> {
|
|
|
|
self.set_word_size(WordSize::EightBit);
|
|
|
|
let regs = T::regs();
|
|
|
|
|
|
|
|
for word in words.iter() {
|
|
|
|
let _ = transfer_word(regs, *word)?;
|
|
|
|
}
|
|
|
|
|
|
|
|
Ok(())
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
impl<'d, T: Instance> embedded_hal::blocking::spi::Transfer<u8> for Spi<'d, T, NoDma, NoDma> {
|
|
|
|
type Error = Error;
|
|
|
|
|
|
|
|
fn transfer<'w>(&mut self, words: &'w mut [u8]) -> Result<&'w [u8], Self::Error> {
|
|
|
|
self.set_word_size(WordSize::EightBit);
|
|
|
|
let regs = T::regs();
|
|
|
|
|
|
|
|
for word in words.iter_mut() {
|
|
|
|
*word = transfer_word(regs, *word)?;
|
|
|
|
}
|
|
|
|
|
|
|
|
Ok(words)
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
impl<'d, T: Instance> embedded_hal::blocking::spi::Write<u16> for Spi<'d, T, NoDma, NoDma> {
|
|
|
|
type Error = Error;
|
|
|
|
|
|
|
|
fn write(&mut self, words: &[u16]) -> Result<(), Self::Error> {
|
|
|
|
self.set_word_size(WordSize::SixteenBit);
|
|
|
|
let regs = T::regs();
|
|
|
|
|
|
|
|
for word in words.iter() {
|
|
|
|
let _ = transfer_word(regs, *word)?;
|
|
|
|
}
|
|
|
|
|
|
|
|
Ok(())
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
impl<'d, T: Instance> embedded_hal::blocking::spi::Transfer<u16> for Spi<'d, T, NoDma, NoDma> {
|
|
|
|
type Error = Error;
|
|
|
|
|
|
|
|
fn transfer<'w>(&mut self, words: &'w mut [u16]) -> Result<&'w [u16], Self::Error> {
|
|
|
|
self.set_word_size(WordSize::SixteenBit);
|
|
|
|
let regs = T::regs();
|
|
|
|
|
|
|
|
for word in words.iter_mut() {
|
|
|
|
*word = transfer_word(regs, *word)?;
|
|
|
|
}
|
|
|
|
|
|
|
|
Ok(words)
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2021-12-07 05:06:58 +01:00
|
|
|
impl<'d, T: Instance, Tx, Rx> traits::Spi<u8> for Spi<'d, T, Tx, Rx> {
|
|
|
|
type Error = Error;
|
|
|
|
}
|
|
|
|
|
|
|
|
impl<'d, T: Instance, Tx: TxDmaChannel<T>, Rx> traits::Write<u8> for Spi<'d, T, Tx, Rx> {
|
|
|
|
#[rustfmt::skip]
|
|
|
|
type WriteFuture<'a> where Self: 'a = impl Future<Output = Result<(), Self::Error>> + 'a;
|
|
|
|
|
|
|
|
fn write<'a>(&'a mut self, data: &'a [u8]) -> Self::WriteFuture<'a> {
|
|
|
|
self.write_dma_u8(data)
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
impl<'d, T: Instance, Tx: TxDmaChannel<T>, Rx: RxDmaChannel<T>> traits::Read<u8>
|
|
|
|
for Spi<'d, T, Tx, Rx>
|
|
|
|
{
|
|
|
|
#[rustfmt::skip]
|
|
|
|
type ReadFuture<'a> where Self: 'a = impl Future<Output = Result<(), Self::Error>> + 'a;
|
|
|
|
|
|
|
|
fn read<'a>(&'a mut self, data: &'a mut [u8]) -> Self::ReadFuture<'a> {
|
|
|
|
self.read_dma_u8(data)
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
impl<'d, T: Instance, Tx: TxDmaChannel<T>, Rx: RxDmaChannel<T>> traits::FullDuplex<u8>
|
|
|
|
for Spi<'d, T, Tx, Rx>
|
|
|
|
{
|
|
|
|
#[rustfmt::skip]
|
|
|
|
type WriteReadFuture<'a> where Self: 'a = impl Future<Output = Result<(), Self::Error>> + 'a;
|
|
|
|
|
|
|
|
fn read_write<'a>(
|
|
|
|
&'a mut self,
|
|
|
|
read: &'a mut [u8],
|
|
|
|
write: &'a [u8],
|
|
|
|
) -> Self::WriteReadFuture<'a> {
|
|
|
|
self.read_write_dma_u8(read, write)
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2021-05-14 16:11:43 +02:00
|
|
|
pub(crate) mod sealed {
|
|
|
|
use super::*;
|
|
|
|
|
|
|
|
pub trait Instance {
|
|
|
|
fn regs() -> &'static crate::pac::spi::Spi;
|
|
|
|
}
|
|
|
|
|
2021-10-09 22:04:25 +02:00
|
|
|
pub trait SckPin<T: Instance>: OptionalPin {
|
2021-05-15 03:07:37 +02:00
|
|
|
fn af_num(&self) -> u8;
|
2021-05-14 16:11:43 +02:00
|
|
|
}
|
|
|
|
|
2021-10-09 22:04:25 +02:00
|
|
|
pub trait MosiPin<T: Instance>: OptionalPin {
|
2021-05-15 03:07:37 +02:00
|
|
|
fn af_num(&self) -> u8;
|
2021-05-14 16:11:43 +02:00
|
|
|
}
|
|
|
|
|
2021-10-09 22:04:25 +02:00
|
|
|
pub trait MisoPin<T: Instance>: OptionalPin {
|
2021-05-15 03:07:37 +02:00
|
|
|
fn af_num(&self) -> u8;
|
2021-05-14 16:11:43 +02:00
|
|
|
}
|
2021-07-20 15:19:23 +02:00
|
|
|
|
|
|
|
pub trait TxDmaChannel<T: Instance> {
|
|
|
|
fn request(&self) -> dma::Request;
|
|
|
|
}
|
|
|
|
|
|
|
|
pub trait RxDmaChannel<T: Instance> {
|
|
|
|
fn request(&self) -> dma::Request;
|
|
|
|
}
|
2021-05-14 16:11:43 +02:00
|
|
|
}
|
|
|
|
|
2021-07-20 19:38:44 +02:00
|
|
|
pub trait Instance: sealed::Instance + RccPeripheral {}
|
|
|
|
pub trait SckPin<T: Instance>: sealed::SckPin<T> {}
|
|
|
|
pub trait MosiPin<T: Instance>: sealed::MosiPin<T> {}
|
|
|
|
pub trait MisoPin<T: Instance>: sealed::MisoPin<T> {}
|
|
|
|
pub trait TxDmaChannel<T: Instance>: sealed::TxDmaChannel<T> + dma::Channel {}
|
|
|
|
pub trait RxDmaChannel<T: Instance>: sealed::RxDmaChannel<T> + dma::Channel {}
|
2021-07-20 15:19:23 +02:00
|
|
|
|
2021-06-03 17:09:29 +02:00
|
|
|
crate::pac::peripherals!(
|
|
|
|
(spi, $inst:ident) => {
|
|
|
|
impl sealed::Instance for peripherals::$inst {
|
2021-05-14 16:11:43 +02:00
|
|
|
fn regs() -> &'static crate::pac::spi::Spi {
|
|
|
|
&crate::pac::$inst
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2021-06-03 17:09:29 +02:00
|
|
|
impl Instance for peripherals::$inst {}
|
2021-05-14 16:11:43 +02:00
|
|
|
};
|
2021-06-03 17:09:29 +02:00
|
|
|
);
|
2021-05-14 16:11:43 +02:00
|
|
|
|
2021-06-03 17:31:03 +02:00
|
|
|
macro_rules! impl_pin {
|
|
|
|
($inst:ident, $pin:ident, $signal:ident, $af:expr) => {
|
|
|
|
impl $signal<peripherals::$inst> for peripherals::$pin {}
|
2021-05-14 16:11:43 +02:00
|
|
|
|
2021-06-03 17:31:03 +02:00
|
|
|
impl sealed::$signal<peripherals::$inst> for peripherals::$pin {
|
2021-05-15 03:07:37 +02:00
|
|
|
fn af_num(&self) -> u8 {
|
|
|
|
$af
|
|
|
|
}
|
2021-05-14 16:11:43 +02:00
|
|
|
}
|
|
|
|
};
|
2021-06-03 17:31:03 +02:00
|
|
|
}
|
2021-06-03 17:09:29 +02:00
|
|
|
|
2021-10-09 11:35:05 +02:00
|
|
|
#[cfg(not(rcc_f1))]
|
2021-06-03 17:31:03 +02:00
|
|
|
crate::pac::peripheral_pins!(
|
|
|
|
($inst:ident, spi, SPI, $pin:ident, SCK, $af:expr) => {
|
|
|
|
impl_pin!($inst, $pin, SckPin, $af);
|
|
|
|
};
|
2021-06-03 17:09:29 +02:00
|
|
|
|
2021-06-03 17:31:03 +02:00
|
|
|
($inst:ident, spi, SPI, $pin:ident, MOSI, $af:expr) => {
|
|
|
|
impl_pin!($inst, $pin, MosiPin, $af);
|
2021-06-03 17:09:29 +02:00
|
|
|
};
|
|
|
|
|
|
|
|
($inst:ident, spi, SPI, $pin:ident, MISO, $af:expr) => {
|
2021-06-03 17:31:03 +02:00
|
|
|
impl_pin!($inst, $pin, MisoPin, $af);
|
2021-06-03 17:09:29 +02:00
|
|
|
};
|
|
|
|
);
|
2021-07-20 21:44:13 +02:00
|
|
|
|
2021-10-09 11:35:05 +02:00
|
|
|
#[cfg(rcc_f1)]
|
|
|
|
crate::pac::peripheral_pins!(
|
|
|
|
($inst:ident, spi, SPI, $pin:ident, SCK) => {
|
|
|
|
impl_pin!($inst, $pin, SckPin, 0);
|
|
|
|
};
|
|
|
|
|
|
|
|
($inst:ident, spi, SPI, $pin:ident, MOSI) => {
|
|
|
|
impl_pin!($inst, $pin, MosiPin, 0);
|
|
|
|
};
|
|
|
|
|
|
|
|
($inst:ident, spi, SPI, $pin:ident, MISO) => {
|
|
|
|
impl_pin!($inst, $pin, MisoPin, 0);
|
|
|
|
};
|
|
|
|
);
|
|
|
|
|
2021-12-06 21:02:21 +01:00
|
|
|
macro_rules! impl_nopin {
|
|
|
|
($inst:ident, $signal:ident) => {
|
|
|
|
impl $signal<peripherals::$inst> for NoPin {}
|
|
|
|
|
|
|
|
impl sealed::$signal<peripherals::$inst> for NoPin {
|
|
|
|
fn af_num(&self) -> u8 {
|
|
|
|
0
|
|
|
|
}
|
|
|
|
}
|
|
|
|
};
|
|
|
|
}
|
|
|
|
|
|
|
|
crate::pac::peripherals!(
|
|
|
|
(spi, $inst:ident) => {
|
|
|
|
impl_nopin!($inst, SckPin);
|
|
|
|
impl_nopin!($inst, MosiPin);
|
|
|
|
impl_nopin!($inst, MisoPin);
|
|
|
|
};
|
|
|
|
);
|
|
|
|
|
2021-07-20 21:44:13 +02:00
|
|
|
macro_rules! impl_dma {
|
|
|
|
($inst:ident, {dmamux: $dmamux:ident}, $signal:ident, $request:expr) => {
|
|
|
|
impl<T> sealed::$signal<peripherals::$inst> for T
|
|
|
|
where
|
|
|
|
T: crate::dma::MuxChannel<Mux = crate::dma::$dmamux>,
|
|
|
|
{
|
|
|
|
fn request(&self) -> dma::Request {
|
|
|
|
$request
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
impl<T> $signal<peripherals::$inst> for T where
|
|
|
|
T: crate::dma::MuxChannel<Mux = crate::dma::$dmamux>
|
|
|
|
{
|
|
|
|
}
|
|
|
|
};
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|
|
|
($inst:ident, {channel: $channel:ident}, $signal:ident, $request:expr) => {
|
|
|
|
impl sealed::$signal<peripherals::$inst> for peripherals::$channel {
|
|
|
|
fn request(&self) -> dma::Request {
|
|
|
|
$request
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
impl $signal<peripherals::$inst> for peripherals::$channel {}
|
|
|
|
};
|
|
|
|
}
|
|
|
|
|
|
|
|
crate::pac::peripheral_dma_channels! {
|
|
|
|
($peri:ident, spi, $kind:ident, RX, $channel:tt, $request:expr) => {
|
|
|
|
impl_dma!($peri, $channel, RxDmaChannel, $request);
|
|
|
|
};
|
|
|
|
($peri:ident, spi, $kind:ident, TX, $channel:tt, $request:expr) => {
|
|
|
|
impl_dma!($peri, $channel, TxDmaChannel, $request);
|
|
|
|
};
|
|
|
|
}
|