Unify blocking trait impls
This commit is contained in:
Grant Miller
parent
3a17e3a2a5
commit
bf1f80afa1
@ -1,6 +1,7 @@
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#![macro_use]
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use crate::dma;
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use crate::dma::NoDma;
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use crate::gpio::sealed::{AFType, Pin};
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use crate::gpio::{AnyPin, NoPin, OptionalPin};
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use crate::pac::spi::{regs, vals};
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@ -9,6 +10,7 @@ use crate::rcc::RccPeripheral;
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use crate::time::Hertz;
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use core::future::Future;
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use core::marker::PhantomData;
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use core::ptr;
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use embassy::util::Unborrow;
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use embassy_hal_common::unborrow;
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use embassy_traits::spi as traits;
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@ -403,11 +405,121 @@ fn check_error_flags(sr: regs::Sr) -> Result<(), Error> {
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Ok(())
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}
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fn spin_until_tx_ready(regs: &'static crate::pac::spi::Spi) -> Result<(), Error> {
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loop {
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let sr = unsafe { regs.sr().read() };
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check_error_flags(sr)?;
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#[cfg(not(spi_v3))]
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if sr.txe() {
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return Ok(());
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}
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#[cfg(spi_v3)]
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if sr.txp() {
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return Ok(());
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}
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}
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}
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fn spin_until_rx_ready(regs: &'static crate::pac::spi::Spi) -> Result<(), Error> {
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loop {
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let sr = unsafe { regs.sr().read() };
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check_error_flags(sr)?;
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#[cfg(not(spi_v3))]
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if sr.rxne() {
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return Ok(());
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}
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#[cfg(spi_v3)]
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if sr.rxp() {
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return Ok(());
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}
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}
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}
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trait Word {}
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impl Word for u8 {}
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impl Word for u16 {}
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fn transfer_word<W: Word>(regs: &'static crate::pac::spi::Spi, tx_word: W) -> Result<W, Error> {
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spin_until_tx_ready(regs)?;
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unsafe {
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ptr::write_volatile(regs.tx_ptr(), tx_word);
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#[cfg(spi_v3)]
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regs.cr1().modify(|reg| reg.set_cstart(true));
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}
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spin_until_rx_ready(regs)?;
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let rx_word = unsafe { ptr::read_volatile(regs.rx_ptr()) };
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return Ok(rx_word);
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}
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impl<'d, T: Instance> embedded_hal::blocking::spi::Write<u8> for Spi<'d, T, NoDma, NoDma> {
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type Error = Error;
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fn write(&mut self, words: &[u8]) -> Result<(), Self::Error> {
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self.set_word_size(WordSize::EightBit);
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let regs = T::regs();
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for word in words.iter() {
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let _ = transfer_word(regs, *word)?;
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}
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Ok(())
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}
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}
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impl<'d, T: Instance> embedded_hal::blocking::spi::Transfer<u8> for Spi<'d, T, NoDma, NoDma> {
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type Error = Error;
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fn transfer<'w>(&mut self, words: &'w mut [u8]) -> Result<&'w [u8], Self::Error> {
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self.set_word_size(WordSize::EightBit);
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let regs = T::regs();
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for word in words.iter_mut() {
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*word = transfer_word(regs, *word)?;
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}
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Ok(words)
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}
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}
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impl<'d, T: Instance> embedded_hal::blocking::spi::Write<u16> for Spi<'d, T, NoDma, NoDma> {
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type Error = Error;
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fn write(&mut self, words: &[u16]) -> Result<(), Self::Error> {
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self.set_word_size(WordSize::SixteenBit);
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let regs = T::regs();
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for word in words.iter() {
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let _ = transfer_word(regs, *word)?;
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}
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Ok(())
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}
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}
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impl<'d, T: Instance> embedded_hal::blocking::spi::Transfer<u16> for Spi<'d, T, NoDma, NoDma> {
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type Error = Error;
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fn transfer<'w>(&mut self, words: &'w mut [u16]) -> Result<&'w [u16], Self::Error> {
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self.set_word_size(WordSize::SixteenBit);
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let regs = T::regs();
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for word in words.iter_mut() {
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*word = transfer_word(regs, *word)?;
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}
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Ok(words)
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}
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}
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impl<'d, T: Instance, Tx, Rx> traits::Spi<u8> for Spi<'d, T, Tx, Rx> {
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type Error = Error;
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}
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@ -1,15 +1,10 @@
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#![macro_use]
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use crate::dma::NoDma;
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use crate::spi::{
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check_error_flags, Error, Instance, RegsExt, RxDmaChannel, TxDmaChannel, WordSize,
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};
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use core::ptr;
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pub use embedded_hal::blocking;
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pub use embedded_hal::spi::{Mode, Phase, Polarity, MODE_0, MODE_1, MODE_2, MODE_3};
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use futures::future::join3;
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use super::Spi;
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use super::*;
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impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
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pub(super) async fn write_dma_u8(&mut self, write: &[u8]) -> Result<(), Error>
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@ -155,99 +150,3 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
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}
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}
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}
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impl<'d, T: Instance> embedded_hal::blocking::spi::Write<u8> for Spi<'d, T, NoDma, NoDma> {
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type Error = Error;
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fn write(&mut self, words: &[u8]) -> Result<(), Self::Error> {
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self.set_word_size(WordSize::EightBit);
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let regs = T::regs();
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for word in words.iter() {
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write_word(regs, *word)?;
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let _: u8 = read_word(regs)?;
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}
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Ok(())
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}
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}
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impl<'d, T: Instance> embedded_hal::blocking::spi::Transfer<u8> for Spi<'d, T, NoDma, NoDma> {
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type Error = Error;
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fn transfer<'w>(&mut self, words: &'w mut [u8]) -> Result<&'w [u8], Self::Error> {
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self.set_word_size(WordSize::EightBit);
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let regs = T::regs();
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for word in words.iter_mut() {
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write_word(regs, *word)?;
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*word = read_word(regs)?;
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}
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Ok(words)
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}
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}
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impl<'d, T: Instance> embedded_hal::blocking::spi::Write<u16> for Spi<'d, T, NoDma, NoDma> {
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type Error = Error;
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fn write(&mut self, words: &[u16]) -> Result<(), Self::Error> {
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self.set_word_size(WordSize::SixteenBit);
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let regs = T::regs();
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for word in words.iter() {
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write_word(regs, *word)?;
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let _: u8 = read_word(regs)?;
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}
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Ok(())
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}
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}
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impl<'d, T: Instance> embedded_hal::blocking::spi::Transfer<u16> for Spi<'d, T, NoDma, NoDma> {
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type Error = Error;
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fn transfer<'w>(&mut self, words: &'w mut [u16]) -> Result<&'w [u16], Self::Error> {
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self.set_word_size(WordSize::SixteenBit);
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let regs = T::regs();
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for word in words.iter_mut() {
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write_word(regs, *word)?;
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*word = read_word(regs)?;
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}
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Ok(words)
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}
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}
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use super::Word;
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fn write_word<W: Word>(regs: &'static crate::pac::spi::Spi, word: W) -> Result<(), Error> {
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loop {
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let sr = unsafe { regs.sr().read() };
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check_error_flags(sr)?;
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if sr.txe() {
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unsafe {
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ptr::write_volatile(regs.tx_ptr(), word);
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}
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return Ok(());
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}
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}
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}
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/// Read a single word blocking. Assumes word size have already been set.
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fn read_word<W: Word>(regs: &'static crate::pac::spi::Spi) -> Result<W, Error> {
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loop {
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let sr = unsafe { regs.sr().read() };
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check_error_flags(sr)?;
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if sr.rxne() {
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unsafe {
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return Ok(ptr::read_volatile(regs.rx_ptr()));
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}
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}
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}
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}
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@ -1,14 +1,9 @@
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#![macro_use]
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use crate::dma::NoDma;
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use crate::spi::{
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check_error_flags, Error, Instance, RegsExt, RxDmaChannel, TxDmaChannel, WordSize,
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};
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use core::ptr;
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pub use embedded_hal::spi::{Mode, Phase, Polarity, MODE_0, MODE_1, MODE_2, MODE_3};
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use futures::future::{join, join3};
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use super::Spi;
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use super::*;
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impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
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pub(super) async fn write_dma_u8(&mut self, write: &[u8]) -> Result<(), Error>
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@ -100,7 +95,11 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
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Ok(())
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}
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pub(super) async fn read_write_dma_u8(&mut self, read: &mut [u8], write: &[u8]) -> Result<(), Error>
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pub(super) async fn read_write_dma_u8(
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&mut self,
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read: &mut [u8],
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write: &[u8],
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) -> Result<(), Error>
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where
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Tx: TxDmaChannel<T>,
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Rx: RxDmaChannel<T>,
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@ -170,100 +169,3 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
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}
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}
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}
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use super::Word;
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/// Write a single word blocking. Assumes word size have already been set.
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fn write_word<W: Word>(regs: &'static crate::pac::spi::Spi, word: W) -> Result<(), Error> {
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loop {
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let sr = unsafe { regs.sr().read() };
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check_error_flags(sr)?;
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if sr.txe() {
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unsafe {
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ptr::write_volatile(regs.tx_ptr(), word);
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}
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return Ok(());
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}
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}
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}
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/// Read a single word blocking. Assumes word size have already been set.
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fn read_word<W: Word>(regs: &'static crate::pac::spi::Spi) -> Result<W, Error> {
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loop {
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let sr = unsafe { regs.sr().read() };
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check_error_flags(sr)?;
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if sr.rxne() {
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unsafe {
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return Ok(ptr::read_volatile(regs.rx_ptr()));
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}
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}
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}
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}
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impl<'d, T: Instance, Rx> embedded_hal::blocking::spi::Write<u8> for Spi<'d, T, NoDma, Rx> {
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type Error = Error;
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fn write(&mut self, words: &[u8]) -> Result<(), Self::Error> {
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self.set_word_size(WordSize::EightBit);
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let regs = T::regs();
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for word in words.iter() {
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write_word(regs, *word)?;
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let _: u8 = read_word(regs)?;
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}
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Ok(())
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}
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}
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impl<'d, T: Instance> embedded_hal::blocking::spi::Transfer<u8> for Spi<'d, T, NoDma, NoDma> {
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type Error = Error;
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fn transfer<'w>(&mut self, words: &'w mut [u8]) -> Result<&'w [u8], Self::Error> {
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self.set_word_size(WordSize::EightBit);
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let regs = T::regs();
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for word in words.iter_mut() {
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write_word(regs, *word)?;
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*word = read_word(regs)?;
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}
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Ok(words)
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}
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}
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impl<'d, T: Instance, Rx> embedded_hal::blocking::spi::Write<u16> for Spi<'d, T, NoDma, Rx> {
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type Error = Error;
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fn write(&mut self, words: &[u16]) -> Result<(), Self::Error> {
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self.set_word_size(WordSize::SixteenBit);
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let regs = T::regs();
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for word in words.iter() {
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write_word(regs, *word)?;
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let _: u16 = read_word(regs)?;
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}
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Ok(())
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}
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}
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impl<'d, T: Instance> embedded_hal::blocking::spi::Transfer<u16> for Spi<'d, T, NoDma, NoDma> {
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type Error = Error;
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fn transfer<'w>(&mut self, words: &'w mut [u16]) -> Result<&'w [u16], Self::Error> {
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self.set_word_size(WordSize::SixteenBit);
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let regs = T::regs();
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for word in words.iter_mut() {
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write_word(regs, *word)?;
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*word = read_word(regs)?;
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}
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Ok(words)
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}
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}
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@ -1,15 +1,9 @@
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#![macro_use]
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use crate::dma::NoDma;
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use crate::spi::{
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check_error_flags, Error, Instance, RegsExt, RxDmaChannel, TxDmaChannel, WordSize,
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};
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use core::ptr;
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pub use embedded_hal::spi::{Mode, Phase, Polarity, MODE_0, MODE_1, MODE_2, MODE_3};
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use futures::future::join3;
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use super::Spi;
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use super::*;
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impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
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pub(super) async fn write_dma_u8(&mut self, write: &[u8]) -> Result<(), Error>
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@ -105,7 +99,11 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
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Ok(())
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}
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pub(super) async fn read_write_dma_u8(&mut self, read: &mut [u8], write: &[u8]) -> Result<(), Error>
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pub(super) async fn read_write_dma_u8(
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&mut self,
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read: &mut [u8],
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write: &[u8],
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) -> Result<(), Error>
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where
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Tx: TxDmaChannel<T>,
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Rx: RxDmaChannel<T>,
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@ -173,171 +171,3 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
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}
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}
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}
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impl<'d, T: Instance> embedded_hal::blocking::spi::Write<u8> for Spi<'d, T, NoDma, NoDma> {
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type Error = Error;
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fn write(&mut self, words: &[u8]) -> Result<(), Self::Error> {
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self.set_word_size(WordSize::EightBit);
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let regs = T::regs();
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for word in words.iter() {
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while unsafe { !regs.sr().read().txp() } {
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// spin
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}
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unsafe {
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ptr::write_volatile(regs.tx_ptr(), *word);
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regs.cr1().modify(|reg| reg.set_cstart(true));
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}
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loop {
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let sr = unsafe { regs.sr().read() };
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if sr.tifre() {
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return Err(Error::Framing);
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}
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if sr.ovr() {
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return Err(Error::Overrun);
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}
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if sr.crce() {
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return Err(Error::Crc);
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}
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if !sr.txp() {
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// loop waiting for TXE
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continue;
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}
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break;
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}
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unsafe {
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// discard read to prevent pverrun.
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let _: u8 = ptr::read_volatile(T::regs().rx_ptr());
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}
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}
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while unsafe { !regs.sr().read().txc() } {
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// spin
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}
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Ok(())
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}
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}
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impl<'d, T: Instance> embedded_hal::blocking::spi::Transfer<u8> for Spi<'d, T, NoDma, NoDma> {
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type Error = Error;
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fn transfer<'w>(&mut self, words: &'w mut [u8]) -> Result<&'w [u8], Self::Error> {
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self.set_word_size(WordSize::EightBit);
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let regs = T::regs();
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for word in words.iter_mut() {
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unsafe {
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regs.cr1().modify(|reg| {
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reg.set_ssi(false);
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});
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}
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while unsafe { !regs.sr().read().txp() } {
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// spin
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}
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unsafe {
|
||||
ptr::write_volatile(T::regs().tx_ptr(), *word);
|
||||
regs.cr1().modify(|reg| reg.set_cstart(true));
|
||||
}
|
||||
loop {
|
||||
let sr = unsafe { regs.sr().read() };
|
||||
|
||||
if sr.rxp() {
|
||||
break;
|
||||
}
|
||||
|
||||
check_error_flags(sr)?;
|
||||
}
|
||||
unsafe {
|
||||
*word = ptr::read_volatile(T::regs().rx_ptr());
|
||||
}
|
||||
let sr = unsafe { regs.sr().read() };
|
||||
check_error_flags(sr)?;
|
||||
}
|
||||
|
||||
Ok(words)
|
||||
}
|
||||
}
|
||||
|
||||
impl<'d, T: Instance> embedded_hal::blocking::spi::Write<u16> for Spi<'d, T, NoDma, NoDma> {
|
||||
type Error = Error;
|
||||
|
||||
fn write(&mut self, words: &[u16]) -> Result<(), Self::Error> {
|
||||
self.set_word_size(WordSize::SixteenBit);
|
||||
let regs = T::regs();
|
||||
|
||||
for word in words.iter() {
|
||||
while unsafe { !regs.sr().read().txp() } {
|
||||
// spin
|
||||
}
|
||||
unsafe {
|
||||
let txdr = regs.txdr().ptr() as *mut u16;
|
||||
ptr::write_volatile(txdr, *word);
|
||||
regs.cr1().modify(|reg| reg.set_cstart(true));
|
||||
}
|
||||
loop {
|
||||
let sr = unsafe { regs.sr().read() };
|
||||
|
||||
check_error_flags(sr)?;
|
||||
|
||||
if !sr.txp() {
|
||||
// loop waiting for TXE
|
||||
continue;
|
||||
}
|
||||
break;
|
||||
}
|
||||
|
||||
unsafe {
|
||||
let rxdr = regs.rxdr().ptr() as *const u8;
|
||||
// discard read to prevent pverrun.
|
||||
let _ = ptr::read_volatile(rxdr);
|
||||
}
|
||||
}
|
||||
|
||||
while unsafe { !regs.sr().read().txc() } {
|
||||
// spin
|
||||
}
|
||||
|
||||
Ok(())
|
||||
}
|
||||
}
|
||||
|
||||
impl<'d, T: Instance> embedded_hal::blocking::spi::Transfer<u16> for Spi<'d, T, NoDma, NoDma> {
|
||||
type Error = Error;
|
||||
|
||||
fn transfer<'w>(&mut self, words: &'w mut [u16]) -> Result<&'w [u16], Self::Error> {
|
||||
self.set_word_size(WordSize::SixteenBit);
|
||||
let regs = T::regs();
|
||||
|
||||
for word in words.iter_mut() {
|
||||
while unsafe { !regs.sr().read().txp() } {
|
||||
// spin
|
||||
}
|
||||
unsafe {
|
||||
let txdr = regs.txdr().ptr() as *mut u16;
|
||||
ptr::write_volatile(txdr, *word);
|
||||
regs.cr1().modify(|reg| reg.set_cstart(true));
|
||||
}
|
||||
|
||||
loop {
|
||||
let sr = unsafe { regs.sr().read() };
|
||||
|
||||
if sr.rxp() {
|
||||
break;
|
||||
}
|
||||
|
||||
check_error_flags(sr)?;
|
||||
}
|
||||
|
||||
unsafe {
|
||||
let rxdr = regs.rxdr().ptr() as *const u16;
|
||||
*word = ptr::read_volatile(rxdr);
|
||||
}
|
||||
let sr = unsafe { regs.sr().read() };
|
||||
check_error_flags(sr)?;
|
||||
}
|
||||
|
||||
Ok(words)
|
||||
}
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user