2023-05-31 01:01:30 +02:00
|
|
|
use embedded_hal_async::spi::SpiDevice;
|
|
|
|
|
2023-05-09 01:51:08 +02:00
|
|
|
use crate::socket;
|
2023-08-15 17:11:24 +02:00
|
|
|
use crate::spi::{Address, SpiInterface};
|
2023-05-09 01:51:08 +02:00
|
|
|
|
2023-08-15 17:11:24 +02:00
|
|
|
pub const MODE: Address = (RegisterBlock::Common, 0x00);
|
|
|
|
pub const MAC: Address = (RegisterBlock::Common, 0x09);
|
|
|
|
pub const SOCKET_INTR: Address = (RegisterBlock::Common, 0x18);
|
|
|
|
pub const PHY_CFG: Address = (RegisterBlock::Common, 0x2E);
|
2023-05-09 01:51:08 +02:00
|
|
|
|
|
|
|
#[repr(u8)]
|
|
|
|
pub enum RegisterBlock {
|
|
|
|
Common = 0x00,
|
|
|
|
Socket0 = 0x01,
|
|
|
|
TxBuf = 0x02,
|
|
|
|
RxBuf = 0x03,
|
|
|
|
}
|
|
|
|
|
|
|
|
/// W5500 in MACRAW mode
|
|
|
|
#[derive(Debug)]
|
|
|
|
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
|
|
|
|
pub struct W5500<SPI> {
|
|
|
|
bus: SpiInterface<SPI>,
|
|
|
|
}
|
|
|
|
|
|
|
|
impl<SPI: SpiDevice> W5500<SPI> {
|
|
|
|
/// Create and initialize the W5500 driver
|
|
|
|
pub async fn new(spi: SPI, mac_addr: [u8; 6]) -> Result<W5500<SPI>, SPI::Error> {
|
|
|
|
let mut bus = SpiInterface(spi);
|
|
|
|
// Reset device
|
2023-08-15 17:11:24 +02:00
|
|
|
bus.write_frame(MODE, &[0x80]).await?;
|
2023-05-09 01:51:08 +02:00
|
|
|
|
|
|
|
// Enable interrupt pin
|
2023-08-15 17:11:24 +02:00
|
|
|
bus.write_frame(SOCKET_INTR, &[0x01]).await?;
|
2023-05-09 01:51:08 +02:00
|
|
|
// Enable receive interrupt
|
2023-08-15 17:11:24 +02:00
|
|
|
bus.write_frame(socket::SOCKET_INTR_MASK, &[socket::Interrupt::Receive as u8])
|
|
|
|
.await?;
|
2023-05-09 01:51:08 +02:00
|
|
|
|
|
|
|
// Set MAC address
|
2023-08-15 17:11:24 +02:00
|
|
|
bus.write_frame(MAC, &mac_addr).await?;
|
2023-05-09 01:51:08 +02:00
|
|
|
|
|
|
|
// Set the raw socket RX/TX buffer sizes to 16KB
|
2023-08-15 17:11:24 +02:00
|
|
|
bus.write_frame(socket::TXBUF_SIZE, &[16]).await?;
|
|
|
|
bus.write_frame(socket::RXBUF_SIZE, &[16]).await?;
|
2023-05-09 01:51:08 +02:00
|
|
|
|
|
|
|
// MACRAW mode with MAC filtering.
|
|
|
|
let mode: u8 = (1 << 2) | (1 << 7);
|
2023-08-15 17:11:24 +02:00
|
|
|
bus.write_frame(socket::MODE, &[mode]).await?;
|
2023-05-09 01:51:08 +02:00
|
|
|
socket::command(&mut bus, socket::Command::Open).await?;
|
|
|
|
|
|
|
|
Ok(Self { bus })
|
|
|
|
}
|
|
|
|
|
|
|
|
/// Read bytes from the RX buffer. Returns the number of bytes read.
|
2023-08-15 16:47:45 +02:00
|
|
|
async fn read_bytes(&mut self, read_ptr: &mut u16, buffer: &mut [u8]) -> Result<(), SPI::Error> {
|
2023-08-15 17:11:24 +02:00
|
|
|
self.bus.read_frame((RegisterBlock::RxBuf, *read_ptr), buffer).await?;
|
2023-08-15 16:47:45 +02:00
|
|
|
*read_ptr = (*read_ptr).wrapping_add(buffer.len() as u16);
|
2023-05-09 01:51:08 +02:00
|
|
|
|
2023-08-15 16:47:45 +02:00
|
|
|
Ok(())
|
2023-05-09 01:51:08 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
/// Read an ethernet frame from the device. Returns the number of bytes read.
|
|
|
|
pub async fn read_frame(&mut self, frame: &mut [u8]) -> Result<usize, SPI::Error> {
|
|
|
|
let rx_size = socket::get_rx_size(&mut self.bus).await? as usize;
|
|
|
|
if rx_size == 0 {
|
|
|
|
return Ok(0);
|
|
|
|
}
|
|
|
|
|
|
|
|
socket::reset_interrupt(&mut self.bus, socket::Interrupt::Receive).await?;
|
|
|
|
|
2023-08-15 16:47:45 +02:00
|
|
|
let mut read_ptr = socket::get_rx_read_ptr(&mut self.bus).await?;
|
|
|
|
|
2023-05-09 01:51:08 +02:00
|
|
|
// First two bytes gives the size of the received ethernet frame
|
|
|
|
let expected_frame_size: usize = {
|
|
|
|
let mut frame_bytes = [0u8; 2];
|
2023-08-15 16:47:45 +02:00
|
|
|
self.read_bytes(&mut read_ptr, &mut frame_bytes).await?;
|
2023-05-09 01:51:08 +02:00
|
|
|
u16::from_be_bytes(frame_bytes) as usize - 2
|
|
|
|
};
|
|
|
|
|
|
|
|
// Read the ethernet frame
|
2023-08-15 16:47:45 +02:00
|
|
|
self.read_bytes(&mut read_ptr, &mut frame[..expected_frame_size])
|
|
|
|
.await?;
|
2023-05-09 01:51:08 +02:00
|
|
|
|
|
|
|
// Register RX as completed
|
2023-08-15 16:47:45 +02:00
|
|
|
socket::set_rx_read_ptr(&mut self.bus, read_ptr).await?;
|
2023-05-09 01:51:08 +02:00
|
|
|
socket::command(&mut self.bus, socket::Command::Receive).await?;
|
|
|
|
|
2023-08-15 16:47:45 +02:00
|
|
|
Ok(expected_frame_size)
|
2023-05-09 01:51:08 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
/// Write an ethernet frame to the device. Returns number of bytes written
|
|
|
|
pub async fn write_frame(&mut self, frame: &[u8]) -> Result<usize, SPI::Error> {
|
2023-05-13 06:34:03 +02:00
|
|
|
while socket::get_tx_free_size(&mut self.bus).await? < frame.len() as u16 {}
|
2023-05-09 01:51:08 +02:00
|
|
|
let write_ptr = socket::get_tx_write_ptr(&mut self.bus).await?;
|
2023-08-15 17:11:24 +02:00
|
|
|
self.bus.write_frame((RegisterBlock::TxBuf, write_ptr), frame).await?;
|
2023-05-13 06:34:03 +02:00
|
|
|
socket::set_tx_write_ptr(&mut self.bus, write_ptr.wrapping_add(frame.len() as u16)).await?;
|
2023-05-09 01:51:08 +02:00
|
|
|
socket::command(&mut self.bus, socket::Command::Send).await?;
|
2023-05-13 06:34:03 +02:00
|
|
|
Ok(frame.len())
|
2023-05-09 01:51:08 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
pub async fn is_link_up(&mut self) -> bool {
|
|
|
|
let mut link = [0];
|
2023-08-15 17:11:24 +02:00
|
|
|
self.bus.read_frame(PHY_CFG, &mut link).await.ok();
|
2023-05-09 01:51:08 +02:00
|
|
|
link[0] & 1 == 1
|
|
|
|
}
|
|
|
|
}
|