2023-07-28 16:34:20 +02:00
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#![no_std]
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#![no_main]
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#![feature(type_alias_impl_trait)]
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use defmt::*;
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use embassy_executor::Spawner;
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2023-11-21 04:12:36 +01:00
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use embassy_stm32::dac::{DacCh1, DacCh2, ValueArray};
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2023-07-28 16:34:20 +02:00
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use embassy_stm32::pac::timer::vals::{Mms, Opm};
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2023-11-21 04:12:36 +01:00
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use embassy_stm32::peripherals::{DAC1, DMA1_CH3, DMA1_CH4, TIM6, TIM7};
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2023-07-28 16:34:20 +02:00
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use embassy_stm32::rcc::low_level::RccPeripheral;
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2023-09-19 04:22:57 +02:00
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use embassy_stm32::time::Hertz;
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2023-07-28 16:34:20 +02:00
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use embassy_stm32::timer::low_level::Basic16bitInstance;
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use micromath::F32Ext;
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use {defmt_rtt as _, panic_probe as _};
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#[embassy_executor::main]
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async fn main(spawner: Spawner) {
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let mut config = embassy_stm32::Config::default();
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2023-09-19 04:22:57 +02:00
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{
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use embassy_stm32::rcc::*;
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2023-10-23 01:48:09 +02:00
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config.rcc.hsi = Some(HSIPrescaler::DIV1);
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2023-09-19 04:22:57 +02:00
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config.rcc.csi = true;
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config.rcc.pll1 = Some(Pll {
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2023-10-23 01:48:09 +02:00
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source: PllSource::HSI,
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2023-10-09 02:48:22 +02:00
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prediv: PllPreDiv::DIV4,
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mul: PllMul::MUL50,
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divp: Some(PllDiv::DIV2),
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divq: Some(PllDiv::DIV8), // 100mhz
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2023-09-19 04:22:57 +02:00
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divr: None,
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});
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config.rcc.pll2 = Some(Pll {
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2023-10-23 01:48:09 +02:00
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source: PllSource::HSI,
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2023-10-09 02:48:22 +02:00
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prediv: PllPreDiv::DIV4,
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mul: PllMul::MUL50,
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divp: Some(PllDiv::DIV8), // 100mhz
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2023-09-19 04:22:57 +02:00
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divq: None,
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divr: None,
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});
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2023-10-23 01:48:09 +02:00
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config.rcc.sys = Sysclk::PLL1_P; // 400 Mhz
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2023-09-19 04:22:57 +02:00
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config.rcc.ahb_pre = AHBPrescaler::DIV2; // 200 Mhz
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config.rcc.apb1_pre = APBPrescaler::DIV2; // 100 Mhz
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config.rcc.apb2_pre = APBPrescaler::DIV2; // 100 Mhz
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config.rcc.apb3_pre = APBPrescaler::DIV2; // 100 Mhz
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config.rcc.apb4_pre = APBPrescaler::DIV2; // 100 Mhz
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config.rcc.voltage_scale = VoltageScale::Scale1;
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config.rcc.adc_clock_source = AdcClockSource::PLL2_P;
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}
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2023-07-28 16:34:20 +02:00
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// Initialize the board and obtain a Peripherals instance
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let p: embassy_stm32::Peripherals = embassy_stm32::init(config);
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// Obtain two independent channels (p.DAC1 can only be consumed once, though!)
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let (dac_ch1, dac_ch2) = embassy_stm32::dac::Dac::new(p.DAC1, p.DMA1_CH3, p.DMA1_CH4, p.PA4, p.PA5).split();
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spawner.spawn(dac_task1(dac_ch1)).ok();
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spawner.spawn(dac_task2(dac_ch2)).ok();
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}
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#[embassy_executor::task]
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2023-11-21 04:12:36 +01:00
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async fn dac_task1(mut dac: DacCh1<'static, DAC1, DMA1_CH3>) {
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2023-07-28 16:34:20 +02:00
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let data: &[u8; 256] = &calculate_array::<256>();
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info!("TIM6 frequency is {}", TIM6::frequency());
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const FREQUENCY: Hertz = Hertz::hz(200);
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// Compute the reload value such that we obtain the FREQUENCY for the sine
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let reload: u32 = (TIM6::frequency().0 / FREQUENCY.0) / data.len() as u32;
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// Depends on your clock and on the specific chip used, you may need higher or lower values here
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if reload < 10 {
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error!("Reload value {} below threshold!", reload);
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}
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2023-11-21 04:12:36 +01:00
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dac.set_trigger(embassy_stm32::dac::TriggerSel::Tim6);
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dac.set_triggering(true);
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dac.enable();
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2023-07-28 16:34:20 +02:00
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2023-10-11 21:38:41 +02:00
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TIM6::enable_and_reset();
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2023-07-28 16:34:20 +02:00
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TIM6::regs().arr().modify(|w| w.set_arr(reload as u16 - 1));
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TIM6::regs().cr2().modify(|w| w.set_mms(Mms::UPDATE));
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TIM6::regs().cr1().modify(|w| {
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w.set_opm(Opm::DISABLED);
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w.set_cen(true);
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});
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debug!(
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"TIM6 Frequency {}, Target Frequency {}, Reload {}, Reload as u16 {}, Samples {}",
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TIM6::frequency(),
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FREQUENCY,
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reload,
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reload as u16,
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data.len()
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);
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// Loop technically not necessary if DMA circular mode is enabled
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loop {
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info!("Loop DAC1");
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2023-11-21 04:12:36 +01:00
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dac.write(ValueArray::Bit8(data), true).await;
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2023-07-28 16:34:20 +02:00
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}
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}
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#[embassy_executor::task]
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2023-11-21 04:12:36 +01:00
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async fn dac_task2(mut dac: DacCh2<'static, DAC1, DMA1_CH4>) {
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2023-07-28 16:34:20 +02:00
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let data: &[u8; 256] = &calculate_array::<256>();
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info!("TIM7 frequency is {}", TIM7::frequency());
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const FREQUENCY: Hertz = Hertz::hz(600);
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let reload: u32 = (TIM7::frequency().0 / FREQUENCY.0) / data.len() as u32;
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if reload < 10 {
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error!("Reload value {} below threshold!", reload);
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}
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2023-10-11 21:38:41 +02:00
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TIM7::enable_and_reset();
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2023-07-28 16:34:20 +02:00
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TIM7::regs().arr().modify(|w| w.set_arr(reload as u16 - 1));
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TIM7::regs().cr2().modify(|w| w.set_mms(Mms::UPDATE));
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TIM7::regs().cr1().modify(|w| {
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w.set_opm(Opm::DISABLED);
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w.set_cen(true);
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});
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2023-11-21 04:12:36 +01:00
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dac.set_trigger(embassy_stm32::dac::TriggerSel::Tim7);
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dac.set_triggering(true);
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dac.enable();
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2023-07-28 16:34:20 +02:00
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debug!(
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"TIM7 Frequency {}, Target Frequency {}, Reload {}, Reload as u16 {}, Samples {}",
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TIM7::frequency(),
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FREQUENCY,
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reload,
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reload as u16,
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data.len()
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);
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2023-11-21 04:12:36 +01:00
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dac.write(ValueArray::Bit8(data), true).await;
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2023-07-28 16:34:20 +02:00
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}
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fn to_sine_wave(v: u8) -> u8 {
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if v >= 128 {
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// top half
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let r = 3.14 * ((v - 128) as f32 / 128.0);
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(r.sin() * 128.0 + 127.0) as u8
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} else {
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// bottom half
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let r = 3.14 + 3.14 * (v as f32 / 128.0);
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(r.sin() * 128.0 + 127.0) as u8
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}
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}
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fn calculate_array<const N: usize>() -> [u8; N] {
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let mut res = [0; N];
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let mut i = 0;
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while i < N {
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res[i] = to_sine_wave(i as u8);
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i += 1;
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}
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res
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}
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