2022-08-04 02:02:57 +02:00
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#![macro_use]
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use cfg_if::cfg_if;
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2022-07-23 14:00:19 +02:00
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use embassy_hal_common::{into_ref, PeripheralRef};
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2022-06-12 22:15:44 +02:00
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2021-05-28 19:31:40 +02:00
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use crate::pac::dac;
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2022-08-04 02:02:57 +02:00
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use crate::{peripherals, Peripheral};
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2021-05-28 19:31:40 +02:00
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2022-02-10 02:34:59 +01:00
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#[derive(Debug, Copy, Clone, Eq, PartialEq)]
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2021-06-07 13:51:06 +02:00
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#[cfg_attr(feature = "defmt", derive(defmt::Format))]
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2021-05-28 19:31:40 +02:00
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pub enum Error {
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UnconfiguredChannel,
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InvalidValue,
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}
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2022-02-10 02:34:59 +01:00
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#[derive(Debug, Copy, Clone, Eq, PartialEq)]
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#[cfg_attr(feature = "defmt", derive(defmt::Format))]
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2021-05-28 19:31:40 +02:00
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pub enum Channel {
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Ch1,
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Ch2,
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}
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2022-08-04 02:02:57 +02:00
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impl Channel {
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fn index(&self) -> usize {
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match self {
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Channel::Ch1 => 0,
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Channel::Ch2 => 1,
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}
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}
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}
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2022-02-10 02:34:59 +01:00
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#[derive(Debug, Copy, Clone, Eq, PartialEq)]
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#[cfg_attr(feature = "defmt", derive(defmt::Format))]
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2021-05-28 19:31:40 +02:00
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pub enum Ch1Trigger {
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Tim6,
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Tim3,
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Tim7,
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Tim15,
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Tim2,
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Exti9,
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Software,
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}
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impl Ch1Trigger {
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fn tsel(&self) -> dac::vals::Tsel1 {
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match self {
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Ch1Trigger::Tim6 => dac::vals::Tsel1::TIM6_TRGO,
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Ch1Trigger::Tim3 => dac::vals::Tsel1::TIM3_TRGO,
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Ch1Trigger::Tim7 => dac::vals::Tsel1::TIM7_TRGO,
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Ch1Trigger::Tim15 => dac::vals::Tsel1::TIM15_TRGO,
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Ch1Trigger::Tim2 => dac::vals::Tsel1::TIM2_TRGO,
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Ch1Trigger::Exti9 => dac::vals::Tsel1::EXTI9,
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Ch1Trigger::Software => dac::vals::Tsel1::SOFTWARE,
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}
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}
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}
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2022-02-10 02:34:59 +01:00
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#[derive(Debug, Copy, Clone, Eq, PartialEq)]
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#[cfg_attr(feature = "defmt", derive(defmt::Format))]
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2021-05-28 19:31:40 +02:00
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pub enum Ch2Trigger {
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Tim6,
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Tim8,
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Tim7,
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Tim5,
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Tim2,
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Tim4,
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Exti9,
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Software,
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}
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impl Ch2Trigger {
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fn tsel(&self) -> dac::vals::Tsel2 {
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match self {
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Ch2Trigger::Tim6 => dac::vals::Tsel2::TIM6_TRGO,
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Ch2Trigger::Tim8 => dac::vals::Tsel2::TIM8_TRGO,
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Ch2Trigger::Tim7 => dac::vals::Tsel2::TIM7_TRGO,
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Ch2Trigger::Tim5 => dac::vals::Tsel2::TIM5_TRGO,
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Ch2Trigger::Tim2 => dac::vals::Tsel2::TIM2_TRGO,
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Ch2Trigger::Tim4 => dac::vals::Tsel2::TIM4_TRGO,
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Ch2Trigger::Exti9 => dac::vals::Tsel2::EXTI9,
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Ch2Trigger::Software => dac::vals::Tsel2::SOFTWARE,
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}
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}
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}
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2022-02-10 02:34:59 +01:00
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#[derive(Debug, Copy, Clone, Eq, PartialEq)]
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#[cfg_attr(feature = "defmt", derive(defmt::Format))]
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2021-05-28 19:31:40 +02:00
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pub enum Alignment {
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Left,
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Right,
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}
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2022-02-10 02:34:59 +01:00
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#[derive(Debug, Copy, Clone, Eq, PartialEq)]
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#[cfg_attr(feature = "defmt", derive(defmt::Format))]
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2021-05-28 19:31:40 +02:00
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pub enum Value {
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Bit8(u8),
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Bit12(u16, Alignment),
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}
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pub struct Dac<'d, T: Instance> {
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channels: u8,
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_peri: PeripheralRef<'d, T>,
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2021-05-28 19:31:40 +02:00
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}
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2022-03-18 00:11:57 +01:00
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macro_rules! enable {
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2022-03-18 00:33:39 +01:00
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($enable_reg:ident, $enable_field:ident, $reset_reg:ident, $reset_field:ident) => {
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2022-06-12 22:15:44 +02:00
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crate::pac::RCC.$enable_reg().modify(|w| w.$enable_field(true));
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crate::pac::RCC.$reset_reg().modify(|w| w.$reset_field(true));
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crate::pac::RCC.$reset_reg().modify(|w| w.$reset_field(false));
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2022-03-18 00:11:57 +01:00
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};
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}
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2021-05-28 19:31:40 +02:00
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impl<'d, T: Instance> Dac<'d, T> {
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2022-07-23 14:00:19 +02:00
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pub fn new_1ch(peri: impl Peripheral<P = T> + 'd, _ch1: impl Peripheral<P = impl DacPin<T, 1>> + 'd) -> Self {
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into_ref!(peri);
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2022-02-10 02:34:59 +01:00
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Self::new_inner(peri, 1)
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}
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pub fn new_2ch(
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peri: impl Peripheral<P = T> + 'd,
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_ch1: impl Peripheral<P = impl DacPin<T, 1>> + 'd,
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_ch2: impl Peripheral<P = impl DacPin<T, 2>> + 'd,
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) -> Self {
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into_ref!(peri);
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Self::new_inner(peri, 2)
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}
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2021-05-28 19:31:40 +02:00
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2022-07-23 14:00:19 +02:00
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fn new_inner(peri: PeripheralRef<'d, T>, channels: u8) -> Self {
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2021-09-29 02:56:19 +02:00
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unsafe {
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2022-02-10 02:34:59 +01:00
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// Sadly we cannot use `RccPeripheral::enable` since devices are quite inconsistent DAC clock
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// configuration.
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2022-03-18 00:11:57 +01:00
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critical_section::with(|_| {
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2022-08-04 02:02:57 +02:00
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cfg_if! {
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if #[cfg(rcc_f1)] {
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enable!(apb1enr, set_dacen, apb1rstr, set_dacrst);
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} else if #[cfg(rcc_h7)] {
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enable!(apb1lenr, set_dac12en, apb1lrstr, set_dac12rst);
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} else if #[cfg(rcc_h7ab)] {
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enable!(apb1lenr, set_dac1en, apb1lrstr, set_dac1rst);
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} else if #[cfg(stm32g0)] {
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enable!(apbenr1, set_dac1en, apbrstr1, set_dac1rst);
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} else if #[cfg(any(stm32l4, stm32l5))] {
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enable!(apb1enr1, set_dac1en, apb1rstr1, set_dac1rst);
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} else {
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unimplemented!("DAC enable/reset is not yet implemented for this chip");
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}
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}
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2022-03-18 00:11:57 +01:00
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});
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2022-02-10 02:34:59 +01:00
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2022-08-04 02:02:57 +02:00
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T::regs().cr().modify(|reg| {
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for ch in 0..channels {
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reg.set_en(ch as usize, true);
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}
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});
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2021-05-28 19:31:40 +02:00
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}
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2022-07-23 01:29:35 +02:00
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Self { channels, _peri: peri }
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}
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2022-02-10 02:34:59 +01:00
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/// Check the channel is configured
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fn check_channel_exists(&self, ch: Channel) -> Result<(), Error> {
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if ch == Channel::Ch2 && self.channels < 2 {
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Err(Error::UnconfiguredChannel)
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} else {
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Ok(())
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}
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}
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2021-12-29 05:27:59 +01:00
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fn set_channel_enable(&mut self, ch: Channel, on: bool) -> Result<(), Error> {
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2022-02-10 02:34:59 +01:00
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self.check_channel_exists(ch)?;
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unsafe {
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T::regs().cr().modify(|reg| {
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reg.set_en(ch.index(), on);
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})
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}
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Ok(())
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}
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2021-12-29 05:27:59 +01:00
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pub fn enable_channel(&mut self, ch: Channel) -> Result<(), Error> {
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self.set_channel_enable(ch, true)
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}
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2021-05-28 19:31:40 +02:00
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pub fn disable_channel(&mut self, ch: Channel) -> Result<(), Error> {
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2021-12-29 05:27:59 +01:00
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self.set_channel_enable(ch, false)
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}
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pub fn select_trigger_ch1(&mut self, trigger: Ch1Trigger) -> Result<(), Error> {
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self.check_channel_exists(Channel::Ch1)?;
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2021-06-05 10:15:35 +02:00
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unwrap!(self.disable_channel(Channel::Ch1));
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2021-05-28 19:31:40 +02:00
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unsafe {
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T::regs().cr().modify(|reg| {
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reg.set_tsel1(trigger.tsel());
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})
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}
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Ok(())
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}
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pub fn select_trigger_ch2(&mut self, trigger: Ch2Trigger) -> Result<(), Error> {
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self.check_channel_exists(Channel::Ch2)?;
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2021-06-05 10:15:35 +02:00
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unwrap!(self.disable_channel(Channel::Ch2));
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2021-05-28 19:31:40 +02:00
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unsafe {
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T::regs().cr().modify(|reg| {
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reg.set_tsel2(trigger.tsel());
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})
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}
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Ok(())
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}
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pub fn trigger(&mut self, ch: Channel) -> Result<(), Error> {
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self.check_channel_exists(ch)?;
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2022-08-04 02:02:57 +02:00
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unsafe {
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T::regs().swtrigr().write(|reg| {
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reg.set_swtrig(ch.index(), true);
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});
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2021-05-28 19:31:40 +02:00
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}
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2022-02-10 02:34:59 +01:00
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Ok(())
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}
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pub fn trigger_all(&mut self) {
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unsafe {
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T::regs().swtrigr().write(|reg| {
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2022-08-04 02:02:57 +02:00
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reg.set_swtrig(Channel::Ch1.index(), true);
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reg.set_swtrig(Channel::Ch2.index(), true);
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2021-05-28 19:31:40 +02:00
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})
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}
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}
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pub fn set(&mut self, ch: Channel, value: Value) -> Result<(), Error> {
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2022-04-12 12:49:06 +02:00
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self.check_channel_exists(ch)?;
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2022-08-04 02:02:57 +02:00
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match value {
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Value::Bit8(v) => unsafe {
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T::regs().dhr8r(ch.index()).write(|reg| reg.set_dhr(v));
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},
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Value::Bit12(v, Alignment::Left) => unsafe {
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T::regs().dhr12l(ch.index()).write(|reg| reg.set_dhr(v));
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},
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Value::Bit12(v, Alignment::Right) => unsafe {
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T::regs().dhr12r(ch.index()).write(|reg| reg.set_dhr(v));
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},
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}
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Ok(())
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}
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}
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pub(crate) mod sealed {
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pub trait Instance {
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fn regs() -> &'static crate::pac::dac::Dac;
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}
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}
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pub trait Instance: sealed::Instance + 'static {}
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pub trait DacPin<T: Instance, const C: u8>: crate::gpio::Pin + 'static {}
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foreach_peripheral!(
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(dac, $inst:ident) => {
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impl crate::dac::sealed::Instance for peripherals::$inst {
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fn regs() -> &'static crate::pac::dac::Dac {
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&crate::pac::$inst
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}
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}
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impl crate::dac::Instance for peripherals::$inst {}
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};
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);
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macro_rules! impl_dac_pin {
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($inst:ident, $pin:ident, $ch:expr) => {
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impl crate::dac::DacPin<peripherals::$inst, $ch> for crate::peripherals::$pin {}
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};
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}
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