153 lines
3.8 KiB
Rust
Raw Normal View History

#![macro_use]
pub use embedded_hal::blocking;
pub use embedded_hal::spi::{Mode, Phase, Polarity, MODE_0, MODE_1, MODE_2, MODE_3};
2021-07-21 16:45:43 -04:00
use futures::future::join3;
2021-05-12 14:18:42 -04:00
2021-12-06 22:45:40 -06:00
use super::*;
2021-05-10 15:21:57 -04:00
2021-07-21 16:45:43 -04:00
impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
2021-12-06 22:06:58 -06:00
pub(super) async fn write_dma_u8(&mut self, write: &[u8]) -> Result<(), Error>
2021-07-21 16:45:43 -04:00
where
Tx: TxDmaChannel<T>,
{
unsafe {
T::regs().cr1().modify(|w| {
w.set_spe(false);
});
}
self.set_word_size(WordSize::EightBit);
let request = self.txdma.request();
2021-12-06 16:33:06 -06:00
let dst = T::regs().tx_ptr();
2021-07-21 16:45:43 -04:00
let f = self.txdma.write(request, write, dst);
unsafe {
T::regs().cr2().modify(|reg| {
reg.set_txdmaen(true);
});
T::regs().cr1().modify(|w| {
w.set_spe(true);
});
}
f.await;
Ok(())
}
2021-12-06 22:06:58 -06:00
pub(super) async fn read_dma_u8(&mut self, read: &mut [u8]) -> Result<(), Error>
2021-07-21 16:45:43 -04:00
where
Tx: TxDmaChannel<T>,
Rx: RxDmaChannel<T>,
{
unsafe {
T::regs().cr1().modify(|w| {
w.set_spe(false);
});
T::regs().cr2().modify(|reg| {
reg.set_rxdmaen(true);
});
}
self.set_word_size(WordSize::EightBit);
let clock_byte_count = read.len();
let rx_request = self.rxdma.request();
2021-12-06 16:33:06 -06:00
let rx_src = T::regs().rx_ptr();
2021-07-21 16:45:43 -04:00
let rx_f = self.rxdma.read(rx_request, rx_src, read);
let tx_request = self.txdma.request();
2021-12-06 16:33:06 -06:00
let tx_dst = T::regs().tx_ptr();
2021-07-21 16:45:43 -04:00
let clock_byte = 0x00;
let tx_f = self
.txdma
.write_x(tx_request, &clock_byte, clock_byte_count, tx_dst);
unsafe {
T::regs().cr2().modify(|reg| {
reg.set_txdmaen(true);
});
T::regs().cr1().modify(|w| {
w.set_spe(true);
});
}
join3(tx_f, rx_f, Self::wait_for_idle()).await;
unsafe {
T::regs().cr2().modify(|reg| {
reg.set_txdmaen(false);
reg.set_rxdmaen(false);
});
T::regs().cr1().modify(|w| {
w.set_spe(false);
});
}
Ok(())
}
2021-12-06 22:06:58 -06:00
pub(super) async fn read_write_dma_u8(
&mut self,
read: &mut [u8],
write: &[u8],
) -> Result<(), Error>
2021-07-21 16:45:43 -04:00
where
Tx: TxDmaChannel<T>,
Rx: RxDmaChannel<T>,
{
assert!(read.len() >= write.len());
2021-07-21 16:45:43 -04:00
unsafe {
T::regs().cr1().modify(|w| {
w.set_spe(false);
});
T::regs().cr2().modify(|reg| {
reg.set_rxdmaen(true);
});
}
self.set_word_size(WordSize::EightBit);
let rx_request = self.rxdma.request();
2021-12-06 16:33:06 -06:00
let rx_src = T::regs().rx_ptr();
let rx_f = self
.rxdma
.read(rx_request, rx_src, &mut read[0..write.len()]);
2021-07-21 16:45:43 -04:00
let tx_request = self.txdma.request();
2021-12-06 16:33:06 -06:00
let tx_dst = T::regs().tx_ptr();
2021-07-21 16:45:43 -04:00
let tx_f = self.txdma.write(tx_request, write, tx_dst);
unsafe {
T::regs().cr2().modify(|reg| {
reg.set_txdmaen(true);
});
T::regs().cr1().modify(|w| {
w.set_spe(true);
});
}
join3(tx_f, rx_f, Self::wait_for_idle()).await;
unsafe {
T::regs().cr2().modify(|reg| {
reg.set_txdmaen(false);
reg.set_rxdmaen(false);
});
T::regs().cr1().modify(|w| {
w.set_spe(false);
});
}
Ok(())
}
async fn wait_for_idle() {
unsafe {
while T::regs().sr().read().bsy() {
// spin
}
}
}
}