2022-05-06 09:21:29 +02:00
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use core::convert::TryInto;
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use core::ptr::write_volatile;
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2023-03-25 16:04:45 +01:00
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use atomic_polyfill::{fence, Ordering};
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2023-03-30 06:01:56 +02:00
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use super::{FlashSector, BANK1_REGION, FLASH_REGIONS, WRITE_SIZE};
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2022-05-06 09:21:29 +02:00
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use crate::flash::Error;
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use crate::pac;
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const fn is_dual_bank() -> bool {
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2023-03-30 06:01:56 +02:00
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FLASH_REGIONS.len() == 2
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2022-05-06 09:21:29 +02:00
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}
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pub(crate) unsafe fn lock() {
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pac::FLASH.bank(0).cr().modify(|w| w.set_lock(true));
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if is_dual_bank() {
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pac::FLASH.bank(1).cr().modify(|w| w.set_lock(true));
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}
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}
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pub(crate) unsafe fn unlock() {
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pac::FLASH.bank(0).keyr().write(|w| w.set_keyr(0x4567_0123));
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pac::FLASH.bank(0).keyr().write(|w| w.set_keyr(0xCDEF_89AB));
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if is_dual_bank() {
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pac::FLASH.bank(1).keyr().write(|w| w.set_keyr(0x4567_0123));
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pac::FLASH.bank(1).keyr().write(|w| w.set_keyr(0xCDEF_89AB));
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}
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}
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2023-03-25 16:04:45 +01:00
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pub(crate) unsafe fn begin_write() {
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assert_eq!(0, WRITE_SIZE % 4);
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}
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pub(crate) unsafe fn end_write() {}
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pub(crate) unsafe fn blocking_write(start_address: u32, buf: &[u8; WRITE_SIZE]) -> Result<(), Error> {
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// We cannot have the write setup sequence in begin_write as it depends on the address
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2023-03-30 06:01:56 +02:00
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let bank = if start_address < BANK1_REGION.end() {
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2022-05-06 09:21:29 +02:00
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pac::FLASH.bank(0)
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} else {
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pac::FLASH.bank(1)
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};
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bank.cr().write(|w| {
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w.set_pg(true);
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w.set_psize(2); // 32 bits at once
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});
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2022-10-18 22:42:02 +02:00
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cortex_m::asm::isb();
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cortex_m::asm::dsb();
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2023-03-25 16:04:45 +01:00
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fence(Ordering::SeqCst);
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let mut res = None;
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let mut address = start_address;
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for val in buf.chunks(4) {
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write_volatile(address as *mut u32, u32::from_le_bytes(val.try_into().unwrap()));
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address += val.len() as u32;
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res = Some(blocking_wait_ready(bank));
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bank.sr().modify(|w| {
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if w.eop() {
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w.set_eop(true);
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2022-05-06 09:21:29 +02:00
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}
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2023-03-25 16:04:45 +01:00
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});
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if res.unwrap().is_err() {
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break;
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2022-05-06 09:21:29 +02:00
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}
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2023-03-25 16:04:45 +01:00
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}
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2022-05-06 09:21:29 +02:00
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bank.cr().write(|w| w.set_pg(false));
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2022-10-18 22:42:02 +02:00
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cortex_m::asm::isb();
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cortex_m::asm::dsb();
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2023-03-25 16:04:45 +01:00
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fence(Ordering::SeqCst);
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2022-10-18 22:42:02 +02:00
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2023-03-25 16:04:45 +01:00
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res.unwrap()
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2022-05-06 09:21:29 +02:00
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}
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2023-03-29 13:37:10 +02:00
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pub(crate) unsafe fn blocking_erase_sector(sector: &FlashSector) -> Result<(), Error> {
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2023-03-29 14:50:19 +02:00
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let bank = pac::FLASH.bank(if sector.index >= 8 { 1 } else { 0 });
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2023-03-29 13:37:10 +02:00
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let sector = sector.index % 8;
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2022-05-06 09:21:29 +02:00
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bank.cr().modify(|w| {
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w.set_ser(true);
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w.set_snb(sector)
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});
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bank.cr().modify(|w| {
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w.set_start(true);
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});
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let ret: Result<(), Error> = blocking_wait_ready(bank);
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bank.cr().modify(|w| w.set_ser(false));
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bank_clear_all_err(bank);
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ret
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}
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pub(crate) unsafe fn clear_all_err() {
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bank_clear_all_err(pac::FLASH.bank(0));
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bank_clear_all_err(pac::FLASH.bank(1));
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}
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unsafe fn bank_clear_all_err(bank: pac::flash::Bank) {
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bank.sr().modify(|w| {
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if w.wrperr() {
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w.set_wrperr(true);
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}
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if w.pgserr() {
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w.set_pgserr(true);
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}
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if w.strberr() {
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// single address was written multiple times, can be ignored
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w.set_strberr(true);
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}
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if w.incerr() {
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// writing to a different address when programming 256 bit word was not finished
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w.set_incerr(true);
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}
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if w.operr() {
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w.set_operr(true);
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}
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if w.sneccerr1() {
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// single ECC error
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w.set_sneccerr1(true);
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}
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if w.dbeccerr() {
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// double ECC error
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w.set_dbeccerr(true);
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}
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if w.rdperr() {
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w.set_rdperr(true);
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}
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if w.rdserr() {
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w.set_rdserr(true);
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}
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});
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}
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2023-03-25 16:04:45 +01:00
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unsafe fn blocking_wait_ready(bank: pac::flash::Bank) -> Result<(), Error> {
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2022-05-06 09:21:29 +02:00
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loop {
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let sr = bank.sr().read();
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if !sr.bsy() && !sr.qw() {
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if sr.wrperr() {
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return Err(Error::Protected);
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}
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if sr.pgserr() {
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error!("pgserr");
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return Err(Error::Seq);
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}
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if sr.incerr() {
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// writing to a different address when programming 256 bit word was not finished
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error!("incerr");
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return Err(Error::Seq);
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}
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if sr.operr() {
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return Err(Error::Prog);
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}
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if sr.sneccerr1() {
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// single ECC error
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return Err(Error::Prog);
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}
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if sr.dbeccerr() {
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// double ECC error
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return Err(Error::Prog);
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}
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if sr.rdperr() {
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return Err(Error::Protected);
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}
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if sr.rdserr() {
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return Err(Error::Protected);
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}
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return Ok(());
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}
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}
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}
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2023-03-29 12:49:13 +02:00
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pub(crate) fn get_sector(address: u32) -> FlashSector {
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2023-03-30 06:01:56 +02:00
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let sector_size = BANK1_REGION.erase_size;
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2023-03-29 12:49:13 +02:00
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let index = address / sector_size;
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FlashSector {
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index: index as u8,
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2023-03-30 06:01:56 +02:00
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start: BANK1_REGION.base + index * sector_size,
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2023-03-29 12:49:13 +02:00
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size: sector_size,
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}
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}
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