2021-05-06 03:59:16 +02:00
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#![macro_use]
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2021-12-08 05:12:48 +01:00
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use core::marker::PhantomData;
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use embassy::interrupt::Interrupt;
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use embassy::util::Unborrow;
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use embassy_hal_common::unborrow;
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2021-04-14 15:34:58 +02:00
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2021-12-08 05:12:48 +01:00
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use crate::dma::NoDma;
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2022-02-24 00:20:43 +01:00
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use crate::gpio::sealed::AFType;
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2021-12-08 05:12:48 +01:00
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use crate::pac::usart::{regs, vals};
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2022-02-10 21:38:03 +01:00
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use crate::peripherals;
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2021-06-29 16:59:22 +02:00
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use crate::rcc::RccPeripheral;
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2021-04-14 15:34:58 +02:00
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2021-06-30 20:37:35 +02:00
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#[derive(Clone, Copy, PartialEq, Eq, Debug)]
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pub enum DataBits {
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DataBits8,
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DataBits9,
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}
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#[derive(Clone, Copy, PartialEq, Eq, Debug)]
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pub enum Parity {
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ParityNone,
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ParityEven,
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ParityOdd,
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}
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#[derive(Clone, Copy, PartialEq, Eq, Debug)]
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pub enum StopBits {
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#[doc = "1 stop bit"]
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STOP1,
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#[doc = "0.5 stop bits"]
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STOP0P5,
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#[doc = "2 stop bits"]
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STOP2,
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#[doc = "1.5 stop bits"]
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STOP1P5,
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}
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#[non_exhaustive]
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#[derive(Clone, Copy, PartialEq, Eq, Debug)]
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pub struct Config {
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pub baudrate: u32,
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pub data_bits: DataBits,
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pub stop_bits: StopBits,
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pub parity: Parity,
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}
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impl Default for Config {
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fn default() -> Self {
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Self {
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baudrate: 115200,
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data_bits: DataBits::DataBits8,
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stop_bits: StopBits::STOP1,
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parity: Parity::ParityNone,
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}
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}
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}
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2021-05-15 03:52:58 +02:00
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/// Serial error
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#[derive(Debug, Eq, PartialEq, Copy, Clone)]
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2021-07-04 23:34:37 +02:00
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#[cfg_attr(feature = "defmt", derive(defmt::Format))]
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2021-04-14 15:34:58 +02:00
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#[non_exhaustive]
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2021-05-15 03:52:58 +02:00
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pub enum Error {
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/// Framing error
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Framing,
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/// Noise error
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Noise,
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/// RX buffer overrun
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Overrun,
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/// Parity check error
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Parity,
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2021-04-14 15:34:58 +02:00
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}
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2021-12-08 05:12:48 +01:00
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pub struct Uart<'d, T: Instance, TxDma = NoDma, RxDma = NoDma> {
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inner: T,
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phantom: PhantomData<&'d mut T>,
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tx_dma: TxDma,
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rx_dma: RxDma,
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}
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impl<'d, T: Instance, TxDma, RxDma> Uart<'d, T, TxDma, RxDma> {
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pub fn new(
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2022-02-10 16:06:42 +01:00
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inner: impl Unborrow<Target = T> + 'd,
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rx: impl Unborrow<Target = impl RxPin<T>> + 'd,
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tx: impl Unborrow<Target = impl TxPin<T>> + 'd,
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tx_dma: impl Unborrow<Target = TxDma> + 'd,
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rx_dma: impl Unborrow<Target = RxDma> + 'd,
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2021-12-08 05:12:48 +01:00
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config: Config,
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) -> Self {
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unborrow!(inner, rx, tx, tx_dma, rx_dma);
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T::enable();
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let pclk_freq = T::frequency();
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// TODO: better calculation, including error checking and OVER8 if possible.
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let div = (pclk_freq.0 + (config.baudrate / 2)) / config.baudrate;
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let r = inner.regs();
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unsafe {
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2022-02-24 00:20:43 +01:00
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rx.set_as_af(rx.af_num(), AFType::Input);
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tx.set_as_af(tx.af_num(), AFType::OutputPushPull);
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2021-12-08 05:12:48 +01:00
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r.cr2().write(|_w| {});
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r.cr3().write(|_w| {});
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r.brr().write_value(regs::Brr(div));
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r.cr1().write(|w| {
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w.set_ue(true);
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w.set_te(true);
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w.set_re(true);
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w.set_m0(vals::M0::BIT8);
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w.set_pce(config.parity != Parity::ParityNone);
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w.set_ps(match config.parity {
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Parity::ParityOdd => vals::Ps::ODD,
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Parity::ParityEven => vals::Ps::EVEN,
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_ => vals::Ps::EVEN,
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});
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});
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}
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Self {
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inner,
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phantom: PhantomData,
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tx_dma,
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rx_dma,
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}
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}
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2022-01-14 22:43:40 +01:00
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pub async fn write(&mut self, buffer: &[u8]) -> Result<(), Error>
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2021-12-08 05:12:48 +01:00
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where
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TxDma: crate::usart::TxDma<T>,
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{
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let ch = &mut self.tx_dma;
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let request = ch.request();
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unsafe {
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self.inner.regs().cr3().modify(|reg| {
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reg.set_dmat(true);
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});
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}
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let r = self.inner.regs();
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let dst = tdr(r);
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crate::dma::write(ch, request, buffer, dst).await;
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Ok(())
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}
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2022-01-14 22:43:40 +01:00
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pub async fn read(&mut self, buffer: &mut [u8]) -> Result<(), Error>
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2021-12-08 05:12:48 +01:00
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where
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RxDma: crate::usart::RxDma<T>,
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{
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let ch = &mut self.rx_dma;
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let request = ch.request();
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unsafe {
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self.inner.regs().cr3().modify(|reg| {
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reg.set_dmar(true);
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});
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}
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let r = self.inner.regs();
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let src = rdr(r);
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crate::dma::read(ch, request, src, buffer).await;
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Ok(())
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}
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2022-01-14 22:43:40 +01:00
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pub fn blocking_read(&mut self, buffer: &mut [u8]) -> Result<(), Error> {
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2021-12-08 05:12:48 +01:00
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unsafe {
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let r = self.inner.regs();
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for b in buffer {
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loop {
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let sr = sr(r).read();
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if sr.pe() {
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rdr(r).read_volatile();
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return Err(Error::Parity);
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} else if sr.fe() {
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rdr(r).read_volatile();
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return Err(Error::Framing);
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} else if sr.ne() {
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rdr(r).read_volatile();
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return Err(Error::Noise);
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} else if sr.ore() {
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rdr(r).read_volatile();
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return Err(Error::Overrun);
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} else if sr.rxne() {
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break;
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}
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}
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*b = rdr(r).read_volatile();
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}
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}
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Ok(())
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}
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2022-01-14 22:43:40 +01:00
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pub fn blocking_write(&mut self, buffer: &[u8]) -> Result<(), Error> {
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unsafe {
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let r = self.inner.regs();
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for &b in buffer {
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while !sr(r).read().txe() {}
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tdr(r).write_volatile(b);
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}
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}
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Ok(())
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}
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pub fn blocking_flush(&mut self) -> Result<(), Error> {
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unsafe {
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let r = self.inner.regs();
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while !sr(r).read().tc() {}
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}
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Ok(())
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}
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2021-12-08 05:12:48 +01:00
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}
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2022-01-26 22:39:06 +01:00
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mod eh02 {
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use super::*;
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impl<'d, T: Instance, TxDma, RxDma> embedded_hal_02::serial::Read<u8>
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for Uart<'d, T, TxDma, RxDma>
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{
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type Error = Error;
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fn read(&mut self) -> Result<u8, nb::Error<Self::Error>> {
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let r = self.inner.regs();
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unsafe {
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let sr = sr(r).read();
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if sr.pe() {
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rdr(r).read_volatile();
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Err(nb::Error::Other(Error::Parity))
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} else if sr.fe() {
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rdr(r).read_volatile();
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Err(nb::Error::Other(Error::Framing))
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} else if sr.ne() {
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rdr(r).read_volatile();
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Err(nb::Error::Other(Error::Noise))
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} else if sr.ore() {
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rdr(r).read_volatile();
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Err(nb::Error::Other(Error::Overrun))
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} else if sr.rxne() {
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Ok(rdr(r).read_volatile())
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} else {
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Err(nb::Error::WouldBlock)
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}
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2021-12-17 12:50:48 +01:00
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}
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}
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}
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2022-01-26 22:39:06 +01:00
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impl<'d, T: Instance, TxDma, RxDma> embedded_hal_02::blocking::serial::Write<u8>
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for Uart<'d, T, TxDma, RxDma>
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{
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type Error = Error;
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fn bwrite_all(&mut self, buffer: &[u8]) -> Result<(), Self::Error> {
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self.blocking_write(buffer)
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}
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fn bflush(&mut self) -> Result<(), Self::Error> {
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self.blocking_flush()
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}
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}
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2021-12-17 12:50:48 +01:00
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}
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2022-01-26 22:39:06 +01:00
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#[cfg(feature = "unstable-traits")]
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mod eh1 {
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use super::*;
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impl embedded_hal_1::serial::Error for Error {
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fn kind(&self) -> embedded_hal_1::serial::ErrorKind {
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match *self {
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Self::Framing => embedded_hal_1::serial::ErrorKind::FrameFormat,
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Self::Noise => embedded_hal_1::serial::ErrorKind::Noise,
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Self::Overrun => embedded_hal_1::serial::ErrorKind::Overrun,
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Self::Parity => embedded_hal_1::serial::ErrorKind::Parity,
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}
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}
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2021-12-08 05:12:48 +01:00
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}
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2022-01-26 22:39:06 +01:00
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impl<'d, T: Instance, TxDma, RxDma> embedded_hal_1::serial::ErrorType
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for Uart<'d, T, TxDma, RxDma>
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{
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type Error = Error;
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2021-12-08 05:12:48 +01:00
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}
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2022-02-12 02:26:15 +01:00
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}
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#[cfg(all(feature = "unstable-traits", feature = "nightly"))]
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mod eh1a {
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use super::*;
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use core::future::Future;
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2021-12-08 05:12:48 +01:00
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2022-01-26 22:39:06 +01:00
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impl<'d, T: Instance, TxDma, RxDma> embedded_hal_async::serial::Write for Uart<'d, T, TxDma, RxDma>
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2021-12-16 11:37:53 +01:00
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where
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2022-01-26 22:39:06 +01:00
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TxDma: crate::usart::TxDma<T>,
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{
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type WriteFuture<'a>
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where
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Self: 'a,
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= impl Future<Output = Result<(), Self::Error>> + 'a;
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fn write<'a>(&'a mut self, buf: &'a [u8]) -> Self::WriteFuture<'a> {
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self.write(buf)
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}
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2021-12-08 05:12:48 +01:00
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2022-01-26 22:39:06 +01:00
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type FlushFuture<'a>
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where
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Self: 'a,
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= impl Future<Output = Result<(), Self::Error>> + 'a;
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fn flush<'a>(&'a mut self) -> Self::FlushFuture<'a> {
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async move { Ok(()) }
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}
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2021-12-08 05:12:48 +01:00
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}
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2022-01-26 22:39:06 +01:00
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impl<'d, T: Instance, TxDma, RxDma> embedded_hal_async::serial::Read for Uart<'d, T, TxDma, RxDma>
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2021-12-16 11:37:53 +01:00
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where
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2022-01-26 22:39:06 +01:00
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RxDma: crate::usart::RxDma<T>,
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{
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type ReadFuture<'a>
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where
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Self: 'a,
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= impl Future<Output = Result<(), Self::Error>> + 'a;
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2021-12-08 05:12:48 +01:00
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2022-01-26 22:39:06 +01:00
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fn read<'a>(&'a mut self, buf: &'a mut [u8]) -> Self::ReadFuture<'a> {
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self.read(buf)
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}
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2021-12-08 05:12:48 +01:00
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}
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}
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pub use buffered::*;
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mod buffered {
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use atomic_polyfill::{compiler_fence, Ordering};
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use core::pin::Pin;
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use core::task::Context;
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use core::task::Poll;
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use embassy::waitqueue::WakerRegistration;
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use embassy_hal_common::peripheral::{PeripheralMutex, PeripheralState, StateStorage};
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use embassy_hal_common::ring_buffer::RingBuffer;
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use super::*;
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pub struct State<'d, T: Instance>(StateStorage<StateInner<'d, T>>);
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impl<'d, T: Instance> State<'d, T> {
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pub fn new() -> Self {
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Self(StateStorage::new())
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}
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}
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struct StateInner<'d, T: Instance> {
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uart: Uart<'d, T, NoDma, NoDma>,
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phantom: PhantomData<&'d mut T>,
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rx_waker: WakerRegistration,
|
|
|
|
rx: RingBuffer<'d>,
|
|
|
|
|
|
|
|
tx_waker: WakerRegistration,
|
|
|
|
tx: RingBuffer<'d>,
|
|
|
|
}
|
|
|
|
|
|
|
|
unsafe impl<'d, T: Instance> Send for StateInner<'d, T> {}
|
|
|
|
unsafe impl<'d, T: Instance> Sync for StateInner<'d, T> {}
|
|
|
|
|
|
|
|
pub struct BufferedUart<'d, T: Instance> {
|
|
|
|
inner: PeripheralMutex<'d, StateInner<'d, T>>,
|
|
|
|
}
|
|
|
|
|
|
|
|
impl<'d, T: Instance> Unpin for BufferedUart<'d, T> {}
|
|
|
|
|
|
|
|
impl<'d, T: Instance> BufferedUart<'d, T> {
|
|
|
|
pub unsafe fn new(
|
|
|
|
state: &'d mut State<'d, T>,
|
|
|
|
uart: Uart<'d, T, NoDma, NoDma>,
|
|
|
|
irq: impl Unborrow<Target = T::Interrupt> + 'd,
|
|
|
|
tx_buffer: &'d mut [u8],
|
|
|
|
rx_buffer: &'d mut [u8],
|
|
|
|
) -> BufferedUart<'d, T> {
|
|
|
|
unborrow!(irq);
|
|
|
|
|
|
|
|
let r = uart.inner.regs();
|
|
|
|
r.cr1().modify(|w| {
|
|
|
|
w.set_rxneie(true);
|
|
|
|
w.set_idleie(true);
|
|
|
|
});
|
|
|
|
|
|
|
|
Self {
|
|
|
|
inner: PeripheralMutex::new_unchecked(irq, &mut state.0, move || StateInner {
|
|
|
|
uart,
|
|
|
|
phantom: PhantomData,
|
|
|
|
tx: RingBuffer::new(tx_buffer),
|
|
|
|
tx_waker: WakerRegistration::new(),
|
|
|
|
|
|
|
|
rx: RingBuffer::new(rx_buffer),
|
|
|
|
rx_waker: WakerRegistration::new(),
|
|
|
|
}),
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
impl<'d, T: Instance> StateInner<'d, T>
|
|
|
|
where
|
|
|
|
Self: 'd,
|
|
|
|
{
|
|
|
|
fn on_rx(&mut self) {
|
|
|
|
let r = self.uart.inner.regs();
|
|
|
|
unsafe {
|
2021-12-26 16:04:07 +01:00
|
|
|
let sr = sr(r).read();
|
2022-02-25 13:19:51 +01:00
|
|
|
clear_interrupt_flags(r, sr);
|
|
|
|
|
|
|
|
// This read also clears the error and idle interrupt flags on v1.
|
|
|
|
let b = rdr(r).read_volatile();
|
|
|
|
|
|
|
|
if sr.rxne() {
|
|
|
|
if sr.pe() {
|
|
|
|
warn!("Parity error");
|
|
|
|
}
|
|
|
|
if sr.fe() {
|
|
|
|
warn!("Framing error");
|
|
|
|
}
|
|
|
|
if sr.ne() {
|
|
|
|
warn!("Noise error");
|
|
|
|
}
|
|
|
|
if sr.ore() {
|
|
|
|
warn!("Overrun error");
|
|
|
|
}
|
|
|
|
|
2021-12-08 05:12:48 +01:00
|
|
|
let buf = self.rx.push_buf();
|
2022-02-25 13:19:51 +01:00
|
|
|
if !buf.is_empty() {
|
|
|
|
buf[0] = b;
|
2021-12-08 05:12:48 +01:00
|
|
|
self.rx.push(1);
|
2022-02-25 13:19:51 +01:00
|
|
|
} else {
|
|
|
|
warn!("RX buffer full, discard received byte");
|
|
|
|
}
|
|
|
|
|
|
|
|
if self.rx.is_full() {
|
|
|
|
self.rx_waker.wake();
|
2021-12-08 05:12:48 +01:00
|
|
|
}
|
2022-02-25 13:19:51 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
if sr.idle() {
|
2021-12-08 05:12:48 +01:00
|
|
|
self.rx_waker.wake();
|
|
|
|
};
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
fn on_tx(&mut self) {
|
|
|
|
let r = self.uart.inner.regs();
|
|
|
|
unsafe {
|
2021-12-26 16:04:07 +01:00
|
|
|
if sr(r).read().txe() {
|
2021-12-08 05:12:48 +01:00
|
|
|
let buf = self.tx.pop_buf();
|
|
|
|
if !buf.is_empty() {
|
|
|
|
r.cr1().modify(|w| {
|
|
|
|
w.set_txeie(true);
|
|
|
|
});
|
2021-12-26 16:04:07 +01:00
|
|
|
tdr(r).write_volatile(buf[0].into());
|
2021-12-08 05:12:48 +01:00
|
|
|
self.tx.pop(1);
|
|
|
|
self.tx_waker.wake();
|
|
|
|
} else {
|
|
|
|
// Disable interrupt until we have something to transmit again
|
|
|
|
r.cr1().modify(|w| {
|
|
|
|
w.set_txeie(false);
|
|
|
|
});
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
impl<'d, T: Instance> PeripheralState for StateInner<'d, T>
|
|
|
|
where
|
|
|
|
Self: 'd,
|
|
|
|
{
|
|
|
|
type Interrupt = T::Interrupt;
|
|
|
|
fn on_interrupt(&mut self) {
|
|
|
|
self.on_rx();
|
|
|
|
self.on_tx();
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
impl<'d, T: Instance> embassy::io::AsyncBufRead for BufferedUart<'d, T> {
|
|
|
|
fn poll_fill_buf(
|
|
|
|
mut self: Pin<&mut Self>,
|
|
|
|
cx: &mut Context<'_>,
|
|
|
|
) -> Poll<Result<&[u8], embassy::io::Error>> {
|
|
|
|
self.inner.with(|state| {
|
|
|
|
compiler_fence(Ordering::SeqCst);
|
|
|
|
|
|
|
|
// We have data ready in buffer? Return it.
|
|
|
|
let buf = state.rx.pop_buf();
|
|
|
|
if !buf.is_empty() {
|
|
|
|
let buf: &[u8] = buf;
|
|
|
|
// Safety: buffer lives as long as uart
|
|
|
|
let buf: &[u8] = unsafe { core::mem::transmute(buf) };
|
|
|
|
return Poll::Ready(Ok(buf));
|
|
|
|
}
|
|
|
|
|
|
|
|
state.rx_waker.register(cx.waker());
|
|
|
|
Poll::<Result<&[u8], embassy::io::Error>>::Pending
|
|
|
|
})
|
|
|
|
}
|
|
|
|
fn consume(mut self: Pin<&mut Self>, amt: usize) {
|
|
|
|
let signal = self.inner.with(|state| {
|
|
|
|
let full = state.rx.is_full();
|
|
|
|
state.rx.pop(amt);
|
|
|
|
full
|
|
|
|
});
|
|
|
|
if signal {
|
|
|
|
self.inner.pend();
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
impl<'d, T: Instance> embassy::io::AsyncWrite for BufferedUart<'d, T> {
|
|
|
|
fn poll_write(
|
|
|
|
mut self: Pin<&mut Self>,
|
|
|
|
cx: &mut Context<'_>,
|
|
|
|
buf: &[u8],
|
|
|
|
) -> Poll<Result<usize, embassy::io::Error>> {
|
|
|
|
let (poll, empty) = self.inner.with(|state| {
|
|
|
|
let empty = state.tx.is_empty();
|
|
|
|
let tx_buf = state.tx.push_buf();
|
|
|
|
if tx_buf.is_empty() {
|
|
|
|
state.tx_waker.register(cx.waker());
|
|
|
|
return (Poll::Pending, empty);
|
|
|
|
}
|
|
|
|
|
|
|
|
let n = core::cmp::min(tx_buf.len(), buf.len());
|
|
|
|
tx_buf[..n].copy_from_slice(&buf[..n]);
|
|
|
|
state.tx.push(n);
|
|
|
|
|
|
|
|
(Poll::Ready(Ok(n)), empty)
|
|
|
|
});
|
|
|
|
if empty {
|
|
|
|
self.inner.pend();
|
|
|
|
}
|
|
|
|
poll
|
|
|
|
}
|
2021-12-10 05:11:41 +01:00
|
|
|
|
|
|
|
fn poll_flush(
|
|
|
|
mut self: Pin<&mut Self>,
|
|
|
|
cx: &mut Context<'_>,
|
|
|
|
) -> Poll<Result<(), embassy::io::Error>> {
|
|
|
|
self.inner.with(|state| {
|
|
|
|
if !state.tx.is_empty() {
|
|
|
|
state.tx_waker.register(cx.waker());
|
|
|
|
return Poll::Pending;
|
|
|
|
}
|
|
|
|
|
|
|
|
Poll::Ready(Ok(()))
|
|
|
|
})
|
|
|
|
}
|
2021-12-08 05:12:48 +01:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
#[cfg(usart_v1)]
|
|
|
|
fn tdr(r: crate::pac::usart::Usart) -> *mut u8 {
|
|
|
|
r.dr().ptr() as _
|
|
|
|
}
|
|
|
|
|
|
|
|
#[cfg(usart_v1)]
|
|
|
|
fn rdr(r: crate::pac::usart::Usart) -> *mut u8 {
|
|
|
|
r.dr().ptr() as _
|
|
|
|
}
|
|
|
|
|
|
|
|
#[cfg(usart_v1)]
|
|
|
|
fn sr(r: crate::pac::usart::Usart) -> crate::pac::common::Reg<regs::Sr, crate::pac::common::RW> {
|
|
|
|
r.sr()
|
|
|
|
}
|
|
|
|
|
2021-12-26 16:04:07 +01:00
|
|
|
#[cfg(usart_v1)]
|
2022-02-25 13:19:51 +01:00
|
|
|
unsafe fn clear_interrupt_flags(_r: crate::pac::usart::Usart, _sr: regs::Sr) {
|
|
|
|
// On v1 the flags are cleared implicitly by reads and writes to DR.
|
2021-12-26 16:04:07 +01:00
|
|
|
}
|
|
|
|
|
2021-12-08 05:12:48 +01:00
|
|
|
#[cfg(usart_v2)]
|
|
|
|
fn tdr(r: crate::pac::usart::Usart) -> *mut u8 {
|
|
|
|
r.tdr().ptr() as _
|
|
|
|
}
|
|
|
|
|
|
|
|
#[cfg(usart_v2)]
|
|
|
|
fn rdr(r: crate::pac::usart::Usart) -> *mut u8 {
|
|
|
|
r.rdr().ptr() as _
|
|
|
|
}
|
|
|
|
|
|
|
|
#[cfg(usart_v2)]
|
|
|
|
fn sr(r: crate::pac::usart::Usart) -> crate::pac::common::Reg<regs::Ixr, crate::pac::common::R> {
|
|
|
|
r.isr()
|
|
|
|
}
|
|
|
|
|
2021-12-26 16:04:07 +01:00
|
|
|
#[cfg(usart_v2)]
|
2022-02-25 13:19:51 +01:00
|
|
|
unsafe fn clear_interrupt_flags(r: crate::pac::usart::Usart, sr: regs::Ixr) {
|
|
|
|
r.icr().write(|w| *w = sr);
|
2021-12-26 16:04:07 +01:00
|
|
|
}
|
|
|
|
|
2021-04-25 22:35:51 +02:00
|
|
|
pub(crate) mod sealed {
|
|
|
|
pub trait Instance {
|
2021-07-04 23:34:37 +02:00
|
|
|
fn regs(&self) -> crate::pac::usart::Usart;
|
2021-04-25 22:35:51 +02:00
|
|
|
}
|
|
|
|
}
|
2021-06-25 20:00:11 +02:00
|
|
|
|
2021-08-16 17:16:49 +02:00
|
|
|
pub trait Instance: sealed::Instance + RccPeripheral {
|
|
|
|
type Interrupt: Interrupt;
|
|
|
|
}
|
2022-02-10 21:38:03 +01:00
|
|
|
|
|
|
|
pin_trait!(RxPin, Instance);
|
|
|
|
pin_trait!(TxPin, Instance);
|
|
|
|
pin_trait!(CtsPin, Instance);
|
|
|
|
pin_trait!(RtsPin, Instance);
|
|
|
|
pin_trait!(CkPin, Instance);
|
|
|
|
|
|
|
|
dma_trait!(TxDma, Instance);
|
|
|
|
dma_trait!(RxDma, Instance);
|
2021-06-25 20:00:11 +02:00
|
|
|
|
2021-08-16 17:16:49 +02:00
|
|
|
crate::pac::interrupts!(
|
|
|
|
($inst:ident, usart, $block:ident, $signal_name:ident, $irq:ident) => {
|
2021-06-03 17:27:17 +02:00
|
|
|
impl sealed::Instance for peripherals::$inst {
|
2021-05-06 03:43:46 +02:00
|
|
|
fn regs(&self) -> crate::pac::usart::Usart {
|
|
|
|
crate::pac::$inst
|
2021-04-14 15:34:58 +02:00
|
|
|
}
|
|
|
|
}
|
2021-06-03 17:27:17 +02:00
|
|
|
|
2021-08-16 17:16:49 +02:00
|
|
|
impl Instance for peripherals::$inst {
|
|
|
|
type Interrupt = crate::interrupt::$irq;
|
|
|
|
}
|
2021-04-14 15:34:58 +02:00
|
|
|
};
|
2021-06-03 17:27:17 +02:00
|
|
|
);
|