Merge #1406
1406: rp: DMA behaviour during flash operations r=Dirbaio a=kalkyl This PR changes the old behaviour during flash operations where all DMA transfers were paused during the flash operation. The new approach is to wait for any DMA operating in flash region to finish and let RAM transfers continue. Co-authored-by: kalkyl <henrik.alser@me.com>
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03d6363d5a
@ -162,8 +162,6 @@ impl<'d, T: Instance, const FLASH_SIZE: usize> Flash<'d, T, FLASH_SIZE> {
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/// - interrupts must be disabled
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/// - interrupts must be disabled
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/// - DMA must not access flash memory
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/// - DMA must not access flash memory
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unsafe fn in_ram(&mut self, operation: impl FnOnce()) -> Result<(), Error> {
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unsafe fn in_ram(&mut self, operation: impl FnOnce()) -> Result<(), Error> {
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let dma_status = &mut [false; crate::dma::CHANNEL_COUNT];
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// Make sure we're running on CORE0
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// Make sure we're running on CORE0
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let core_id: u32 = unsafe { pac::SIO.cpuid().read() };
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let core_id: u32 = unsafe { pac::SIO.cpuid().read() };
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if core_id != 0 {
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if core_id != 0 {
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@ -174,25 +172,15 @@ impl<'d, T: Instance, const FLASH_SIZE: usize> Flash<'d, T, FLASH_SIZE> {
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crate::multicore::pause_core1();
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crate::multicore::pause_core1();
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critical_section::with(|_| {
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critical_section::with(|_| {
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// Pause all DMA channels for the duration of the ram operation
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// Wait for all DMA channels in flash to finish before ram operation
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for (number, status) in dma_status.iter_mut().enumerate() {
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const SRAM_LOWER: u32 = 0x2000_0000;
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let ch = crate::pac::DMA.ch(number as _);
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for n in 0..crate::dma::CHANNEL_COUNT {
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*status = ch.ctrl_trig().read().en();
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let ch = crate::pac::DMA.ch(n);
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if *status {
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while ch.read_addr().read() < SRAM_LOWER && ch.ctrl_trig().read().busy() {}
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ch.ctrl_trig().modify(|w| w.set_en(false));
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}
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}
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}
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// Run our flash operation in RAM
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// Run our flash operation in RAM
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operation();
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operation();
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// Re-enable previously enabled DMA channels
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for (number, status) in dma_status.iter().enumerate() {
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let ch = crate::pac::DMA.ch(number as _);
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if *status {
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ch.ctrl_trig().modify(|w| w.set_en(true));
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}
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}
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});
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});
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// Resume CORE1 execution
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// Resume CORE1 execution
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