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cleanup consts

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This commit is contained in:
Brandon Ros 2023-08-22 18:41:48 -04:00
parent 145a5cb762
commit 058c10f3e9
3 changed files with 12 additions and 27 deletions
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7
cyw43/src/bus.rs
View File

@ -259,7 +259,7 @@ where
self.backplane_set_window(0x18000000).await; // CHIPCOMMON_BASE_ADDRESS self.backplane_set_window(0x18000000).await; // CHIPCOMMON_BASE_ADDRESS
return val; return val
} }
async fn backplane_writen(&mut self, addr: u32, val: u32, len: u32) { async fn backplane_writen(&mut self, addr: u32, val: u32, len: u32) {
@ -345,10 +345,7 @@ where
self.status = self.spi.cmd_read(cmd, &mut buf[..len]).await; self.status = self.spi.cmd_read(cmd, &mut buf[..len]).await;
debug!( debug!("readn cmd = {:08x} addr = {:08x} len = {} buf = {:08x}", cmd, addr, len, buf);
"readn cmd = {:08x} addr = {:08x} len = {} buf = {:08x}",
cmd, addr, len, buf
);
// if we read from the backplane, the result is in the second word, after the response delay // if we read from the backplane, the result is in the second word, after the response delay
if func == FUNC_BACKPLANE { if func == FUNC_BACKPLANE {

26
cyw43/src/consts.rs
View File

@ -65,8 +65,8 @@ pub(crate) const REG_BACKPLANE_READ_FRAME_BC_HIGH: u32 = 0x1001C;
pub(crate) const REG_BACKPLANE_WAKEUP_CTRL: u32 = 0x1001E; pub(crate) const REG_BACKPLANE_WAKEUP_CTRL: u32 = 0x1001E;
pub(crate) const REG_BACKPLANE_SLEEP_CSR: u32 = 0x1001F; pub(crate) const REG_BACKPLANE_SLEEP_CSR: u32 = 0x1001F;
pub(crate) const I_HMB_SW_MASK: u32 = (0x000000f0); pub(crate) const I_HMB_SW_MASK: u32 = 0x000000f0;
pub(crate) const I_HMB_FC_CHANGE: u32 = (1 << 5); pub(crate) const I_HMB_FC_CHANGE: u32 = 1 << 5;
pub(crate) const SDIO_INT_STATUS: u32 = 0x20; pub(crate) const SDIO_INT_STATUS: u32 = 0x20;
pub(crate) const SDIO_INT_HOST_MASK: u32 = 0x24; pub(crate) const SDIO_INT_HOST_MASK: u32 = 0x24;
@ -142,18 +142,6 @@ pub(crate) const MAX_PSK_LEN: usize = 64;
// Bluetooth constants. // Bluetooth constants.
pub(crate) const SPI_RESP_DELAY_F1: u32 = 0x001d; pub(crate) const SPI_RESP_DELAY_F1: u32 = 0x001d;
pub(crate) const WHD_BUS_SPI_BACKPLANE_READ_PADD_SIZE: u8 = 4; pub(crate) const WHD_BUS_SPI_BACKPLANE_READ_PADD_SIZE: u8 = 4;
pub(crate) const CYW43_BACKPLANE_READ_PAD_LEN_BYTES: u8 = 16;
pub(crate) const BTFW_ADDR_MODE_UNKNOWN: i32 = 0;
pub(crate) const BTFW_ADDR_MODE_EXTENDED: i32 = 1;
pub(crate) const BTFW_ADDR_MODE_SEGMENT: i32 = 2;
pub(crate) const BTFW_ADDR_MODE_LINEAR32: i32 = 3;
pub(crate) const BTFW_HEX_LINE_TYPE_DATA: u8 = 0;
pub(crate) const BTFW_HEX_LINE_TYPE_END_OF_DATA: u8 = 1;
pub(crate) const BTFW_HEX_LINE_TYPE_EXTENDED_SEGMENT_ADDRESS: u8 = 2;
pub(crate) const BTFW_HEX_LINE_TYPE_EXTENDED_ADDRESS: u8 = 4;
pub(crate) const BTFW_HEX_LINE_TYPE_ABSOLUTE_32BIT_ADDRESS: u8 = 5;
pub(crate) const BT2WLAN_PWRUP_WAKE: u32 = 3; pub(crate) const BT2WLAN_PWRUP_WAKE: u32 = 3;
pub(crate) const BT2WLAN_PWRUP_ADDR: u32 = 0x640894; pub(crate) const BT2WLAN_PWRUP_ADDR: u32 = 0x640894;
@ -162,11 +150,11 @@ pub(crate) const BT_CTRL_REG_ADDR: u32 = 0x18000c7c;
pub(crate) const HOST_CTRL_REG_ADDR: u32 = 0x18000d6c; pub(crate) const HOST_CTRL_REG_ADDR: u32 = 0x18000d6c;
pub(crate) const WLAN_RAM_BASE_REG_ADDR: u32 = 0x18000d68; pub(crate) const WLAN_RAM_BASE_REG_ADDR: u32 = 0x18000d68;
pub(crate) const BTSDIO_REG_DATA_VALID_BITMASK: u32 = (1 << 1); pub(crate) const BTSDIO_REG_DATA_VALID_BITMASK: u32 = 1 << 1;
pub(crate) const BTSDIO_REG_BT_AWAKE_BITMASK: u32 = (1 << 8); pub(crate) const BTSDIO_REG_BT_AWAKE_BITMASK: u32 = 1 << 8;
pub(crate) const BTSDIO_REG_WAKE_BT_BITMASK: u32 = (1 << 17); pub(crate) const BTSDIO_REG_WAKE_BT_BITMASK: u32 = 1 << 17;
pub(crate) const BTSDIO_REG_SW_RDY_BITMASK: u32 = (1 << 24); pub(crate) const BTSDIO_REG_SW_RDY_BITMASK: u32 = 1 << 24;
pub(crate) const BTSDIO_REG_FW_RDY_BITMASK: u32 = (1 << 24); pub(crate) const BTSDIO_REG_FW_RDY_BITMASK: u32 = 1 << 24;
// Security type (authentication and encryption types are combined using bit mask) // Security type (authentication and encryption types are combined using bit mask)
#[allow(non_camel_case_types)] #[allow(non_camel_case_types)]